Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

Abstract: An operating system is configured to receive a request to store an object that does not specify the location at which the object should be stored. The request might also include an optimization factor and one or more object location factors. The operating system might also generate object location factors or retrieve object location factors from one or more external locations. Object location factors might also be utilized that are based upon properties of the object to be stored. Utilizing the object location factors, and the optimization factor if provided, the operating system dynamically selects an appropriate storage tier for storing the object. The tiers might include a local storage tier, a local network storage tier, a remote network storage tier, and other types of storage tiers. The object is then stored on the selected storage tier. The object may be retrieved from the storage tier at a later time.

Abstract: Sharing tasks among compute units in a processor can increase the efficiency of the processor. When a compute unit does not have a task in its task memory to perform, donating tasks from other compute units can prevent the compute unit from being idle while there is task in other parts of the processor. It is desirable to share tasks among compute units that are within defined scopes of the processor. Compute units may share tasks by allowing other compute units to access their private memory, or by donating tasks to a shared memory.

Abstract: Systems, methods, and other embodiments associated with controlling when data blocks are cached at hosts from a shared storage are described. According to one embodiment, an apparatus includes a request logic configured to receive, from a first host of a plurality of hosts, a request to cache a data block at the first host. The data block is part of a plurality of data blocks that are stored in a network storage. The network storage is shared by the plurality of hosts. The apparatus also includes a lock logic configured to control access to the data block by issuing a lock for the data block identified by the request in response to determining that the data block is available. The lock provides exclusive access to the data block for the first host to permit the first host to cache the data block locally at the first host.

Abstract: Techniques for maintaining consistent replicas of data are disclosed. By way of example, a method for managing copies of objects within caches, in a system including multiple caches, includes the following steps. Consistent copies of objects are maintained within the caches. A home cache for each object is maintained, wherein the home cache maintains information identifying other caches likely containing a copy of the object. In response to a request to update an object, the home cache for the object is contacted to identify other caches which might have copies of the object.

Abstract: Methods and systems to identify and migrate threads among system nodes based on system performance metrics. An example method disclosed herein includes sampling a performance metric of a computer program thread, the computer program thread executing on a home node of a computer system having multiple nodes, and determining whether the performance metric exceeds a threshold value. The method also includes identifying a remote node associated with a remote memory if the threshold value is exceeded, the remote memory being accessed by the computer program thread, and identifying the computer program thread as a candidate for migration from the home node to the remote node if the threshold value is exceeded. In this way, a computer program thread that frequently accesses a remote memory can be migrated from a home node to a remote node associated with the remote memory to reduce the latency associated with memory accesses performed by the computer program thread and thereby improve system performance.

Abstract: Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.

Abstract: A method, article of manufacture, and apparatus for transferring data from a source tier to a target tier. In some embodiments, this may include dividing an object stored in the source tier into a plurality of segments, determining if the target tier is missing at least one of the segments, writing the missing segments to the target tier, and deleting the object from the source tier. In some embodiments, the object's metadata is updated to indicate that the object is in the target tier.

Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache, including considering an Input/Output Performance (IOP) metric, a bandwidth metric, and a garbage collection metric, and a whole data segment is promoted containing the one of the partial data segments to both the lower and higher levels of cache.

Abstract: A method and apparatus for optimizing weak atomicity overhead is herein described. A state table is maintained either during static or dynamic compilation of code to track data non-transactionally accessed. Within execution of a transaction, such as at transactional memory accesses or within a commit function, it is determined if data associated with memory access within the transaction is to be conflictingly accessed outside the transaction from the state table. If the data is not accessed outside the transaction, then the transaction potentially commits without weak atomicity safety mechanisms, such as privatization. Furthermore, even if data is accessed outside the transaction, optimized safety mechanisms may be performed to ensure isolation between the potentially conflicting accesses, while eliding the mechanisms for data not accessed outside the transaction.

Abstract: A method for execution by a storage unit in a directory-less distributed storage network (DSN) begins by receiving a read request regarding a data segment of data. The method continues by determining, based on the read request, whether an encoded data slice of a set of encoded data slices is locally stored, wherein the data segment was dispersed storage error encoded to produce the set of encoded data slices. When the encoded data slices are locally stored, the method continues by generating a read response. The method continues by determining whether to forward the read request to another storage unit of the directory-less DSN. When the read request is to be forwarded, the method continues by identifying one or more storage units to which the read request is to be forwarded and the read request is then forwarded to the one or more identified storage units.

Abstract: Disclosed is an improved approach to implement I/O and storage device management in a virtualization environment. According to some approaches, a Service VM is employed to control and manage any type of storage device, including directly attached storage in addition to networked and cloud storage. The Service VM implements the Storage Controller logic in the user space, and can be migrated as needed from one node to another. IP-based requests are used to send I/O request to the Service VMs. The Service VM can directly implement storage and I/O optimizations within the direct data access path, without the need for add-on products.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: Embodiments of the present invention include methods and systems for accelerated application startup. A method for accelerating startup of an application is provided. The method includes persistently storing a number of uniform resource locator (URL) hostnames based on one or more hostname requests made by one or more users during use of the application. The method further includes, upon startup of the application, making a DNS lookup call for at least one of the stored hostnames prior to a hostname request initiated by the application, wherein a resolution result for at least one of the stored hostnames is cached in the operating system DNS cache in preparation for the hostname request. A system for accelerating startup of an application is provided. The system includes a hostname storage device, a DNS pre-fetcher and a startup DNS pre-cacher.

Abstract: A method for accessing data in a directory-less dispersed storage (DS) network. In various embodiments, the method begins when a DS processing unit receives a read request for data stored in accordance with a dispersed storage error encoding function. Estimated storage metadata is determined based on the identity of the data, the identity of the requesting unit, and data storage preferences of the requesting unit. The estimated storage metadata is used to determine a target set of storage units. Next, a retrieval request is sent to one or more storage units of the target set. If a favorable response is received (e.g., a read threshold number of storage units return encoded data slices), the data is decoded and forwarded to the requestor. Otherwise, the storage metadata is re-estimated and used to determine a second target set of storage units for solicitation. This process continues until a favorable response is received.

Abstract: A network storage appliance is disclosed. The storage appliance includes a port combiner that provides data communication between at least first, second, and third I/O ports; a storage controller that controls storage devices and includes the first I/O port; a server having the second I/O port; and an I/O connector for networking the third I/O port to the port combiner. A single chassis encloses the port combiner, storage controller, and server, and the I/O connector is affixed on the storage appliance. The third I/O port is external to the chassis and is not enclosed therein. In various embodiments, the port combiner comprises a FiberChannel hub comprising a series of loop resiliency circuits, or a FiberChannel, Ethernet, or Infiniband switch. In one embodiment, the port combiner, I/O ports, and server are all comprised in a single blade module for plugging into a backplane of the chassis.

Abstract: A storage system uses a block-level file system to manage physical storage of data blocks of logical units, the file system being mounted on an owning one of a set of storage processors. The storage processors redirect received storage requests to the owning storage processor, and periodically the amount of redirection is evaluated. If the amount of redirection is higher than a threshold, then the file system is dismounted at the owning storage processor and mounted at another storage processor to reduce the amount of redirection.

Abstract: Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

Abstract: A system for storing files comprises a processor and a memory. The processor is configured to break a file into one or more segments; store the one or more segments in a first storage unit; and add metadata to the first storage unit so that the file can be accessed independent of a second storage unit, wherein a single namespace enables access for files stored in the first storage unit and the second storage unit. The memory is coupled to the processor and configured to provide the processor with instructions.

Abstract: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

Abstract: An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.

Abstract: An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a plurality of threads.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).

Abstract: A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.

Abstract: A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively; an address collision detection unit detecting collision between addresses in which the first and second CPUs respectively read and write the data signal from and to the dual port RAM; a first storage unit storing the data signal read by the first CPU; a second storage unit storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM when the collision between the addresses is detected; and a switching unit switching a reading source outputting the data signal to the port to which the first CPU is connected and outputting the read data signal to the first CPU entering a readable state.

Abstract: A data processing system includes a host device including a first working memory and a data storage device suitable for responding to an access request from the host device. The data storage device includes a controller suitable for controlling an operation of the data storage device, a second working memory suitable for storing data used for driving of the controller, and an access controller suitable for accessing a shared memory region of the first working memory under the control of the controller.

Abstract: Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.

Abstract: Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.

Abstract: One embodiment of the present invention sets forth a hybrid memory module that combines memory devices of different types while presenting a single technology interface. The hybrid memory module includes a number of super-stacks and a first interface configured to transmit data between the super-stacks and a memory controller. Each super-stack includes a number of sub-stacks, a super-controller configured to control the sub-stacks, and a second interface configured to transmit data between the sub-stacks and the first interface. Combining memory devices of different types allows utilizing the favorable properties of each type of the memory devices, while hiding their unfavorable properties from the memory controller.

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract: A memory system, including a plurality of stacked slices and a controller electrically coupled to the plurality of slices, includes: the plurality of slices configured to share a command in a preset number unit, wherein a slice performs a data input/output operation; and the controller configured to generate the command and a control signal for selecting slices in the preset number unit from the plurality of slices.

Abstract: An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

Abstract: The present invention provides an approach for automatic storage planning and provisioning within a clustered computing environment (e.g., a cloud computing environment). The present invention will receive planning input for a set of storage area network volume controllers (SVCs), the planning input indicating a potential load on the SVCs and its associated components. Configuration data for a set of storage components (i.e., the set of SVCs, a set of managed disk (Mdisk) groups associated with the set of SVCs, and a set of backend storage systems) will also be collected. Based on this configuration data, the set of storage components will be filtered to identify candidate storage components capable of addressing the potential load. Then, performance data for the candidate storage components will be analyzed to identify an SVC and an Mdisk group to address the potential load.

Abstract: An information processing system includes: CPUs; storage devices; switches; dummy storage devices which are with respective storage devices and each of which sends, when receiving an identifying information request, its own identifying information back to a sender of the identifying information request; and dummy CPUs which are associated with respective CPUs and each of which tries to, when receiving an instruction for acquiring identifying information from a dummy storage device, acquire the identifying information of the dummy storage device by transmitting the identifying information request, and sends the identifying information as response information back to a sender device of the acquiring instruction.

Abstract: Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices.

Abstract: A method of servicing a command sent from a host device file system (HDFS) within a host device (HD) by a local storage device (LSD) in communication with the HD is described. The method includes receiving a first command at the LSD instructing the LSD to execute an operation on associated logical addresses. If the first command is associated with at least a first set of logical addresses, the method includes servicing the first command by the LSD at least by way of sending a second command to a device (RD) external to the LSD that instructs the RD to execute an operation on memory locations within the RD. If the first command is not associated with the first set of logical addresses, the method includes servicing the first command by the LSD only by way of operations executed by the LSD on memory locations within the LSD.

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract: Memory is dynamically switched through the optical-switching fabric using at least one communication pattern to transfer memory space in the memory blades from one processor to an alternative processor in the processor blades without physically copying data in the memory to the processors. Various communication patterns for the dynamically switching are supported.

Abstract: Memory is dynamically switched through the optical-switching fabric using at least one communication pattern to transfer memory space in the memory blades from one processor to an alternative processor in the processor blades without physically copying data in the memory to the processors. Various communication patterns for the dynamically switching are supported.

Abstract: A method begins by processing module determining data to migrate, wherein the data is stored as a plurality of sets of encoded data slices in a first set of dispersed storage (DS) units. The method continues with the processing module retrieving at least a read threshold number of encoded data slices for each set of the plurality of sets of encoded data slices and dispersed storage error decoding the at least the read threshold number of encoded data slices in accordance with error coding dispersal storage function parameters to reproduce the data. The method continues with the processing module dispersed storage error encoding the data in accordance with second error coding dispersal storage function parameters to produce a plurality of sets of second encoded data slices and sending at least a write threshold number of second encoded data slices to a second set of DS units for storage therein.

Abstract: A storage device and memory accessing method configure two separate memory units, each with dedicated I/O channel, accessible by two controllers, each corresponding to an interface connected to a host, and allows the storage device to establish at least two connections to the different hosts. As more than one connection is established between the storage device and the hosts at the same time, a first controller has both read and write accessibility to a first memory unit and a second controller has both read and write accessibility to a second memory unit, while the first controller has read-only accessibility to the second memory unit and the second controller has read-only accessibility to the second memory unit.

Abstract: A storage layer is configured to implement efficient open-close consistency operations. Open close consistency may comprise preserving the original state of a file until the file is closed. The storage layer may be configured to clone a file in response to a file open request. Cloning the file may comprise referencing file data by two separate sets of identifiers. One set may be configured to reflect file modifications, and the other set may be configured to preserve the original state of the file. Subsequent operations configured to modify the file may be performed in reference to one of the sets of identifiers, while the storage layer provides access to the unmodified file through the other set of identifiers. Closing the file may comprise merging the sets of identifiers according to a merge policy.

Abstract: Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

Abstract: An event recorder includes an outer case, and a first memory module including a first amount of data storage capacity contained within the outer case. The first memory module is configured to receive and store multiple types of data including at least two of: video data; audio data; locomotive data indicative of one or more locomotive operating parameters, locomotive control signals, and locomotive performance characteristics; engine operating parameter data; exhaust characteristics data; electrical data; and positive train control data. A controller contained within the outer case may be configured to associate a universal time stamp with each of the multiple types of data stored in the first memory module. An inner, crash-hardened case may be contained within the outer case, containing a second memory module including a second amount of data storage capacity that is smaller than the first amount.

Abstract: A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for example). The storage system has a function for adding a virtual port to a physical port. The storage system migrates the virtual port addition destination from a first physical port to a second physical port and transmits a request of a predetermined type which includes identification information on the virtual port of the migration target to the switch unit. The transfer management information is updated by the update function of the switch unit so that the transfer destination which corresponds with the migration target virtual port is the switch port connected to the second physical port.

Abstract: The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.

Abstract: A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.

Abstract: A memory controller is coupled to a memory device including a first block and a second block and includes a first register module, a first execution unit and a second register module. The first register module includes a plurality of set registers to store a first configuration file and a second configuration file. The first execution unit computes data stored in the first block simultaneously according to the first and the second configuration files to generate a first computation result and a computation operation result. The second register module includes a plurality of result registers to store the first and the second computation results.

Abstract: A memory controller receives memory access requests from a host terminal, the memory access requests from the host terminal including one or both of host read requests and host write requests. The memory controller generates memory access requests. Priorities are assigned to the memory access requests. The memory access requests are segregated to memory unit queues of at least one set of memory unit queues, the set of memory unit queues associated with a memory unit. Each memory access request is sent to the memory unit according to a priority and an assigned memory unit queue of the memory access request.

Abstract: An embodiment of this invention is an information storage system comprising a plurality of storage systems connected to be able to communicate. Each of the plurality of storage systems includes default storage system identification information which is the same to the plurality of storage systems, common volume identification information for uniquely identifying volumes provided by the plurality of storage systems to a host computer among the plurality of storage systems, and a controller configured to return the default storage system identification information to the host computer in response to a request from the host computer and to process a read or write request to a volume accompanying the common volume identification information from the host computer.