Simultaneous Access Regulation Patents (Class 711/150)
  • Patent number: 11169808
    Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 9, 2021
    Assignee: Kalray
    Inventors: Benoit Dupont de Dinechin, Julien Le Maire, Nicolas Brunie
  • Patent number: 11169972
    Abstract: A technique to name data is disclosed to allow preservation of storage efficiency over a link between a source and a destination in a replication relationship as well as in storage at the destination. The technique allows the source to send named data to the destination once and refer to it by name multiple times in the future, without having to resend the data. The technique also allows the transmission of data extents to be decoupled from the logical containers that refer to the data extents. Additionally, the technique allows a replication system to accommodate different extent sizes between replication source and destination while preserving storage efficiency.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 9, 2021
    Assignee: NetApp Inc.
    Inventors: Blake Lewis, John K. Edwards, Vijay Deshmukh, Kapil Kumar, Rajesh Desai
  • Patent number: 11079945
    Abstract: A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 3, 2021
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Omer Irshad, Joohyun Lee
  • Patent number: 11080064
    Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Giora Biran, Fadi Y. Busaba, Ophir Erez, Mark S. Farrell, Lisa C. Heller, Christian Jacobi, Alexander Mesh, Timothy J. Slegel
  • Patent number: 11061680
    Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Giora Biran, Fadi Y. Busaba, Ophir Erez, Mark S. Farrell, Lisa C. Heller, Christian Jacobi, Alexander Mesh, Timothy J. Slegel
  • Patent number: 10929033
    Abstract: A method includes receiving an indication of an operational mode for a memory system including a set of memory devices. A first memory device of the set of memory devices includes a first media having a first media type and a second memory device of the et of memory devices includes a second media having a second media type that is different than the first media type. The method also includes allocating, by a processing device, a first portion and a second portion of the first memory device based on the operational mode for the memory system. The method also includes storing data at the first portion of the first memory device, the second portion of the first memory device, or the second memory device based on the operational mode for the memory system.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 23, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: James H. Meeker, Michael B. Danielson, Paul A. Suhler
  • Patent number: 10904536
    Abstract: Provided are a frame processing method and device for use in image processing. The method includes: receiving a first frame by a first processing unit; sending, by the first processing unit and before receiving a second frame processed with a third processing unit, the first frame to a second processing unit, followed by processing the first frame with the second processing unit or processing the first frame with the second processing unit and another processing unit; and receiving a third frame by the first processing unit before the first processing unit receives the first frame processed with the second processing unit or the first frame processed with the second processing unit and the other processing unit. The method precludes frame hysteresis, at a fixed frame rate and with invariable frame processability of each frame.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 26, 2021
    Assignee: ArcSoft Corporation Limited
    Inventors: Muhuo Li, Jin Wang
  • Patent number: 10902324
    Abstract: Systems for distributed data storage. A method embodiment commences upon capturing a history of storage I/O activity over a recent time period. A predictive model is derived from the captured storage I/O activity, and the predictive model is then used for predicting future storage I/O activity. A set of snapshot planning parameters comprising objectives (e.g., to minimize costs or to maximize likelihood completing a snapshot activity by a prescribed time) and/or constraints (e.g., don't wait more than one day to start a snapshot) are applied to the predicted storage I/O characteristics to generate a set of feasible snapshot plans. One of the feasible snapshot plans is selected for scheduling so as to begin the planned snapshot activity at a prescribed time. The snapshot planning parameters are normalized based on the predicted storage I/O characteristics.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 26, 2021
    Assignee: Nutanix, Inc.
    Inventors: Bharat Kumar Beedu, Abhinay Nagpal, Himanshu Shukla
  • Patent number: 10891232
    Abstract: Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin Lopes, Deanna P. D. Berger, Jason D Kohl, Robert J Sonnelitter, III
  • Patent number: 10884742
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10877762
    Abstract: A microprocessor includes: a first memory bus; a second memory bus; a fetch part configured to fetch an instruction from a first memory connected to the first memory bus; a bus controller configured to control the second memory bus; a determination part configured to determine whether or not an address output from the bus controller is in an area of the first memory; and a first logic circuit part configured to use an output of the determination part to set an access destination of the first memory as the bus controller when the address output from the bus controller is in the area of the first memory.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 29, 2020
    Assignee: Rohm Co., Ltd.
    Inventor: Takahiro Nishiyama
  • Patent number: 10866747
    Abstract: An arrangement for securing a memory device of a computing system in which a memory access command is compared to each command in a list of commands. The command, with specified attributes, is authenticated when the command and its attributes match an entry in the list of commands. Following authentication, the command is evaluated according to usage and behavior metrics in order to identify and prevent unauthorized or malicious access of the memory device. If no violation of usage or behavior metrics is detected, the command may be issued to the memory device for execution.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 15, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sukhamoy Som, David F. Heinrich, Theodore F. Emerson
  • Patent number: 10853200
    Abstract: In one aspect, IO recovery mechanisms in active/active replication for storage clusters provide, for each write IO request: determining an extent of pages to be modified; acquiring a lock by a cluster local to the request and locally persisting data; atomically creating an entry in a local journal; and sending, by the local cluster, a data write request to a peer cluster. Upon receiving acknowledgement from the peer cluster of successful transmission, the replication journal entry is cleared, the extent is unlocked, and a notification is returned to the peer. In response to a failure event at the peer cluster after persisting the data at the local cluster and creating the journal entry at the local cluster, an aspect includes sending, to the peer cluster upon recovery of the peer cluster, the journal entry with respect to an extent corresponding to a time of the failure event.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiangping Chen, Ying Hu, David Meiri
  • Patent number: 10838868
    Abstract: Embodiments for implementing a communicating memory between a plurality of computing components are provided. In one embodiment, an apparatus comprises a plurality of memory components residing on a processing chip, the plurality of memory components interconnected between a plurality of processing elements of at least one processing core of the processing chip and at least one external memory component external to the processing chip. The apparatus further comprises a plurality of load agents and a plurality of store agents on the processing chip, each interfacing with the plurality of memory components. Each of the plurality of load agents and the plurality of store agents execute an independent program specifying a destination of data transacted between the plurality of memory components, the at least one external memory component, and the plurality of processing elements.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Jungwook Choi, Brian Curran, Bruce Fleischer, Kailash Gopalakrishan, Jinwook Oh, Sunil K Shukla, Vijayalakshmi Srinivasan, Swagath Venkataramani
  • Patent number: 10812567
    Abstract: A system and method are presented for the facilitation of threaded download of software record identifiers and software records. Software record identifiers and software records are stored in separate one-dimensional stacks, which stacks feed a plurality of download threads in a first-in, first-out method. Software records and/or software record identifiers may optionally be written in parallel, or in an asynchronous manner. The total number of threads allowed to a user may optionally be limited to a pre-set number. The speed and efficiency of downloading records is increased through use of all of the cores of multi-cored computing systems to substantively concurrently download several threads. The method further allows a failed download thread to restart from the point at which it failed, rather than beginning again from the origin of the thread, thus ensuring that no software records are duplicated, and that no software records are skipped within a download thread.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 20, 2020
    Inventors: Richard Banister, William Dubberley
  • Patent number: 10769068
    Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. Matsakis, Craig R. Walters, Jane H. Bartik, Chung-Lung K. Shum, Elpida Tzortzatos
  • Patent number: 10768962
    Abstract: A method of emulating nested page table (NPT) mode-based execute control in a virtualized computing system includes: providing NPT mode-based execute control from a hypervisor to a virtual machine (VM) executing in the virtualized computing system; generating a plurality of shadow NPT hierarchies at the hypervisor based on an NPT mode-based execute policy obtained from the VM; configuring a processor of the virtualized computing system to exit from the VM to the hypervisor in response to an escalation from a user privilege level to a supervisor privilege level caused by guest code of the VM; and exposing a first shadow NPT hierarchy of the plurality of shadow NPT hierarchies to the processor in response to an exit from the VM to the hypervisor due to the escalation from the user privilege level to the supervisor privilege level.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 8, 2020
    Assignee: VMware, Inc.
    Inventors: David Dunn, Doug Covelli
  • Patent number: 10740106
    Abstract: A transactional memory system determines whether a hardware transaction can be salvaged. A processor of the transactional memory system begins execution of a transaction in a transactional memory environment. Based on detection that an amount of available resource for transactional execution is below a predetermined threshold level, the processor determines whether the transaction can be salvaged. Based on determining that the transaction can not be salvaged, the processor aborts the transaction. Based on determining the transaction can be salvaged, the processor performs a salvage operation, wherein the salvage operation comprises one or more of: determining that the transaction can be brought to a stable state without exceeding the amount of available resource for transactional execution, and bringing the transaction to a stable state; and determining that a resource can be made available, and making the resource available.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura
  • Patent number: 10716122
    Abstract: When a radio bearer for sending packets to a UE is split between master and secondary network nodes, then based on relative network conditions (such as relative link quality in view of latency targets or other conditions that reflect user-plane loading) between that master and secondary network nodes a redundancy retransmission mode may be selected from among multiple redundancy retransmission modes. Each of these redundancy retransmission modes define a different protocol for retransmitting multiple copies of selected ones of the packets to the UE over the split radio bearer. These multiple copies are then wirelessly retransmitted to the UE over the split radio bearer according to the selected redundancy retransmission mode. In one example there are 4 possible modes and different modes retransmit PDCP PDUs versus RLC PDUs; in one mode the master and secondary network nodes both perform retransmissions of the identical selected packets.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: July 14, 2020
    Assignee: Nokia Technologies Oy
    Inventors: Reza Holakouei, Venkatkumar Venkatasubramanian
  • Patent number: 10698813
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Patent number: 10642531
    Abstract: A method of operating a host includes defining transaction identifications for each one of multiple transactions in a multi-transaction, thereafter communicating atomic write data related to each transaction to a data storage device using the transaction ID, and storing the atomic write data in the data storage device using the transaction ID and an identifier.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In Sung Song, Sang Hoon Choi, Moon Sang Kwon, Hyung Jin Im
  • Patent number: 10635316
    Abstract: Provided herein are methods and systems for improved storage strategies for use of collections of storage resources, such as solid state drives, including in connection with a converged networking and storage node that may be used for virtualization of a collection of physically attached and/or network-connected storage resources.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 28, 2020
    Assignee: Diamanti, Inc.
    Inventors: Abhay Kumar Singh, Sambasiva Rao Bandarupalli, Gopal Sharma, Jeffrey Chou
  • Patent number: 10599589
    Abstract: According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 24, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Kurafuji
  • Patent number: 10565131
    Abstract: Disclosed is a main memory capable of speeding up a hardware accelerator and saving memory space. The main memory according to the present disclosure is at least temporarily implemented by a computer and includes a memory, and an accelerator responsible for performing an operation for hardware acceleration while sharing the storage space of a host processor and the memory.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 18, 2020
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Eui Young Chung, Hyeok Jun Seo, Sang Woo Han
  • Patent number: 10521116
    Abstract: A system and method include receiving, by an object store virtual machine of a virtual object storage system, a user request for updating an element of an object store. The user request includes a first compare and swap value. The system and method also include updating the first compare and swap value from the second user request for obtaining an updated compare and swap value, comparing the updated compare and swap value with a current compare and swap value of the element, and updating the element upon determining that the updated compare and swap value is greater than the current swap and compare value. Updating the element comprises one of creating a new version of the element and overwriting a previous version of the element. The system and method further include replacing the current compare and swap value with the updated compare and swap value.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 31, 2019
    Assignee: NUTANIX, INC.
    Inventor: Ranjan Parthasarathy
  • Patent number: 10496406
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10452655
    Abstract: Techniques are provided herein for processing a query using in-memory cursor duration temporary tables. The techniques involve storing a part of the temporary table in memory of nodes in a database cluster. A part of the temporary table may be stored in disk segments of nodes in the database cluster. Writer threads running on a particular node writes data for the temporary table to the memory of the particular node. Excess data may be written to the disk segment of the particular node. Reader threads running on the particular node reads data for the temporary table from the memory of the particular node and the disk segment of the particular node.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 22, 2019
    Assignee: Oracle International Corporation
    Inventors: Janaki Latha Lahorani, You Jung Kim, Andrew Witkowski, Sankar Subramanian
  • Patent number: 10437726
    Abstract: Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10423603
    Abstract: A method includes determining, by a processor, whether a program check condition exists. The method further includes determining, by the processor, whether a lock descriptor of a lock in a file lock table satisfies an unlocking condition. The method further includes releasing, by the processor, the lock by setting the lock descriptor's host identifier as zero. The method further includes determining, by the processor, whether any lock in the file lock table satisfies a lock conflict condition. The method further includes determining, by the processor, whether the file lock table includes any lock descriptor that satisfies a locking condition. The method further includes creating, by the processor, a new lock using the lock descriptor that satisfies the locking condition.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: September 24, 2019
    Assignee: Unisys Corporation
    Inventors: Michael C Otto, Carl R Crandall, Forest F Crocker, Lnda J Brock, Douglas A Fuller, Michael J Rieschl
  • Patent number: 10409598
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10394760
    Abstract: Systems and methods are disclosed for backing up data in a computing system including a controller configured to backup a file in the non-volatile memory at least in part by receiving the file from a host, the file including a plurality of chunks of data and storing the plurality of chunks of data in a browsable partition of the non-volatile memory in response to said receiving the file. The controller further determines that one or more of the plurality of chunks has been modified, determine a new chunk associated with each of the one or more modified chunks, store the one or more new chunks in the browsable partition of the non-volatile memory using the communication interface in response to said determination of the one or more new chunks and store the one or more modified chunks in a container partition of the non-volatile memory using the communication interface.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: August 27, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Linh Kochan, Shawn Miller, Michael A. Dolan, Sean Rohr
  • Patent number: 10348348
    Abstract: A system includes a processor configured to route a telematics message to all networks not pre-identified as backbone networks in response to a directionality bit, included in a CAN identifier, indicating non-backbone routing. The processor is also configured to route the telematics message to any pre-identified backbone networks in response to the directionality bit indicating backbone routing.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 9, 2019
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Sangeetha Sangameswaran, Jason Michael Miller, Eric Ramsay Paton, John William Schmotzer
  • Patent number: 10296629
    Abstract: A method, system, and computer program product is disclosed for interacting with a client supported by a client-side cache. Embodiments of a method, a system, and a computer program product are disclosed that retrieve a first snapshot, indicating a state of the database after a last database request by the client, associated with the client, determine any number of invalid cached results for the client based on the first snapshot, and transmit the any number of invalid cached results and a second snapshot, an update for the first snapshot.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 21, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Lakshminarayanan Chidambaran, Mehul Dilip Bastawala, Srinath Krishnaswamy, Tirthankar Lahiri, Juan R. Loaiza, Bipul Sinha, Srinivas S. Vemuri
  • Patent number: 10241941
    Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Joachim Fader, Stephan M. Herrmann, Amit Jindal, Nitin Singh
  • Patent number: 10228858
    Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 12, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventors: Timothy Stoakes, Vikas Ratna, Amit Garg
  • Patent number: 10229070
    Abstract: A computer-implemented method for encoding an application memory that a program, executed on a computer, has access to, using a shadow memory corresponding to the application memory, the method comprises: creating and initializing a shadow memory divided into segments, each segment in the application memory being mapped to a corresponding segment in the shadow memory, for each memory block in the application memory that the program allocates, encoding a corresponding shadow memory block, in the shadow memory, by: defining a meta segment preceding the first segment of the memory block in the application memory, and a corresponding shadow meta segment in the shadow memory block, writing in the shadow meta segment a first value indicative of the size of the memory block, writing, in each subsequent segment of the shadow memory block, a second value indicative of the offset between the segment and the first segment of the shadow memory block.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 12, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Kostyantyn Vorobyov, Nikolay Kosmatov, Julien Signoles
  • Patent number: 10162530
    Abstract: A computer coupled to an external apparatus via an I/O device comprising, a control unit configured to assign a command identifier to a command issued to the external apparatus, wherein the I/O device includes a collision detection unit defined a partial command identifier space which is a subspace of a command identifier space that is a set of a plurality of command identifiers, and wherein the collision detection unit is configured to: shift an arrangement of the partial command identifier space within the command identifier space; and determine whether or not the assigned command identifier collides with another command identifier that is in use.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: December 25, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Katsuto Sato, Yuki Kondoh
  • Patent number: 10156888
    Abstract: A method and apparatus are provided for controlling multiple processors in order to reduce current consumption in electronic device. An electronic device includes an application processor (AP) configured to control a plurality of functions; a communication processor (CP) electronically connected to the AP; and a sensor module or a communication module electronically connected to the CP. When the AP enters a sleep state, the CP is configured to control at least one function among the plurality of functions based on information collected from the sensor module or the communication module according to a discontinuous reception (DRX) operating period.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyoungjoo Lee, Taeyoon Kim, Mingyu Kang, Youngpo Lee, Chaiman Lim, Dukhyun Chang
  • Patent number: 10152267
    Abstract: In one embodiment, a method includes intercepting a write command to write to a volume at a production site, saving data from the write command to a cache, sending metadata from the write command to a data protection appliance (DPA), writing the data to the volume, receiving a request for the data in the cache, sending the data from cache to a data protection appliance (DPA) at the production site and sending the data from the DPA to the replication site.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 11, 2018
    Assignee: EMC CORPORATION
    Inventors: Lev Ayzenberg, Ran Goldschmidt, Assaf Natanzon
  • Patent number: 10146598
    Abstract: Technology for configuring a software job is described. An aspect of the technology involves receiving a software job including a plurality of events, each event including a request for processing, assigning the events to respective executors by matching the events with executor profiles, so that for each event the assigned executor is designated to perform the processing for the event, and selecting automatically an alternative executor to perform the processing for an event when the executor originally designated to perform the processing does not complete the processing.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: December 4, 2018
    Assignee: Google LLC
    Inventors: Jan-Simon Pendry, Robert Sidebotham
  • Patent number: 10133622
    Abstract: Disclosed herein are systems, methods, and software for enhancing error detection in data synchronization operations. In an implementation, log data reported by a device is received and incorporated into an event database indicating interleaved events related to data synchronization threads on the device. The event database is queried to extract a listing of events in the event database, the listing of events comprising events potentially associated with at least one error condition in the data synchronization threads. The listing of events is processed to identify one or more patterns from among the interleaved events that indicate the at least one error condition in the data synchronization threads. Responsive to identifying the one or more patterns, an indication of the at least one error condition in the data synchronization threads is communicated.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: November 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jack Allen Nichols, Ryan Gordon Zacher, György Keresztély Schadt, Rayyan Jaber, Erik Hampton Soderberg
  • Patent number: 10089227
    Abstract: A method for performing cache flushing operations in a data storage system can include maintaining a plurality of SSDs as a cache medium for a data storage medium, controlling a region of the SSDs in a write-back cache mode, and monitoring a status of the SSDs to detect a low-performance condition. In the write-back cache mode, data is mirrored across the SSDs. The method can also include performing normal purge operations on the data stored in the region under a condition that the low-performance condition is not detected, and performing aggressive purge operations on the data stored in the region in response to detecting the low-performance condition. The normal purge operations can include flushing the data stored in the region to the data storage medium. The aggressive purge operations can include sequentially mirroring the data stored in the region to one or more special territories of the data storage medium.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: October 2, 2018
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Srikumar Subramanian, Vijayarankan Muthirisavenugopal, Anandh Mahalingam, Narayanaswami Ganapathy
  • Patent number: 10073697
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10067763
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10055129
    Abstract: Threads using hardware transactions and executing instrumented critical sections that do not perform any writes may complete as long as the thread holding the lock has not yet executed its first write operation. If the thread executing the instrumented critical section performs any writes, or if the thread holding the lock performs any writes during its critical section, the hardware transaction may be aborted. A write flag may be used to determine whether the thread holding the lock performs any writes. The thread holding the lock may set the flag before performing any write operation. The thread executing the hardware transaction may subscribe to that flag and abort the transaction if the flag is set to true, indicating that the thread holding the lock performed a write operation.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 21, 2018
    Assignee: Oracle International Corporation
    Inventors: Alex Kogan, Yosef Lev
  • Patent number: 10003634
    Abstract: A system and method are presented for the facilitation of threaded download of software record identifiers and software records. Software record identifiers and software records are stored in separate one-dimensional stacks, which stacks feed a plurality of download threads in a first-in, first-out method. Software records and/or software record identifiers may optionally be written in parallel, or in an asynchronous manner. The total number of threads allowed to a user may optionally be limited to a pre-set number. The speed and efficiency of downloading records is increased through use of all of the cores of multi-cored computing systems to substantively concurrently download several threads. The method further allows a failed download thread to restart from the point at which it failed, rather than beginning again from the origin of the thread, thus ensuring that no software records are duplicated, and that no software records are skipped within a download thread.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: June 19, 2018
    Inventors: Richard Banister, William Dubberley
  • Patent number: 9934405
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu
  • Patent number: 9934404
    Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Amit Agarwal, Faraz Ahmad, Uma Maheswara R. Chandolu
  • Patent number: 9898420
    Abstract: An electronic device includes a memory protection unit configured to protect an access to a register of a device arranged in an address space. An operating system sets an access right to the register by using the memory protection unit. A process requests the operating system to operate the device when the process operates the device, and the operating system makes an access to the corresponding register in accordance with the request for the operation to operate the device.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: February 20, 2018
    Assignee: Yokogawa Electric Corporation
    Inventors: Kazuyuki Obara, Katsuhiko Toba
  • Patent number: 9892067
    Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M. Ambroladze, Deanna P. Berger, Michael Fee, Arthur J. O'Neill, Jr.