Abstract: A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components.

Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.

Abstract: Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.

Abstract: A storage apparatus includes a microprocessor package configured to access a logical volume and a local memory in the microprocessor package. An input/output (I/O) request range of one I/O request, including a start position address and an end position address of the logical volume which is a target of the one I/O request, is stored in the local memory. A counter value indicating a number of I/O requests to and from the logical volume associated with the one I/O request is acquired and stored in the local memory. If the counter value associated with the one I/O request is greater than the counter value associated with another I/O request, the I/O request ranges of the one I/O request and the other I/O request are compared. If there is no overlap between the I/O request ranges, the one I/O request is executed; otherwise, the one I/O request is placed on standby.

Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.

Abstract: A method and apparatus for utilizing hardware mechanisms of a transactional memory system is herein described. Various embodiments relate to software-based filtering of operations from read and write barriers and read isolation barriers during transactional execution. Other embodiments relate to software-implemented read barrier processing to accelerate strong atomicity. Other embodiments are also described and claimed.

Abstract: One embodiment of the present invention sets forth a technique for synchronization between two or more processors. The technique implements a spinlock acquire function and a spinlock release function. A processor executing the spinlock acquire function advantageously operates in a low power state while waiting for an opportunity to acquire spinlock. The spinlock acquire function configures a memory monitor to wake up the processor when spinlock is released by a different processor. The spinlock release function releases spinlock by clearing a lock variable and may clear a wait variable.

Abstract: An aspect of the present invention facilitates selecting suitable nodes to host virtual machines (VMs) in an environment containing a large number of nodes (such as a grid). In one embodiment, information indicating corresponding resources available in each machine node (a node capable of hosting VMs) in the grid is maintained distributed over a set of management nodes contained in the grid. On receiving an indication that a VM requiring a set of resources is sought to be hosted, a machine node having available the set of resources is identified based on the distributed information. The VM is then provisioned/hosted on the identified machine node. The maintenance of the resource availability information distributed across multiple management nodes enables the solution to be scaled for use in environments having a large number of nodes.

Abstract: According to one example embodiment, an arbiter is disclosed to mediate memory access requests from a plurality of processing elements. If two or more processing elements try to access data within the same word in a single memory bank, the arbiter permits some or all of the processing elements to access the word. If two or more processing elements try to access different data words in the same memory bank, the lowest-ordered processing element is granted access and the others are stalled.

Abstract: In order to properly use resources according to the application or search for available resources in an environment in which a block storage apparatus and a file storage apparatus coexist, knowledge and experience of applications and storage apparatuses, as well manpower were required.

Abstract: A system and method described herein allows a virtual tape library (VTL) to perform multiple simultaneous or parallel read/write or access sessions with disk drives or other storage media, particularly when subject to a sequential SCSI-compliant layer or traditional limitations of VTLs. In one embodiment, a virtualizing or transaction layer can establish multiple sessions with one or more clients to concurrently satisfy the read/write requests of those clients for physical storage resources. A table or other data structure tracks or maps the sessions associated with each client and the location of data on the physical storage devices.

Abstract: A backup and restoration process which first attempts to recover information blocks from locally connected information handling systems executing a backup/restore service before looking to the slower access cloud store to recover data blocks.

Abstract: A software transactional memory system is provided with multiple global version counters. The system assigns an affinity to one of the global version counters for each thread that executes transactions. Each thread maintains a local copy of the global version counters for use in validating read accesses of transactions. Each thread uses a corresponding affinitized global version counter to store version numbers of write accesses of executed transactions. The system adaptively changes the affinities of threads when data conflict or global version counter conflict is detected between threads.

Abstract: A data structure of readily accessible units of memory is provided as computer useable media having computer readable program code logic providing information tables and a software emulation program to enable hardware to run new software that uses transactional memory and a bit associated with a transaction for executing transactional memory constructs. The data structure with Guest PTRAN bit is used in emulation of software written for a given computer on a different computer which executes a different set of instructions. The emulating instructions are used to provide transactional memory instructions on a computer which does not support those instructions natively.

Abstract: An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running.

Abstract: According to one aspect of the present disclosure, a method and technique for input/output traffic backpressure prediction is disclosed. The method includes: performing a plurality of memory transactions; determining, for each memory transaction, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determining a median value based on the determined traffic values; determining whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicating a prediction of a backpressure condition.

Abstract: A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.

Abstract: Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Abstract: According to the embodiment, a nonvolatile semiconductor memory that includes a plurality of banks capable of operating in parallel, a command analyzing unit that, upon receiving a power management command from a host, analyzes the received power management command, and a recording control unit that dynamically and variably controls an upper limit of the number of banks to be operated in parallel at a time of writing in accordance with an analysis result by the command analyzing unit are included, thereby suppressing the upper limit of a power consumption in accordance with an instruction from the host.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: Disclosed is a dynamic load balancing system. The dynamic load balancing system includes a resource management master managing bare servers that do not execute services and having a hierarchical structure and a service master dynamically allocating the bare servers to a load balancing server or a service execution server or dynamically releasing the pre-allocated load balancing server or service execution server by the bare servers, in consideration of monitoring information on a state or performance of a server and service requirements to be provided.

Abstract: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device using a foreground process is performed. A persistent metadata bitmap, adapted to indicate whether the at least the portion of the data has been initialized, is staged to cache, the cache operable in the computing storage environment. The background process maintains a volatile bitmap indicating a status of the initialization of the at least the portion of the data in direct correspondence to the metadata bitmap. As the background process initializes the at least the portion of the data, an applicable bit on the persistent metadata bitmap is cleared and a corresponding bit is set on the volatile bitmap.

Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.

Abstract: The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A digital memory architecture for recognition and recall in support of a host comprises a plurality of pattern processors, each of which has its own random access memory (RAM) and controller, an external data bus and external data bus controller, a results bus and results bus controller, an internal data bus and internal data bus controller, and an external control bus and external control bus and controller. Each of the pattern processors may be a general purpose set theoretic processor (GPSTP) operating in interrupt and block modes.

Abstract: A system (10) for virtual disks version control includes a selectively read-only volume (12); at least one topmost overlay (141, 142, 143, 144, 145); and at least two intermediate, selectively read-only overlays (16, 16?, 16?, 16??) configured as at least two mounting points. The at least one topmost overlay (141, 142, 143, 144, 145) is configured to store the results of redirected write operations. One of the at least two mounting points (16, 16?, 16?, 16??) and the volume (12) form an image, and the other of the at least two mounting points (16, 16?, 16?, 16??) and the volume (12) form another image. The at least two intermediate overlays (16, 16?, 16?, 16??) are operatively located between the volume (12) and the at least one topmost overlay (141, 142, 143, 144, 145).

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: A computer implemented method for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG.

Abstract: Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.

Abstract: Disclosed is a method of synchronizing a plurality of processors accesses to at least one shared resource. One of a plurality of processors requests an exclusive region lock for a shared resource using a logical block address (LBA) of a dummy target. The LBA is defined in a region map that associates LBAs to shared resources. The exclusive region lock request is inserted as a node in a region lock tree of the dummy target. Access to the shared resource is granted based on a determination whether there is an existing region lock in the region lock tree that is overlaps with the new exclusive region lock request.

Abstract: In a multiprocessor data processing system having a distributed shared memory system, first and second nested memory transactions are executed, where the first memory transaction is a rewind-only transaction (ROT) and the second memory transaction is a non-ROT memory transaction. The first memory transaction has a transaction body including the second memory transaction and an additional plurality of transactional memory access instructions. In response to execution of the transactional memory access instructions, memory accesses are performed to the distributed shared memory system. Conflicts between memory accesses not within the first memory transaction and at least a load footprint of any of the transactional memory access instructions preceding the second memory transaction are not tracked.

Abstract: A storage system according to one embodiment includes a first storage tier; a second storage tier; logic for storing instances of a file in the first storage tier and the second storage tier; logic for receiving a request to access the file or instance thereof from a user in a group of users; logic for providing the user requesting access to the file with remote access to an instance of the file on the first storage tier that is not being used by any other user in the group of users; logic for setting an ownership status of the instance of the file on the first storage tier to owned by the user requesting access to the file; and logic for setting an ownership status of an unused instance of the file on the second storage tier from owned by the user requesting access to the file to unowned or owned by a second user which previously owned the instance of the file on the first storage tier. Additional systems, methods, and computer program products are also presented.

Abstract: After serially receiving several MSBs of the address, a microcontroller may determine whether a write operation is occurring in the same particular partition. If it is determined that a write operation is not occurring in the same partition, then the microcontroller may immediately perform the read operation. If a write operation is occurring, however, then the microcontroller may first begin to interrupt the write operation before beginning the read operation.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.

Abstract: A method and apparatus for detecting and preemptively ameliorating potential logic unit thrashing in a storage system having multiple I/O requesters is disclosed. In response to detecting that each of two requesters has usable access to both of the active-passive pair of controllers, one of the active-passive pair of controllers is selected to be designated as an active resource controller. In response to detecting that one of the two requesters has usable access to only one of the active-passive pair of controllers, only one of the active-passive pair of controllers is selected to be designated as an active resource controller. In response to detecting that each of the two requesters has usable access only to different ones of the active-passive pair of controllers, one of the active-passive pair of controllers is selected to be designated as an active resource controller.

Abstract: A storage apparatus and method configured to improve efficiency of data access utilizing dynamically adjusting storage zone boundary within a disk are disclosed. A process capable of implementing the flexible zone boundary, in one example, allocates a first zone of a first disk operable to store data. While the first zone can be referred to as a Redundant Array of Independent Disks 0 (“RAID 0”) zone, the implementation of RAID 0 can be carried out in the first zone. Upon allocating a second zone of the first disk operable to store secured data, the process allocates a third zone of the first disk wherein the storage boundary of the first zone can be dynamically expanded into the third zone in response to the availability of free storage capacity of the first zone of the first disk.

Abstract: System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

Abstract: A non-volatile memory device includes first and second memory regions to store data and a memory control unit. Each of the first and second memory regions is configured by a plurality of physical pages. Each of the physical pages is configured by a plurality of regions corresponding to a plurality of logical addresses. The memory control unit performs control of batch erasing and batch writing on every physical page. When a first physical page in the first memory region includes a first region corresponding to a first logical address, which is a target to be written, and when a second physical page in the second memory region includes a second region corresponding to the first logical address, which is a target to be written, the memory control unit selects either the first physical page or the second physical page as a physical page for writing.

Abstract: According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding data. The memory controller transfers data received from host equipment simultaneously to the first and second chips. The timer measures a lapse of preset shift time. The timer control unit starts writing of data into the second chip immediately after the lapse of the shift time.

Abstract: A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.

Abstract: A memory device loops back control information from one interface to another interface to facilitate sharing of the memory device by multiple devices. In some aspects, a memory controller sends control and address information to one interface of a memory device when accessing the memory device. The memory device may then loop back this control and address information to another interface that is used by another memory controller to access the memory device. The other memory controller may then use this information to determine how to access the memory device. In some aspects a memory device loops back arbitration information from one interface to another interface thereby enabling controller devices that are coupled to the memory device to control (e.g., schedule) accesses of the memory device.

Abstract: A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

Abstract: Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal.

Abstract: Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.

Abstract: A multi-user computer system and a remote control method for the multi-user computer system includes a remote controller, with an input unit that receives a remote-control password to remotely operate the computer, information on an OS booted when the remote-control password is input, a key input setting the computer in a mode wherein the remote-control password and the OS information are set, and a key input operating the computer, a microprocessor, a wireless transmitter, and a computer, with a wireless receiver, a microprocessor, and a BIOS that automatically loads an OS corresponding to the remote-control password stored in the memory when the received remote-control password stored in the wireless receiver and the remote-control password in the memory are the same.

Abstract: In one embodiment, a data migration technique enables a source storage system to efficiently and reliably migrate data to a destination storage system. The source storage system includes a copy engine that is configured to migrate or copy a set of data, e.g., one or more files, to the destination storage system using a file-based protocol over a network. The copy engine is also configured to ensure that any locks associated with the migrated data set are reclaimed at the destination storage system using a lock-based protocol. The source storage system further includes a proxy service that is configured to translate client requests to access the migrated data set to access requests executable (i.e., discernable) by the destination storage system. The proxy service then forwards or proxies the translated requests over the network to the destination storage system for processing.

Abstract: According to one embodiment, an error correction channel determination module determines, a channel to be allocated to a logical page as an error correction channel so that each of a plurality of channels is allocated to a uniform number of logical pages as the error correction channel. A command list generation module generates a list of write commands each specifying that a corresponding logical page is to be written using, in parallel, channels included in the plurality of channels and excluding the error correction channel, based on the determination of the channel to be allocated to the corresponding logical page as the error correction channel. A command list issue module issues the list of the write commands.

Abstract: A system and method for detecting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises an initialization bit as well as access type information, collectively called the state tracking bits for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. The second access is identified based on a status of the state tracking bits. The method also includes determining a hazard based on a first type of access and a second type of access to the shared memory location. Information related to the first access is provided in the table.