Memory Access Blocking Patents (Class 711/152)
  • Patent number: 11176121
    Abstract: A method, computer program product, and a system to globally serialize transactions where a processor(s) establishes a communications connection a (serialization) resource and a resource manager for a distributed computing system. The processor(s) obtains a first request from an application executing on the resource for access to a global resource managed by the resource manager, for executing a transaction. The processor(s) implements a lock for the global resource in an object store of the resource manager over the communications connection. The processor(s) communicates the lock to the application, which executes the transaction and the processor(s) updates a memory with a record comprising attributes of the lock. The processor(s) obtains a second request from the application to terminate the lock, obtains, identifies the lock for the transaction, in the object store, and updates the object store to delete the lock.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kishor Kulkarni, Sreejith Nalamvathukkal, Madhu B. Ananthapadmanabh
  • Patent number: 11132457
    Abstract: A system is provided for controlling access to data stored in a cloud-based storage service. Data associated with a user account is stored at the cloud-based storage service. A portion of the data is associated with a heightened authentication protocol, a first request receiving, at the cloud-based storage service, for an application to access data that is associated with the heightened authentication protocol. The first request is authenticated based on the heightened authentication protocol. In response to authenticating the first request, permission is granted to the application to access the data that is associated with the heightened authentication protocol. The permission is time-limited. It is determined that the application is editing the data that is associated with the heightened authentication protocol. Permission for the application to access the data while the application is editing the data is temporarily extended.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Daron Spektor, Jyotsana Rathore, Jose A. Barreto, Kevin Andrew Chan, Peter Daniel Henderson, Gabriela Kornelia Kaczka
  • Patent number: 11120132
    Abstract: Apparatuses and methods are disclosed for protection of data servers configured for data replication of a database. An example apparatus includes a processing circuit configured to receive records indicating respective modifications performed on a first version of the database stored in a first data server of the plurality of data servers. The processing circuit determines a risk level of a modification indicated by a record based on a set of factors indicated in a security profile, the set of factors being indicative of anomalous data access activity. The processing circuit performs the modification in a second data server, in response to the risk level being less than a threshold level indicated in the security profile. The processing circuit prevents the modification indicated by the record from being performed in the second data server in response to the risk level being greater than or equal to the threshold level.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 14, 2021
    Assignee: 8x8, Inc.
    Inventors: Mehdi Salour, Raghu Rengarajan
  • Patent number: 11121960
    Abstract: Techniques for managing communications between applications executing in a distributed computing environment are presented. An example method includes detecting, by a first virtual machine, that an application has migrated from a source virtual machine to a destination virtual machine in the distributed computing environment. The first virtual machine identifies a location of the destination virtual machine in the distributed computing environment. Based on the identified location, the first virtual machine generates one or more routing rules for communications between applications executing on the first virtual machine and the migrated application, wherein the one or more routing rules comprise rules that minimize latency and processing overhead for communications with the migrated application in the distributed computing environment.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dwip N. Banerjee, Maria Joseph Frederic Durairaj, Sivakumar Krishnasamy, James L. Hall
  • Patent number: 11113160
    Abstract: Disclosed are an apparatus for performing data migration and a method of operating the same for processing data migration between memories according to a monitoring result of a change in performance while applications are executed in a High Performance Computing (HPC) environment adapting hybrid memories.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 7, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE & TECHNOLOGY INFORMATION
    Inventors: Geunchul Park, Jieun Choi, Chan-Yeol Park, Seungwoo Rho, Jong Min Lee, Kwangho Lee
  • Patent number: 11093588
    Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Donald M. Morgan, Joseph C. Sher
  • Patent number: 11086672
    Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a lower level cache memory and a processor core coupled to the lower level cache memory. The processor core includes an execution unit for executing instructions in a plurality of simultaneous hardware threads, an upper level cache memory, and a plurality of wait flags each associated with a respective one of the plurality of simultaneous hardware threads. The processor core is configured to set a wait flag among the plurality of wait flags to indicate the associated hardware thread is in a wait state in which the hardware thread suspends instruction execution and to exit the wait state based on the wait flag being reset.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Hugh Shen, Guy L. Guthrie
  • Patent number: 11061832
    Abstract: A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a public network such as the Internet, or over a private connection. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and can be configured to hardware-protect that code from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 13, 2021
    Inventors: Frank N. Newman, Dan Newman
  • Patent number: 11050653
    Abstract: A method of operating a telemetry capture system within a data storage system comprising storage devices is provided. The method includes generating a telemetry packet, and providing the telemetry packet to one or more taps via a telemetry path independent of data and control paths within the storage devices. The method also includes capturing the telemetry packet in one or more of the taps, and generating real-time telemetry data based at least on the telemetry packet.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: June 29, 2021
    Assignee: Burlywood, Inc.
    Inventors: Amy Lee Wohlschlegel, Christopher Bergman, David Christopher Pruett, Edoardo Daelli, Erik Habbinga, John Foister Murphy, John William Slattery, Kevin Darveau Landin, Nathan Koch, Tod Roland Earhart, Will Allan Loechel
  • Patent number: 11036653
    Abstract: A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a public network such as the Internet, or over a private connection. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and can be configured to hardware-protect that code from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 15, 2021
    Inventors: Frank N. Newman, Dan Newman
  • Patent number: 11036532
    Abstract: A system includes a processor executing instructions from a computer-readable storage medium. The instructions include, in response to receiving a job request that identifies a first tenant, obtaining a first virtual network key (VNK) corresponding to the first tenant. The instructions include identifying a first computing system that has resources available to satisfy the job request. The instructions include transmitting a first command to the first computing system. The first command includes the first VNK, instructs the first computing system to assign a virtual machine to the job request, and associates the first VNK with the assigned virtual machine. The instructions include, in response to completion of the job request, transmitting a second command to the first computing system. The second command instructs the first computing system to associate a default VNK with the assigned virtual machine. The default VNK does not correspond to the first tenant.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 15, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sarvesh Sakalanaga, Raghav Mohan, Ashish Bhargava, Vishal Taneja
  • Patent number: 11030039
    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 8, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 10983839
    Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 20, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Ling Ma, Changhua He
  • Patent number: 10958527
    Abstract: Methods and systems for transaction fencing in a multi-domain network are provided. A system for providing transaction fencing in a multi-domain network includes an error identification module that identifies a communication error between a source domain and a destination node. The communication error is associated with a connection in a plurality of connections between a plurality of domains. Additionally, the system includes a tearing module that disconnects the destination node from the plurality of domains and clears outstanding transactions associated with the destination node in the plurality of domains. Further, the system includes a connection enable module that enables connections between the plurality of domains and the destination node.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Guller, Constantine Gavrilov, Ilya Tkachevsky
  • Patent number: 10936502
    Abstract: A computing device includes a persistent storage and a processor. The processor includes a local storage. The local storage includes blocks and an address space. The address space includes a first portion of entries that specify blocks of the local storage and a second portion of entries that specify blocks of the remote data storage. The processor obtains data for storage and makes a determination that the data cannot be stored in the local storage. In response to the determination, the processor stores the data in the remote storage using the second portion of entries.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Bob Yan, Helen Yan
  • Patent number: 10936504
    Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 2, 2021
    Assignee: ARM Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
  • Patent number: 10936469
    Abstract: A system for providing ongoing verification of released software components utilizes feedback from a pool of devices that each locally execute a verification component. The verification component randomly selects one or more locally-executing software components, captures information associated with the randomly-selected software components responsive to detection of events satisfying one or more capture conditions, and communicates the captured information to a software component verification and analysis service. The total number of the randomly-selected software components within the verification pool is set to statistically guarantee that each one of the software components available for random selection is randomly selected on at least one of the plurality of processing devices within the verification pool.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hyuk Joon Kwon, Vladimir A. Levin, Jakob Frederik Lichtenberg, Andrew M. Kluemke, Vikas Pabreja, Sebastian Lerner
  • Patent number: 10936548
    Abstract: Systems, components, devices, and methods for synchronizing files between a local file system and a server are provided. In an example, synchronization of individual files is paused by placing the individual files in a hold state. A non-limiting example method accesses a file stored on the local file system for synchronization with an associated file on the server and determines whether differences between the file and the associated file prevent synchronization. When determined that differences between the file and the associated file prevent synchronization, the method places the file in a hold state. The hold state pauses synchronization of the content in the file with the content of the associated file. In some examples, the method continues to synchronize topological changes to files that have been placed in the hold state and/or resumes synchronization after it is determined that the file is no longer different than the associated file.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yisheng Chen, Amnon Itamar Govrin, Francisco Jose Garcia-Ascanio, Jack Allen Nichols
  • Patent number: 10929203
    Abstract: Embodiments for providing compare and swap (CAS) functionality to key value storage to allow multi-threaded applications to share storage devices and synchronize multiple concurrent threads or processes. A key-value application programming interface (API) is modified to include a CAS API in addition to the standard Put and Get APIs. The CAS function uses a key, expected old value, and new value to compare and swap an existing key value only if its current value equals the expected old value. Hash values of the key value and expected old value may be used by the CAS function to improve performance and reduce bandwidth.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kfir Wolfson, Udi Shemer, Assaf Natanzon
  • Patent number: 10922235
    Abstract: A system and method are disclosed for handling logical-to-physical mapping and increasing the amount of mapping table information that may be stored in a cache in volatile memory. The system includes a storage device having non-volatile memory, an input/output interface, a cache manager, a cache utilization manager, a cache swap manager, and a storage controller configured to service a storage command using a physical address provided by the cache manager. The method includes receiving a storage command comprising a logical address, the logical address comprising a partition identifier, implementing a cache eviction policy in response to determining that a mapping table cache does not have a cache entry that matches the logical address. The method also includes evicting the cache entry with a ranking, or score, that satisfies a cache eviction threshold and loading a replacement cache entry from an address mapping table stores on non-volatile memory.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Shay Benisty, Eran Sharon
  • Patent number: 10908999
    Abstract: Providing continuous replication for container management system that allows configuration of a volume as a replicated network block device (NBD) volume to an actual backend volume. The system configures a pod with an NBD container running and with the actual backend volume device attached. An NBD server intercepts all I/O data arriving to the NBD volume and a filter driver intercepts writes to the NBD volume and writes them to the actual backend volume. The intercepted I/O data is also sent to a remote replication server container with persistent and journal volumes. The data is applied to the replication volume using the journal as a recover point for recovery for any point in time.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Ran Goldschmidt
  • Patent number: 10897390
    Abstract: A method for taking over a process in a processing system that includes a plurality of node groups, the method includes: determining, by a processor of a computer configured to belong to a first group among the plurality of node groups, whether a communication failure with any other of the plurality of node groups is detected; and starting a takeover process with a first priority according to a total number of nodes included in the first group, when the communication failure is detected.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Sho Kato, Kazuhiro Taniguchi, Akitaka Kamauchi
  • Patent number: 10846166
    Abstract: An anomaly detector for a Controller Area Network (CAN) bus performs state space classification on a per-message basis of messages on the CAN bus to label messages as normal or anomalous, and performs temporal pattern analysis as a function of time to label unexpected temporal patterns as anomalous. The anomaly detector issues an alert if an alert criterion is met that is based on the outputs of the state space classification and the temporal pattern analysis. The temporal pattern analysis may compare statistics of messages having analyzed arbitration IDs with statistics for messages having those analyzed arbitration IDs in a training dataset of CAN bus messages, and a temporal pattern is anomalous if there is a statistically significant deviation from the training dataset. The anomaly detector may be implemented on a vehicle Electronic Control Unit (ECU) communicating via a vehicle CAN bus.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 24, 2020
    Assignee: Batttelle Memorial Institute
    Inventors: Anuja Sonalker, David Sherman
  • Patent number: 10776524
    Abstract: Embodiments are directed to securing system management mode (SMM) in a computer system. A CPU is configurable to execute first code in a normal mode, and second code in a SMM. A SMM control engine is operative to transition the CPU from the normal mode to the SMM in response to a SMM transition call, and to control access by the CPU in the SMM to data from an originator of the SMM transition call. The access is controlled based on an authorization state assigned to the SMM transition call. An authorization engine is operative to perform authentication of the originator of the SMM transition call and to assign the authorization state based on an authentication result. The CPU in the SMM is prevented from accessing the data in response to the authentication result being a failure of authentication.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Jiewen Jacques Yao, Vincent J. Zimmer, Bassam N. Coury
  • Patent number: 10769027
    Abstract: Systems, apparatuses, and methods for scheduling maintenance jobs for computing assets implementing configuration items within a CMDB are described. The maintenance jobs include database backups. Two queues operate together to schedule a large number of jobs in a technique that is scalable while staying within resource constraints.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 8, 2020
    Assignee: ServiceNow, Inc.
    Inventors: Sam Hauer, Scott Stone, Ivan Batanov
  • Patent number: 10678710
    Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 9, 2020
    Assignee: Synopsys, Inc.
    Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
  • Patent number: 10652310
    Abstract: A method of distributing data over multiple Internet connections is provided. The method includes the steps of: (a) providing a client computer with access to a plurality of Internet connections; and (b) providing a host computer for determining the allocation of data to be sent to the client computer over each of the plurality of Internet connections using at least one of (i) predetermined criteria and (ii) dynamically changing criteria.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 12, 2020
    Assignee: Connectify, Inc.
    Inventors: Alexander Gizis, Brian Prodoehl, Kevin Cunningham, Brian Lutz
  • Patent number: 10635479
    Abstract: Described systems and methods allow protecting a hardware virtualization system from malicious software. Some embodiments use a hybrid event notification/analysis system, wherein a first component executing within a protected virtual machine (VM) registers as a handler for processor exceptions triggered by violations of memory access permissions, and wherein a second component executing outside the respective VM registers as a handler for VM exit events. The first component filters permission violation events according to a set of rules and only notifies the second component about events which are deemed relevant to security. The second component analyzes notified events to detect malicious software.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 28, 2020
    Assignee: Bitdefender IPR Management Ltd.
    Inventor: Andrei V. Lutas
  • Patent number: 10628192
    Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. the disclosure provides an apparatus including circuitry, a virtual machine management component for execution by the circuitry to define a plurality of public virtual memory spaces and assign each one of the plurality of public virtual memory spaces to a respective one of a plurality of VMs including a first VM and a second VM, and a virtual machine execution component for execution by the circuitry to execute a first virtual machine process corresponding to the first VM and a second virtual machine process corresponding to the second VM, the first virtual machine process to identify data to be provided to the second VM by the first VM and provide the data to the second VM by writing to a public virtual memory space assigned to the first VM. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: April 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Ben-Zion Friedman, Eliezer Tamir
  • Patent number: 10606768
    Abstract: A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a network such as the Internet. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and hardware-protects it from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 31, 2020
    Assignee: PathGuard, LLC
    Inventors: Frank N. Newman, Dan Newman
  • Patent number: 10552091
    Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include storing one or more data volumes to a small computer system interface storage device, and receiving a request to map a given data volume to a host computer. One or more attributes of the given data volume are identified, and using the identified one or more attributes, a unique logical unit number (LUN) for the given data volume is generated. The given data volume is mapped to the host computer via the unique LUN. In some embodiments, the generated LUN includes one of the one or more attributes. In additional embodiments, the generated LUN includes a result of a hash function using the one or more attributes. In storage virtualization environments, the data volume may include secondary logical units, and mapping the given data volume to the host may include binding the SLU to the host.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel I. Goodman, Ran Harel, Oren S. Li-On, Rivka M. Matosevich, Orit Nissan-Messing, Yossi Siles, Eliyahu Weissbrem
  • Patent number: 10545872
    Abstract: Techniques are described for reducing shared cache memory requests in a multi-threaded microprocessor-based system. One method includes receiving a request for data from a thread, identifying that the request correlates with a pending request associated with a different thread, combining the request with the pending request based on the identifying, and receiving the data after the combining, the receiving being based on the pending request. In some examples, the request may be associated with an address of a cache line in a cache memory.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: January 28, 2020
    Assignee: Ikanos Communications, Inc.
    Inventor: Alberto Brizio
  • Patent number: 10503892
    Abstract: The disclosed technology is generally directed to the authentication of software. In one example of the technology, a private attestation key is stored in hardware. In some examples, during a sequential boot process a hash is calculated, in an order in which the software stages are sequentially booted, of each software stage of a plurality of software stages. The hashes of each software stage of the plurality may be cryptographically appended to an accumulation register. The accumulation register may be used to attest to validity of the software stages. The plurality of software stages may include a first bootloader, a runtime for a first core of a multi-core processor, and a runtime for a first execution environment for a second core of the multi-core processor.
    Type: Grant
    Filed: June 25, 2017
    Date of Patent: December 10, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Felix Stefan Domke
  • Patent number: 10503666
    Abstract: A method for operating a microcontroller, where access rights of processes executed in the microcontroller to different memory areas are stored in a memory protection unit, includes, in the course of a simulation mode, a first process carrying out an access attempt to a certain memory area in a certain manner in the name of a second process; the memory protection unit transferring access rights of the second process for the certain memory area to the first process upon the access attempt. The access rights are read out by the first process and the simulation mode is terminated. The access attempt is preferably thereupon terminated and an access is not carried out according to this access attempt by the first process.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 10, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Jens Gladigau, Simon Hufnagel
  • Patent number: 10496302
    Abstract: Described are techniques for use in connection with providing data protection. A storage resource for which data protection is provided by a data protection service may be identified. One or more criteria may be specified denoting one or more trigger conditions for providing data protection by the data protection service, wherein, responsive to an occurrence of any of the one or more trigger conditions, first processing may be performed by the data protection service to protect the storage resource. The one or more criteria may include a first criterion identifying a first amount of data change that has to occur with respect to the storage resource. Notification may be received regarding an occurrence of a first of the one or more trigger conditions. Responsive to receiving the notification, the first processing may be performed by the data protection service.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Natasha Gaurav, Dennis T. Duprey, Bruce R. Rabe, Binbin Lin, Scott E. Joyce
  • Patent number: 10496612
    Abstract: A method for converting metadata in a hierarchical configuration within a filesystem from a first format to a second format includes reading metadata that is in the first format within the hierarchical configuration; writing all of the metadata that is in the first format into a flat file; scanning the metadata to compile a list of inode chunks; sorting the list of inode chunks based on the on disk location of the inode chunks; and writing all of the metadata from the flat file back into the hierarchical configuration, the metadata being in the second format. The method can also include increasing the size of each of a first inode and a second inode within a first inode chunk in the filesystem, assigning the first inode to the first inode chunk, and assigning the second inode to a second inode chunk.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 3, 2019
    Assignee: QUANTUM CORPORATION
    Inventor: Tim LaBerge
  • Patent number: 10491773
    Abstract: An information processing apparatus includes circuitry to check whether a program is active at plural timings. The program is previously terminated while keeping prohibition of at least one operation of the information processing apparatus. The circuitry cancels the prohibition of the at least one operation of the information processing apparatus when the program remains inactive for a given period of time.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: November 26, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Jongsook Eun
  • Patent number: 10481805
    Abstract: Preventing timeouts of I/O requests at a data storage system that are associated with cloud-based and/or external data storage systems. Rather than allow a timeout to occur, a response is sent to the host at a predetermined time before timeout, which will prevent the timeout from occurring and may cause the host system to “retry” the I/O operation by issuing another I/O request specifying the same I/O operation. The data storage system may repeat this process a preconfigured number of times or indefinitely, or until the host or user terminates or the application crashes. An I/O request received from a host may be configured in accordance with one or more SAN- or NAS-based protocols, and the I/O request may be translated into an I/O request conforming to one or more cloud-based and/or Internet-based protocols and transmitted to a cloud-based and/or external storage system.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Adnan Sahin, Wayne D'Entremont, Suresh Krishnan, Arieh Don
  • Patent number: 10452459
    Abstract: Systems and methods are described for verifying functionality of a computing device. Rules are received that are usable to configure a driver verifier function to capture information associated with a device driver identified by the rules. The configured driver verifier function is run on a computing device. The information is captured in response to driver conditions identified by the rules. The computing device is allowed to continue operation when the driver condition includes an error condition of the identified device driver. A communication is initiated to transmit the captured information to a driver verification analysis service.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Markus W. Mielke, Jakob F. Lichtenberg, Vladimir A. Levin, Remy L. De Weduwe, Hyuk Joon Kwon, Nathan L. Deisinger, Vikas Pabreja, Juncao Li
  • Patent number: 10387037
    Abstract: Techniques for enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies are disclosed. A hardware processor includes a plurality of processing elements, a memory that is heavily-banked into a plurality of banks, and an arbiter. The arbiter is to receive requests from threads executing at the plurality of processing elements seeking to perform operations involving the memory, and to maintain a plurality of lock buffers corresponding to the plurality of banks. Each of the lock buffers is able to track up to a plurality of memory addresses within the corresponding bank that are to be treated as locked in that the values stored at those memory addresses cannot be updated by those of the threads that did not cause the memory addresses to be locked until those memory addresses have been removed from being tracked by the plurality of lock buffers.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Ganesh Venkatesh, Deborah Marr
  • Patent number: 10382578
    Abstract: This application relates to embodiments for providing a content stream to a device from a content server based on a protocol that is established between the device and an account server. The account server can initiate a session with the device and provide the device with a list of channels available for a user account associated with the device. When a channel is selected at the device, conditional access information can be provided from the account server to the device, which can thereafter relay the conditional access information to the content server. The content server can use the conditional access information to verify that the device has the appropriate permission to receive streaming content. In this way, because the conditional access information originates at the account server, permission to access streaming content can be managed by correspondence between the account server and the device, rather than the content server.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: August 13, 2019
    Assignee: Apple Inc.
    Inventors: Srinivas Vedula, Daniel P. Carter, Gianpaolo Fasoli, Augustin J. Farrugia, Eugene Jivotovski
  • Patent number: 10379768
    Abstract: In one embodiment, a memory interface employs selective memory mode authorization enforcement in accordance with the present description to ensure that memory modes of operation which have not been authorized, are not permitted to proceed. In one embodiment, mode control logic receives from memory control logic of the memory interface, memory mode selection data which is compared to a mode authorization classification structure to determine if the memory mode being selected in association with a memory transaction request is authorized or otherwise permitted. Memory mode enablement logic of the mode control logic enables the requested memory mode associated with a memory transaction request if it is determined that the selected memory mode associated with the memory transaction request is authorized. Other aspects are described herein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 13, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mahesh S. Natu, Vedaraman Geetha
  • Patent number: 10367923
    Abstract: The invention relates to a method for processing at least one data packet (78, 156) which comprises a first header (82, 158) and a payload (100, 160), wherein the first header (82, 158) is processed by a first mode and the payload (100, 160) is processed by a second mode, wherein a number of processing steps (172, 174) for carrying out the second mode is greater than a number of processing steps (168, 170) for carrying out the first mode, the two modes being performed separately from one another.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: July 30, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Volker Blaschke, Guenter Vogel, Timo Lothspeich, Anton Pfefferseder, Reiner Schnitzer, Jeffrey Lee, Soeren Krieger, Juergen Mallok
  • Patent number: 10348558
    Abstract: The present disclosure discloses a method and system for restarting the network service with zero downtime, comprising: a) listening, by an original process of the network service, on a first port; (b) configuring and initiating a transition process, wherein the configuring includes causing the transition process to listen on a second port different from the first port of the original process; (c) running a connection tracking module and, meanwhile adding an iptables rule to redirect a connection directed to the first port to the second port; (d) waiting until existing connections on the original process are processed completely, then exiting the original process; (e) initiating a new process on the first port according to a new configuring file; (f) reconfiguring the iptables rule to cancel port redirection; and (g) waiting until existing connections on the transition process are processed completely, then exiting the transition process.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: July 9, 2019
    Assignee: WANGSU SCIENCE & TECHNOLOGY CO., LTD
    Inventor: Xun Chen
  • Patent number: 10346306
    Abstract: Methods and apparatuses relating to memory performance monitoring are described, including a processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Amitabha Roy, Subramanya R. Dulloor, Rajesh M. Sankaran
  • Patent number: 10305793
    Abstract: A communication device conforming with plural communication standards and having a storage storing a plurality of virtual stacks each having an application program and communication program that implements a protocol stack for communication by the application program. An executor executes the virtual stacks, and a switching controller switches the virtual stacks to be executed by performing a first processing in which at least one part of at least one of the virtual stacks is read from storage and stored into a memory of, and executed by, the executor. Then, in accordance with free capacity in the memory, at least one part of at least one of the virtual stacks executed in the first processing is deleted from memory. In a second processing at least one part of at least one of the virtual stacks is read from the storage and stored into the memory of, and executed by, the executor.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: May 28, 2019
    Assignee: Yokogawa Electric Corporation
    Inventors: Nobuo Okabe, Yukiyo Akisada, Kazunori Miyazawa, Yasuki Sakurai
  • Patent number: 10291543
    Abstract: A system, method, and computer program product are provided for migrating availability of a resource type in a communication network using network function virtualization, comprising: selecting a resource type; selecting a first section of the network where demand for the resource type is expected to grow; selecting a second section of the network where demand for the resource type is expected to be stable relative to the first section; selecting a third section of the network communicatively coupled to the first and second sections, the third section comprising higher availability of the resource type than the first section; migrating a first virtual network function (VNF) instance from the third section to the first section; and migrating a second virtual network function instance from the second section to the third section.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: May 14, 2019
    Assignee: AMDOCS DEVELOPMENT LIMITED
    Inventors: Eyal Felstaine, Ofer Hermoni, Itzik Kitroser, Nimrod Sandlerman
  • Patent number: 10261794
    Abstract: Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 16, 2019
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Andre′ DeHon
  • Patent number: 10242022
    Abstract: The disclosed computer-implemented method for managing delayed allocation on clustered file systems may include (i) receiving, at a global lock manager that stores storage disk allocation information for a plurality of nodes in a clustered file system, a lock request from a node that requests a lock range on a storage disk to store data from a file, (ii) reserving, by the global lock manager, the lock range, (iii) receiving, at the global lock manager, from an additional node, an additional lock request for an additional lock range to store additional data from the file, and (iv) reserving, by the global lock manager, the additional lock range to be adjacent to the lock range on the storage disk based on the additional data on the additional node being from the same file as the data on the node. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 26, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Sanjay Jain, Shirish Vijayvargiya, Anindya Banerjee
  • Patent number: 10236069
    Abstract: An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Ning Wu, Robert E. Frickey