Memory Access Blocking Patents (Class 711/152)
  • Patent number: 11893248
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host device to read data from the memory device, fetch the read data from the memory device, check metadata associated with the read data, determine if the metadata corresponds to the read command, and provide modified read data to the host device when the metadata does not correspond to the read command. The modified read data may be encrypted read data, corrupted read data, or read data that is replaced with debug information. When the host device receives data that is different than the read data that is requested, the modified read data may be unreadable to the host device so that unprivileged access to the read data may be avoided.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11847349
    Abstract: A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
  • Patent number: 11775180
    Abstract: Disk based emulation of tape libraries is provided with features that allow easier management and administration of a backup system and also allow increased flexibility to both archive data on tape at a remote location and also have fast restore access to archived data files. Features include automatic emulation of physical libraries, and the retention and write protection of virtual tapes that correspond to exported physical tapes.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: October 3, 2023
    Assignee: OVERLAND STORAGE, INC.
    Inventors: Victoria Gonzalez, Sergio Encarnacao
  • Patent number: 11775219
    Abstract: Examples of electronic devices are described herein. In some examples, an electronic device includes a flash memory. In some examples, the electronic device includes a host memory to store an access control structure to access the flash memory. In some examples, the electronic device includes a first circuitry coupled to the host memory and the flash memory. In some examples, the first circuitry is to read the access control structure in the host memory to determine when to access the flash memory.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: October 3, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Wei Ze Liu, Khoa Dang Huynh, Rosilet Retnamoni Braduke
  • Patent number: 11720413
    Abstract: Disclosed are systems and methods of providing virtualized storage that may include establishing, through a load balancer, a transport connection between a device and a group of fabric-attached storage devices, and transferring data between the device and the group of fabric-attached storage devices through the transport connection using a transport protocol, wherein the group of fabric-attached storage devices comprises two or more fabric-attached storage devices and is accessed by the device as a logical storage device. A storage device may include a storage medium, a network fabric interface, and a storage controller configured to transfer data between the storage medium and a device through the network fabric interface over a transport connection, wherein the storage controller is configured to share the transport connection with another data storage device that is fabric-attached.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 8, 2023
    Inventor: Ronald Lee
  • Patent number: 11706299
    Abstract: Aspects of the disclosure relate to data sharding for transmission over a high generation cellular network. A computing platform may detect, via a communication network, transmission of data from a first computing device to a second computing device. Subsequently, the computing platform may intercept, prior to receipt of the transmission by the second computing device, the data. Then, the computing platform may shard the data into a first shard and a second shard. Then, the computing platform may identify, within the communication network, a first communication channel and a second communication channel. Then, the computing platform may send, to the second computing device, the first shard via the first communication channel, and the second shard via the second communication channel. Subsequently, the computing platform may merge, the first shard and the second shard, to reconfigure the data.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: July 18, 2023
    Assignee: Bank of America Corporation
    Inventors: John C. Checco, Ryan Muzzo
  • Patent number: 11681542
    Abstract: The disclosure provides for integrating virtual machine (VM) and host networking, forwarding port data and occupation status to host and VM endpoints. Examples synchronize, by a host agent, port reservations with a guest agent on a first VM on the host; receive an indication that a VM port on the first VM is occupied; based at least on receiving the indication that the VM port is occupied, update the port reservations to include that a host port corresponding to the VM port is occupied; receive incoming external traffic on the host port; and based at least on the port reservations and receiving the incoming external traffic on the host port, route the incoming external traffic to the VM port on the first VM. VM-based application behavior thus appears more similar to that of native applications.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 20, 2023
    Assignee: VMware, Inc.
    Inventors: Junfei Wu, Yan Wang, Haitao Zuo
  • Patent number: 11625416
    Abstract: A uniform model for distinct types of data replication, including receiving, at a source data repository, an update to a dataset; generating, based on the update to the dataset, both metadata describing the update to the dataset and also a metadata representation of the dataset; and initiating, based on the same metadata describing the update to the dataset and also based on the same metadata representation of the dataset, either a first type of data replication or a second type of data replication from among a plurality of types of data replication.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 11, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: David Grunwald, Thomas Gill, Ronald Karr, Matthew Fay, Luke Paulsen, John Colgrove
  • Patent number: 11561899
    Abstract: Disclosed is a computer implemented method to manage a cache, the method comprising, determining that a primary application opens a first file, wherein opening the first file includes reading the first file into a file cache from a storage. The method also includes, setting a first monitoring variable in the primary application process proc structure, wherein the first monitoring variable is set in response to the primary application opening the first file, and the first monitoring variable records a set of operations completed on the first file by the primary application. The method comprises a first read of the first file being at a beginning of the first file. The method includes identifying that the first file is read according to a pattern that includes reading the first file sequentially and reading the first file entirely and removing the first file from the file cache.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Bret R. Olszewski, Grover Cleveland Davidson, II, Chad Collie
  • Patent number: 11544204
    Abstract: A memory system includes a nonvolatile memory set including a nonvolatile memory; and a memory controller configured to control the nonvolatile memory set. The memory controller may write data to a memory block in a target memory block pool in the nonvolatile memory set during a target time period existing between a time at which an operation mode for the nonvolatile memory set is changed from a second operation mode to a first operation mode and a time at which a command including information indicating that a host expects a requested operation to be performed in the first operation mode is received from the host, prevent execution of a background operation for the nonvolatile memory set, when the operation mode is the first operation mode, and control a background operation for the nonvolatile memory set to be executable, when the operation mode is the second operation mode.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Do Hyeong Lee, Hee Chan Shin, Young Ho Ahn, Yong Seok Oh
  • Patent number: 11500648
    Abstract: A method for preparing fast boot of an information handling apparatus. The information handling apparatus contains a first CPU configured to connect to a storage device storing firmware and a second CPU connected to the first CPU. The method contains the steps of: allocating a firmware region in memories associated with each one of the first and second CPUs respectively; and copying a firmware from a storage device to the firmware region of each one of the memories. By utilizing a system memory such as NVDIMM which provides higher access speed than NAND flash and also persistent data storage, one or more CPUs can be booted from firmware images in the NVDIMM much faster, thus saving the total booting time.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 15, 2022
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Zhijun Liu, Chekim Chhuor, Wen Wei Tang
  • Patent number: 11500553
    Abstract: A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 15, 2022
    Assignee: Salesforce, Inc.
    Inventors: Luc Marcel Giavelli, Joshua James Luft-Glidden, Radhika Nair, Fabrice Talbot, Srinivasa Gopaladasu, Venkata Kolla, Lucas Pfister, Chintan Tank, Chaitanya Bhatt
  • Patent number: 11494220
    Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. In an example embodiment, an apparatus may include circuitry and memory storing instructions for execution by the circuitry to assign each one of a plurality of shared virtual memory spaces to a respective one of a plurality of virtual machines, wherein a first shared virtual memory space of the plurality of shared virtual memory spaces is assigned to a first virtual machine of the plurality of virtual machines, write, by the first virtual machine to the first shared virtual memory space, data to be provided to a second virtual machine of the plurality of virtual machines, and read, by the second virtual machine, the data in the first shared virtual memory space.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 8, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ben-Zion Friedman, Eliezer Tamir
  • Patent number: 11481336
    Abstract: Devices and techniques for efficient host assisted logical-to-physical (L2P) mapping are described herein. For example, a command can be executed that results in a change as to which physical address of a memory device corresponds to a logical address. The change can be obfuscated as part of an obfuscated L2P map for the memory device and written to storage on the memory device. The change can then be provided a host from the storage.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nadav Grosz, Jonathan Scott Parry
  • Patent number: 11449228
    Abstract: A recording control apparatus that records data on a recording medium includes a position recording unit configured to perform control so that, upon completion of recording of data, a recording start position for next recording of data is recorded on the recording medium, an initialization unit configured to initialize the recording medium, and a control unit configured to perform control in such a manner that in a case where the initialization unit executes first initialization processing, the first initialization processing and clear processing for clearing the recording start position recorded on the recording medium are executed, and in a case where the initialization unit executes second initialization processing, the second initialization processing is executed without executing the clear processing.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 20, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yohei Fujitani
  • Patent number: 11443052
    Abstract: A system is provided for controlling access to data stored in a cloud-based storage service. Data associated with a user account is stored at the cloud-based storage service. A first request to cause a portion of the data to be associated with a heightened authentication protocol is received. In response, the portion of the data is caused to require the heightened authentication protocol for access. A second request for a file that is stored in the area that is associated with the heightened authentication protocol is received. The second request is authenticated based on the heightened authentication protocol. In response to authenticating the second request, permission is granted to access the file. In response to a failure to authenticate the second request, access to the file is denied, while access to files stored in other areas associated with the user account is allowed.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 13, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Filip C. Lazar, Steven J. Bailey, John D. Rodrigues, Andrew Keith Glover, Jyotsana Rathore, Jose A. Barreto, Kevin Andrew Chan, Gregory P. Young, Jacob C. Schieber, Jackson Cowan, Meir E. Abergel
  • Patent number: 11442638
    Abstract: Devices and techniques for status management in storage backed memory are disclosed herein. An encoded message can be received at a first interface of the memory package. Here, the memory package also includes a second interface to a host. The message can be decoded to obtain a decoded message that includes an attribute. The attribute can be compared a set of attributes that correspond to an advertised status of the memory package. The comparison enables a determination that the attribute is in the set of attributes. The advertised status of the memory package can then be modified in response to the determination that the attribute is in the set of attributes.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Burns, Gary R. Van Sickle, Jeffery J. Leyda
  • Patent number: 11366933
    Abstract: Disclosed herein is a data storage device comprising a data path and an access controller. The data path comprises a data port configured to transmit data between a host computer and the data storage device and registers with the host computer system as a block data storage device. A non-volatile storage medium stores encrypted user content data. A cryptography engine is connected between the data port and the storage medium and uses a key to decrypt the encrypted user content data. A data store stores multiple entries comprising authorization data associated with respective authorized devices. The access controller receives from a manager device a public key associated with a private key stored on a device to be authorized, creates the authorization data, and stores the authorization data in association with the public key in the data store, thereby registering the device to be authorized as one of the authorized devices.
    Type: Grant
    Filed: December 8, 2019
    Date of Patent: June 21, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Brian Edward Mastenbrook, Matthew Harris Klapman
  • Patent number: 11334415
    Abstract: A data storage device and a method for sharing memory of controller thereof are provided. The data storage device comprises a non-volatile memory and a controller, which is electrically coupled to the non-volatile memory and comprises an access interface, a redundant array of independent disks (RAID) error correcting code (ECC) engine and a central processing unit (CPU). The CPU has a first memory for storing temporary data, the RAID ECC engine has a second memory, and the controller maps the unused memory space of the second memory to the first memory to be virtualized as part of the first memory when the second memory is not fully used so that the CPU can also use the unused memory space of the second memory to store the temporary data.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: May 17, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: An-Pang Li
  • Patent number: 11288229
    Abstract: Verifiable intra-cluster migration (VICM) for a chunk storage system is disclosed. VICM can migrate data from a first portion of a cluster to a second portion of a cluster. VICM can comprise locking a first portion of a cluster and locking a corresponding first cluster table during a preparation phase. Chunks of the first portion can then be migrated, during a migration phase, to the second portion and a second cluster table, corresponding to the second portion, can be updated accordingly. Garbage management operations, including recovery operations, can be performed via the second cluster table and the second portion during the migration phase. Upon completion of the migration phase, a reconciliation phase can comprise verifying chunk relationships of the second cluster table and the second portion based on the first cluster table. Exceptions to the verification can be reported via an exception report.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 29, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Mikhail Edkov
  • Patent number: 11256797
    Abstract: The disclosed technology is generally directed to the authentication of software. In one example of the technology, a private attestation key is stored in hardware. In some examples, during a sequential boot process a hash is calculated, in an order in which the software stages are sequentially booted, of each software stage of a plurality of software stages. The hashes of each software stage of the plurality may be cryptographically appended to an accumulation register. The accumulation register may be used to attest to validity of the software stages. The plurality of software stages may include a first bootloader, a runtime for a first core of a multi-core processor, and a runtime for a first execution environment for a second core of the multi-core processor.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 22, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Felix Stefan Domke
  • Patent number: 11258854
    Abstract: Aspects of the disclosure relate to data sharding for transmission over a high generation cellular network. A computing platform may detect, via a communication network, transmission of data from a first computing device to a second computing device. Subsequently, the computing platform may intercept, prior to receipt of the transmission by the second computing device, the data. Then, the computing platform may shard the data into a first shard and a second shard. Then, the computing platform may identify, within the communication network, a first communication channel and a second communication channel. Then, the computing platform may send, to the second computing device, the first shard via the first communication channel, and the second shard via the second communication channel. Subsequently, the computing platform may merge, the first shard and the second shard, to reconfigure the data.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 22, 2022
    Assignee: Bank of America Corporation
    Inventors: John C. Checco, Ryan Muzzo
  • Patent number: 11200158
    Abstract: Methods and devices for hardware-supported schemes for efficient metadata retrieval are described. The schemes may use hardware to efficiently enforce type safety and speed up memory bound checks without imposing undue memory overhead. Multiple such schemes may be supported by a device, permitting the selection of an optimal scheme based on a given memory allocation request. The schemes may be compatible with legacy code and applicable to a wide range of data objects and system constraints. Compilation, instrumentation, and linking of code to effect such schemes is also described.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: December 14, 2021
    Assignees: The Governing Council of the University of Toronto, Huawei Technologies Canada Co., Ltd.
    Inventors: David Lie, Shengjie Xu, Wei Huang
  • Patent number: 11194485
    Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry 8. In response to a realm switch from a source realm to a target realm at a more privileged exception level, state masking of a subset of architectural state associated with a source realm is performed to make the state inaccessible to a target realm. In response to a flush command following the realm switch, any of the subset of architectural state data not already saved to at least one realm execution context memory region is ensured to be saved.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 7, 2021
    Assignee: ARM LIMITED
    Inventors: Jason Parker, Matthew Lucien Evans, Gareth Rhys Stockwell, Djordje Kovacevic
  • Patent number: 11176121
    Abstract: A method, computer program product, and a system to globally serialize transactions where a processor(s) establishes a communications connection a (serialization) resource and a resource manager for a distributed computing system. The processor(s) obtains a first request from an application executing on the resource for access to a global resource managed by the resource manager, for executing a transaction. The processor(s) implements a lock for the global resource in an object store of the resource manager over the communications connection. The processor(s) communicates the lock to the application, which executes the transaction and the processor(s) updates a memory with a record comprising attributes of the lock. The processor(s) obtains a second request from the application to terminate the lock, obtains, identifies the lock for the transaction, in the object store, and updates the object store to delete the lock.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kishor Kulkarni, Sreejith Nalamvathukkal, Madhu B. Ananthapadmanabh
  • Patent number: 11132457
    Abstract: A system is provided for controlling access to data stored in a cloud-based storage service. Data associated with a user account is stored at the cloud-based storage service. A portion of the data is associated with a heightened authentication protocol, a first request receiving, at the cloud-based storage service, for an application to access data that is associated with the heightened authentication protocol. The first request is authenticated based on the heightened authentication protocol. In response to authenticating the first request, permission is granted to the application to access the data that is associated with the heightened authentication protocol. The permission is time-limited. It is determined that the application is editing the data that is associated with the heightened authentication protocol. Permission for the application to access the data while the application is editing the data is temporarily extended.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Daron Spektor, Jyotsana Rathore, Jose A. Barreto, Kevin Andrew Chan, Peter Daniel Henderson, Gabriela Kornelia Kaczka
  • Patent number: 11120132
    Abstract: Apparatuses and methods are disclosed for protection of data servers configured for data replication of a database. An example apparatus includes a processing circuit configured to receive records indicating respective modifications performed on a first version of the database stored in a first data server of the plurality of data servers. The processing circuit determines a risk level of a modification indicated by a record based on a set of factors indicated in a security profile, the set of factors being indicative of anomalous data access activity. The processing circuit performs the modification in a second data server, in response to the risk level being less than a threshold level indicated in the security profile. The processing circuit prevents the modification indicated by the record from being performed in the second data server in response to the risk level being greater than or equal to the threshold level.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 14, 2021
    Assignee: 8x8, Inc.
    Inventors: Mehdi Salour, Raghu Rengarajan
  • Patent number: 11121960
    Abstract: Techniques for managing communications between applications executing in a distributed computing environment are presented. An example method includes detecting, by a first virtual machine, that an application has migrated from a source virtual machine to a destination virtual machine in the distributed computing environment. The first virtual machine identifies a location of the destination virtual machine in the distributed computing environment. Based on the identified location, the first virtual machine generates one or more routing rules for communications between applications executing on the first virtual machine and the migrated application, wherein the one or more routing rules comprise rules that minimize latency and processing overhead for communications with the migrated application in the distributed computing environment.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dwip N. Banerjee, Maria Joseph Frederic Durairaj, Sivakumar Krishnasamy, James L. Hall
  • Patent number: 11113160
    Abstract: Disclosed are an apparatus for performing data migration and a method of operating the same for processing data migration between memories according to a monitoring result of a change in performance while applications are executed in a High Performance Computing (HPC) environment adapting hybrid memories.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 7, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE & TECHNOLOGY INFORMATION
    Inventors: Geunchul Park, Jieun Choi, Chan-Yeol Park, Seungwoo Rho, Jong Min Lee, Kwangho Lee
  • Patent number: 11093588
    Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Donald M. Morgan, Joseph C. Sher
  • Patent number: 11086672
    Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a lower level cache memory and a processor core coupled to the lower level cache memory. The processor core includes an execution unit for executing instructions in a plurality of simultaneous hardware threads, an upper level cache memory, and a plurality of wait flags each associated with a respective one of the plurality of simultaneous hardware threads. The processor core is configured to set a wait flag among the plurality of wait flags to indicate the associated hardware thread is in a wait state in which the hardware thread suspends instruction execution and to exit the wait state based on the wait flag being reset.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Hugh Shen, Guy L. Guthrie
  • Patent number: 11061832
    Abstract: A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a public network such as the Internet, or over a private connection. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and can be configured to hardware-protect that code from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 13, 2021
    Inventors: Frank N. Newman, Dan Newman
  • Patent number: 11050653
    Abstract: A method of operating a telemetry capture system within a data storage system comprising storage devices is provided. The method includes generating a telemetry packet, and providing the telemetry packet to one or more taps via a telemetry path independent of data and control paths within the storage devices. The method also includes capturing the telemetry packet in one or more of the taps, and generating real-time telemetry data based at least on the telemetry packet.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: June 29, 2021
    Assignee: Burlywood, Inc.
    Inventors: Amy Lee Wohlschlegel, Christopher Bergman, David Christopher Pruett, Edoardo Daelli, Erik Habbinga, John Foister Murphy, John William Slattery, Kevin Darveau Landin, Nathan Koch, Tod Roland Earhart, Will Allan Loechel
  • Patent number: 11036653
    Abstract: A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a public network such as the Internet, or over a private connection. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and can be configured to hardware-protect that code from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 15, 2021
    Inventors: Frank N. Newman, Dan Newman
  • Patent number: 11036532
    Abstract: A system includes a processor executing instructions from a computer-readable storage medium. The instructions include, in response to receiving a job request that identifies a first tenant, obtaining a first virtual network key (VNK) corresponding to the first tenant. The instructions include identifying a first computing system that has resources available to satisfy the job request. The instructions include transmitting a first command to the first computing system. The first command includes the first VNK, instructs the first computing system to assign a virtual machine to the job request, and associates the first VNK with the assigned virtual machine. The instructions include, in response to completion of the job request, transmitting a second command to the first computing system. The second command instructs the first computing system to associate a default VNK with the assigned virtual machine. The default VNK does not correspond to the first tenant.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 15, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sarvesh Sakalanaga, Raghav Mohan, Ashish Bhargava, Vishal Taneja
  • Patent number: 11030039
    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 8, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 10983839
    Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 20, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Ling Ma, Changhua He
  • Patent number: 10958527
    Abstract: Methods and systems for transaction fencing in a multi-domain network are provided. A system for providing transaction fencing in a multi-domain network includes an error identification module that identifies a communication error between a source domain and a destination node. The communication error is associated with a connection in a plurality of connections between a plurality of domains. Additionally, the system includes a tearing module that disconnects the destination node from the plurality of domains and clears outstanding transactions associated with the destination node in the plurality of domains. Further, the system includes a connection enable module that enables connections between the plurality of domains and the destination node.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Guller, Constantine Gavrilov, Ilya Tkachevsky
  • Patent number: 10936469
    Abstract: A system for providing ongoing verification of released software components utilizes feedback from a pool of devices that each locally execute a verification component. The verification component randomly selects one or more locally-executing software components, captures information associated with the randomly-selected software components responsive to detection of events satisfying one or more capture conditions, and communicates the captured information to a software component verification and analysis service. The total number of the randomly-selected software components within the verification pool is set to statistically guarantee that each one of the software components available for random selection is randomly selected on at least one of the plurality of processing devices within the verification pool.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hyuk Joon Kwon, Vladimir A. Levin, Jakob Frederik Lichtenberg, Andrew M. Kluemke, Vikas Pabreja, Sebastian Lerner
  • Patent number: 10936502
    Abstract: A computing device includes a persistent storage and a processor. The processor includes a local storage. The local storage includes blocks and an address space. The address space includes a first portion of entries that specify blocks of the local storage and a second portion of entries that specify blocks of the remote data storage. The processor obtains data for storage and makes a determination that the data cannot be stored in the local storage. In response to the determination, the processor stores the data in the remote storage using the second portion of entries.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Bob Yan, Helen Yan
  • Patent number: 10936504
    Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 2, 2021
    Assignee: ARM Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
  • Patent number: 10936548
    Abstract: Systems, components, devices, and methods for synchronizing files between a local file system and a server are provided. In an example, synchronization of individual files is paused by placing the individual files in a hold state. A non-limiting example method accesses a file stored on the local file system for synchronization with an associated file on the server and determines whether differences between the file and the associated file prevent synchronization. When determined that differences between the file and the associated file prevent synchronization, the method places the file in a hold state. The hold state pauses synchronization of the content in the file with the content of the associated file. In some examples, the method continues to synchronize topological changes to files that have been placed in the hold state and/or resumes synchronization after it is determined that the file is no longer different than the associated file.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yisheng Chen, Amnon Itamar Govrin, Francisco Jose Garcia-Ascanio, Jack Allen Nichols
  • Patent number: 10929203
    Abstract: Embodiments for providing compare and swap (CAS) functionality to key value storage to allow multi-threaded applications to share storage devices and synchronize multiple concurrent threads or processes. A key-value application programming interface (API) is modified to include a CAS API in addition to the standard Put and Get APIs. The CAS function uses a key, expected old value, and new value to compare and swap an existing key value only if its current value equals the expected old value. Hash values of the key value and expected old value may be used by the CAS function to improve performance and reduce bandwidth.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kfir Wolfson, Udi Shemer, Assaf Natanzon
  • Patent number: 10922235
    Abstract: A system and method are disclosed for handling logical-to-physical mapping and increasing the amount of mapping table information that may be stored in a cache in volatile memory. The system includes a storage device having non-volatile memory, an input/output interface, a cache manager, a cache utilization manager, a cache swap manager, and a storage controller configured to service a storage command using a physical address provided by the cache manager. The method includes receiving a storage command comprising a logical address, the logical address comprising a partition identifier, implementing a cache eviction policy in response to determining that a mapping table cache does not have a cache entry that matches the logical address. The method also includes evicting the cache entry with a ranking, or score, that satisfies a cache eviction threshold and loading a replacement cache entry from an address mapping table stores on non-volatile memory.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Shay Benisty, Eran Sharon
  • Patent number: 10908999
    Abstract: Providing continuous replication for container management system that allows configuration of a volume as a replicated network block device (NBD) volume to an actual backend volume. The system configures a pod with an NBD container running and with the actual backend volume device attached. An NBD server intercepts all I/O data arriving to the NBD volume and a filter driver intercepts writes to the NBD volume and writes them to the actual backend volume. The intercepted I/O data is also sent to a remote replication server container with persistent and journal volumes. The data is applied to the replication volume using the journal as a recover point for recovery for any point in time.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Ran Goldschmidt
  • Patent number: 10897390
    Abstract: A method for taking over a process in a processing system that includes a plurality of node groups, the method includes: determining, by a processor of a computer configured to belong to a first group among the plurality of node groups, whether a communication failure with any other of the plurality of node groups is detected; and starting a takeover process with a first priority according to a total number of nodes included in the first group, when the communication failure is detected.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Sho Kato, Kazuhiro Taniguchi, Akitaka Kamauchi
  • Patent number: 10846166
    Abstract: An anomaly detector for a Controller Area Network (CAN) bus performs state space classification on a per-message basis of messages on the CAN bus to label messages as normal or anomalous, and performs temporal pattern analysis as a function of time to label unexpected temporal patterns as anomalous. The anomaly detector issues an alert if an alert criterion is met that is based on the outputs of the state space classification and the temporal pattern analysis. The temporal pattern analysis may compare statistics of messages having analyzed arbitration IDs with statistics for messages having those analyzed arbitration IDs in a training dataset of CAN bus messages, and a temporal pattern is anomalous if there is a statistically significant deviation from the training dataset. The anomaly detector may be implemented on a vehicle Electronic Control Unit (ECU) communicating via a vehicle CAN bus.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 24, 2020
    Assignee: Batttelle Memorial Institute
    Inventors: Anuja Sonalker, David Sherman
  • Patent number: 10776524
    Abstract: Embodiments are directed to securing system management mode (SMM) in a computer system. A CPU is configurable to execute first code in a normal mode, and second code in a SMM. A SMM control engine is operative to transition the CPU from the normal mode to the SMM in response to a SMM transition call, and to control access by the CPU in the SMM to data from an originator of the SMM transition call. The access is controlled based on an authorization state assigned to the SMM transition call. An authorization engine is operative to perform authentication of the originator of the SMM transition call and to assign the authorization state based on an authentication result. The CPU in the SMM is prevented from accessing the data in response to the authentication result being a failure of authentication.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Jiewen Jacques Yao, Vincent J. Zimmer, Bassam N. Coury
  • Patent number: 10769027
    Abstract: Systems, apparatuses, and methods for scheduling maintenance jobs for computing assets implementing configuration items within a CMDB are described. The maintenance jobs include database backups. Two queues operate together to schedule a large number of jobs in a technique that is scalable while staying within resource constraints.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 8, 2020
    Assignee: ServiceNow, Inc.
    Inventors: Sam Hauer, Scott Stone, Ivan Batanov
  • Patent number: 10678710
    Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 9, 2020
    Assignee: Synopsys, Inc.
    Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra