Abstract: A memory access operand of an instruction that accesses memory may be treated as a transaction atomic access. The processor may execute one or more processor state setting instructions, causing state information to be set in the processor. Upon executing a transaction policy override instruction, the default conflict detection policy is overridden for one or more subsequent memory accessing instructions.

Abstract: A memory access operand of an instruction that accesses memory may be treated as a transaction atomic access. Non-default atomicity handling of memory accesses is enabled based on successful comparison by the processor of specified storage values at run-time. Upon executing a transaction policy override instruction, the default conflict detection policy is overridden for one or more subsequent memory accessing instructions.

Abstract: A system includes a multi-process application that runs on primary hosts and is checkpointed by a checkpointer comprised of a kernel-mode checkpointer module and one or more user-space interceptors providing at least one of barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing may be incremental using Page Table Entry (PTE) pages and Virtual Memory Areas (VMA) information. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Abstract: Remote computing resource service providers allow customers to execute one or more applications in a virtual environment on computer systems provided by the computing resource service provider. The virtual machines may be managed by a hypervisor executing on computer systems operated by the service provider. The virtual machines' memory may be protected by a memory obfuscation service and the hypervisor. The memory obfuscation service may enable the virtual machines to maintain at least a portion of sensitive information in an obfuscated format. The virtual machines may request access to the virtual machines' memory, the memory obfuscation service may obtain the requested memory in an obfuscated format and un-obfuscate the memory such that it may be used by the virtual machines.

Abstract: In a computer system configured to handle I/O signals received by the computer system from input devices and/or output signals output by the computer system, a virtual attachment module includes logic for selecting such that program code for coupling can alter the operating system's selection of I/O devices used for particular I/O device operations, coupling to a wireless I/O device at least for determining whether the wireless I/O device is available, and causing redirection of I/O signals destined to a default I/O device to be to the wireless I/O device, if the program code for coupling determines that the wireless I/O device is available. A virtual connection module could be used to intercept system messages indicating a wireless device is present and connected, determine whether the wireless device is present and/or connected, and determine which intercepted messages to forward, drop, delay or reformulate.

Abstract: Disclosed is a portable security device and method for detection and treatment of computer malware. An example method includes performing a malware detection experiment by the security device on the computer by simulating a connection to the computer of a simulated data storage device containing a predefined set of data. The method further includes determining if there are any modifications in the set of data contained in the simulated data storage device after termination of the malware detection experiment. The method further includes, based on whether there are any modifications in the set of data, determining whether to perform one or more subsequent malware detection experiments by the security device on the computer. In one example aspect, each of the one or more subsequent malware detection experiments are configured to simulate a different connection to the computer of a different simulated data storage device containing the predefined set of data.

Abstract: A system, method, and computer readable medium for hybrid kernel-mode and user-mode checkpointing of multi-process applications using a character device. The computer readable medium includes computer-executable instructions for execution by a processing system. A multi-process application runs on primary hosts and is checkpointed by a checkpointer comprised of a kernel-mode checkpointer module and one or more user-space interceptors providing barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Abstract: Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.

Abstract: A system, method, and computer readable medium for hybrid kernel-mode and user-mode checkpointing of multi-process applications. The computer readable medium includes computer-executable instructions for execution by a processing system. A multi-process application runs on primary hosts and is checkpointed by a checkpointer comprised of a kernel-mode checkpointer module and one or more user-space interceptors providing barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Abstract: Synchronizing access to resources in a hybrid computing environment that includes a host computer, a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module, where synchronizing access to resources includes providing in a registry, to processes executing on the accelerators and the host computer, a key associated with a resource, the key having a value; attempting, by a process, to access the resource including determining whether a current value of the key represents an unlocked state for the resource; if the current value represents an unlocked state, attempting to lock access to the resource including setting the value to a unique identification of the process; determining whether the current value is the unique identification of the process; if the current value is the unique identification accessing the resource by the process.

Abstract: An information processing apparatus that processes data to be protected is provided. The information processing apparatus includes a first storage unit, a second storage unit, and a cache control unit configured to cache data stored in the first storage unit into the second storage unit. The cache control unit is configured to lock a cache region in the second storage unit to thereby prevent cache data of the stored data from being written back into the first storage unit, the cache data being obtainable from the cache region in the second storage unit in which the stored data is cached, and write the data to be protected different from the stored data into the cache region in the second storage unit, after the cache region in the second storage unit is locked.

Abstract: A data processing apparatus and method are provided for managing access to content within the data processing apparatus. The data processing apparatus has a secure domain and a non-secure domain and comprises at least one device which is operable when seeking to access content stored in memory to issue a memory access request pertaining to either the secure domain or the non-secure domain. Further, writeable memory is provided which can store content required by the at least one device, with the writeable memory having at least one read only region whose content is stored therein under control of a secure task, the secure task being a task executed by one of the devices in the secure domain.

Abstract: A processing core in a multi-processing core system is configured to execute a sequence of instructions as an atomic memory transaction. Executing each instruction in the sequence comprises validating that the instruction meets a set of one or more atomicity criteria, including that executing the instruction does not require accessing shared memory. Executing the atomic memory transaction may comprise storing memory data from a source cache line into a target register, reading or modifying the memory data stored in the target register as part of executing the sequence, and storing a value from the target register to the source cache line.

Abstract: A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.

Abstract: A data protecting method for a memory, which comprising a volatile memory and a non-volatile memory for storing data and data protection information, comprises the following steps. Firstly, load the data protection information to the volatile memory from the non-volatile memory. Next, protect the data stored in the memory according to the data protection information stored in the volatile memory.

Abstract: Systems and methods to manage access to shared resources are provided. A particular method may include receiving a request to access a shared resource from a first client of a plurality of clients and determining whether the shared resource is being used. A first window credential associated with the first client may be retrieved. The first window credential may be one of a plurality of window credentials associated with the plurality of clients. The first window credential may be used to access the shared resource.

Abstract: Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example.

Abstract: A memory includes a plurality of areas corresponding to a plurality of segments of a storage device. An operation unit stores each of generated access instructions in an area corresponding to a segment of an access destination of the access instruction among the plurality of areas. The operation unit loads data of a segment corresponding to at least one area selected from the plurality of areas from the storage device to another area which is different from the plurality of areas on the memory, and executes an access instruction stored in the selected area, for the loaded segment data.

Abstract: Apparatus, systems, and methods may operate to assert a first semi-exclusive write lock with respect to a storage medium area by storing lock information when assertion of another semi-exclusive write lock with respect to the area is not detected. Additional activities may include writing data to the area by a writing entity that has asserted the first semi-exclusive write lock after determining the lock information has not changed, while substantially simultaneously de-asserting the first semi-exclusive write lock. Reading from the area may be determined as successful by determining that the semi-exclusive write lock was not asserted prior to or during the reading by checking the status of the lock information. Additional apparatus, systems, and methods are disclosed.

Abstract: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

Abstract: A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Abstract: According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided.

Abstract: An automatic mutual exclusion computer programming system is disclosed which allows a programmer to produce concurrent programming code that is synchronized by default without the need to write any synchronization code. The programmer creates asynchronous methods which are not permitted make changes to shared memory that they cannot reverse, and can execute concurrently with other asynchronous methods. Changes to shared memory are committed if no other thread has accessed shared memory while the asynchronous method executed. Changes are reversed and the asynchronous method is re-executed if another thread has made changes to shared memory. The resulting program executes in a serialized order. A blocking system method is disclosed which causes the asynchronous method to re-execute until the blocking method's predicate results in an appropriate value. A yield system call is disclosed which divides asynchronous methods into atomic fragments.

Abstract: An apparatus, system, and method are disclosed for implementing nameless storage operations. Storage clients can access and allocate portions of an address space of a non-volatile storage device to a nameless storage request. The methods include receiving from a storage client, a nameless storage request configured for storing data in an unspecified, available address of a logical block address of a non-volatile storage device, determining whether there exists enough logical capacity in the logical address space to satisfy the nameless storage request, allocating a logical identifier to the nameless storage request, and sending the allocated logical identifier to the storage client. Other embodiments are described.

Abstract: A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method.

Abstract: At least one virtual machine implemented on a given physical machine in an information processing system is able to detect the presence of one or more other virtual machines that are also co-resident on that same physical machine. More particularly, at least one virtual machine is configured to avoid usage of a selected portion of a memory resource of the physical machine for a period of time, and to monitor the selected portion of the memory resource for activity during the period of time. Detection of a sufficient level of such activity indicates that the physical machine is also being shared by at least one other virtual machine. The memory resource of the physical machine may comprise, for example, a cache memory, and the selected portion of the memory resource may comprise one or more randomly selected sets of the cache memory.

Abstract: A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.

Abstract: A method, computer program product, and computing system for receiving a reservation for a LUN from Host A, wherein the LUN is defined within a data array. A lock for the LUN is defined as Host A. A write request is received for the LUN from Host B. The lock for the LUN is defined as Transitioning A to B. The write request is delayed for a defined period of time.

Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.

Abstract: A method for managing data in a memory of a computer. The method includes the steps of: prohibiting a specified memory area in a memory from being accessed temporarily or intermittently; and attaching, to first data, a first mark indicating that the first data has been read when a page fault has occurred as a result of an access by any process to read on the first data; where the first data is present in a specified memory area prohibited from being accessed; and where at least one of the steps is carried out using a computer device.

Abstract: A multiprocessor system including a first processor element, and a second processor element that includes a CPU, a shared resource unit shared by the first and second processor elements, a protection setting unit and a guard unit, and the protection setting unit sets an access protection range for the shared resource unit, the guard unit restricts an access request from the first processor element to the shared resource unit based on the access protection range, the guard unit issues an exceptional access notification signal when the access request from the first processor element is within the access protection range, and when the exceptional access notification signal is issued, the CPU extends the access protection range in such a manner that the extended access protection range is wider than the access protection range set before issue of the exceptional access notification signal.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Abstract: A system and method for transactional memory using read-write locks is disclosed. Each of a plurality of shared memory areas is associated with a respective read-write lock, which includes a read-lock portion indicating whether any thread has a read-lock for read-only access to the memory area and a write-lock portion indicating whether any thread has a write-lock for write access to the memory area. A thread executing a group of memory access operations as an atomic transaction acquires the proper read or write permissions before performing a memory operation. To perform a read access, the thread attempts to obtain the corresponding read-lock and succeeds if no other thread holds a write-lock for the memory area. To perform a write-access, the thread attempts to obtain the corresponding write-lock and succeeds if no other thread holds a write-lock or read-lock for the memory area.

Abstract: A computer program product for mitigating conflicts for shared cache lines between an owning core currently owning a cache line and a requestor core. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes determining whether the owning core is operating in a transactional or non-transactional mode and setting a hardware-based reject threshold at a first or second value with the owning core determined to be operating in the transactional or non-transactional mode, respectively. The method further includes taking first or second actions to encourage cache line sharing between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the first or second value, respectively.

Abstract: A system for providing write-protection functionality to a memory device includes: a memory device including configurable registers controlling write and erase operations in the memory device; a system interface; a filter logic device in electrical communication with the memory device and further in communication with the system interface; and a power on reset circuit in communication with the system interface and the filter logic device, wherein the power on reset circuit asserts a reset signal to the system interface on startup of the system, further wherein, while the reset signal is asserted to the system interface, the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device and then the power on reset circuit de-asserts the reset signal to the system interface enabling communication between the system interface and the memory device.

Abstract: The present invention provides an approach for automatic storage planning and provisioning within a clustered computing environment (e.g., a cloud computing environment). The present invention will receive planning input for a set of storage area network volume controllers (SVCs), the planning input indicating a potential load on the SVCs and its associated components. Configuration data for a set of storage components (i.e., the set of SVCs, a set of managed disk (Mdisk) groups associated with the set of SVCs, and a set of backend storage systems) will also be collected. Based on this configuration data, the set of storage components will be filtered to identify candidate storage components capable of addressing the potential load. Then, performance data for the candidate storage components will be analyzed to identify an SVC and an Mdisk group to address the potential load.

Abstract: Cache lines are identified that provide incorrect data for read requests. The cache lines are invalidated before the incorrect data causes processing failure conditions. The cache lines providing incorrect data may be detected according to a number of the same read requests to the same cache lines. The cache lines may also be identified according to an amount of time between the same read requests to the same cache lines. The same read requests to the same cache lines may be identified according to associated start addresses and address lengths.

Abstract: A processing device comprises an instruction execution unit and track and combing logic to combine a plurality of transactions into a single combined transaction. The track and combine logic comprises a transaction monitoring module to monitor an execution of a plurality of transactions by the instruction execution unit, each of the plurality of transactions comprising a transaction begin instruction, at least one operation instruction and a transaction end instruction.

Abstract: A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

Abstract: In a disclosed embodiment, a data processing system comprises a memory protection unit (MPU); and a plurality of region descriptors associated with the MPU. Each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory. The subsets include data-only region descriptors, instruction-only region descriptors, and shared region descriptors. The shared region descriptors are used to access memory regions for data and instruction memory requests.

Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.

Abstract: A method of managing an electronic microcontroller system, the microcontroller system including: two processors with a first processor configured for execution of a nonsecure application exhibiting a nonguaranteed level of functional security and integrity, and a second processor dedicated to execution of a secure application implementing code and data, and involving a guaranteed level of functional security and integrity, the secure application to implement a security function; and a mechanism to access to a shared memory space. The first processor includes a unit for managing the memory configured to implement a write access control, to manage write access to the shared memory space, that is not modifiable when the secure application implements its security function.

Abstract: A disclosed example apparatus includes an interface (702, 726) to receive a request to access a memory (602a) of a memory module (600) and a data store status monitor (730) to determine a status of the memory. The example apparatus also includes a message output subsystem (732) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.

Abstract: A system implements dishonest policies for managing unauthorized access requests. The system includes memory management hardware to store a set of dishonest policy bits, each dishonest policy bit that is configured to a predetermined value indicating disallowed access for one of a set of memory ranges. When a processor receives an access request for a location in a memory range to which access is not allowed as indicated by a set dishonest policy bit, the processor returns a false indication according to a dishonest policy that the requested access has been performed.

Abstract: Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost.

Abstract: Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

Abstract: Techniques for achieving storage and network isolation in a cloud environment are presented. A single Internet Protocol (IP) address is presented to multiple storage tenants that use storage in a cloud environment. When each tenant accesses the IP address, a specific identity of the tenant is resolved and the storage stack for that tenant is sent to the tenant's storage machine having the tenant's storage. The tenant is directly connected to its tenant storage machine thereafter.

Abstract: One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction. The datapath is configured to provide the opcode and the operand to the arithmetic logic unit. The address violation detection logic determines whether a heap memory access is a violation according to the operand and the final address on receiving the compare signal from the arithmetic logic unit.