Abstract: A memory system comprises a nonvolatile memory including a plurality of blocks, a memory controller capable of controlling the nonvolatile memory, and a tag information management table in which tag information allocated to an address of data written to a block of nonvolatile memory, is stored, wherein the tag information is representative of the number of erasures of the block. The memory controller performs garbage collection of the nonvolatile memory based on the tag information.

Abstract: A peripheral circuit of a memory device is configured to: in the process of programming a first physical page, perform a programming verification to a programming corresponding to the 2(N?M) th memory state; when the program verification of the 2(N?M) th memory state is passed, identifiers corresponding to the 1st to 2(N?M) th memory states stored by the main latch are made different from those corresponding to the 2(N?M)+1st to 2N th memory states; release at least one of the N page latches to cache program data of at least one logical page of the N logical pages of a second physical page; and the programming data of one logical page in the N logical pages of the second physical page is stored in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N?2).

Abstract: Systems and methods for resolving data (DQ) line swapping configuration in Double Data Rate (DDR) memories are described. In an illustrative, non-limiting embodiment, a system may include a memory controller and a memory coupled to the memory controller, the memory having program instructions stored thereon that, upon execution, cause the system to: apply a first technique to resolve DQ line swapping between a memory interface and a memory module with respect to a first subset of a plurality of DQ lines; apply a second technique different than the first technique to resolve DQ line swapping with respect to a second subset of the plurality of DQ lines; and apply a third technique different than the first and the second techniques to resolve DQ line swapping with respect to a third subset of the plurality of DQ lines.

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Abstract: This disclosure describes techniques to perform convolutional neural networks (CNNs) on embedded devices. The techniques include operations comprising: accessing DNN information including definition of layers and weights of the DNN; obtaining cache or memory information for one or more cache or memory levels of the resource constrained embedded device; and configuring the DNN to be loaded onto the one or more cache or memory levels of the resource constrained embedded device based on the cache or memory information and the DNN information.

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

Abstract: An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.

Abstract: Disclosed are a convolution processing engine and a control method thereof, and a convolutional neural network accelerator comprising the convolution processing engine. The convolution processing engine comprises at least two cache memories connected in series and an operational circuit. The convolution processing engine can realize an efficient convolution operation with lower complexity and power consumption.

Abstract: A processor in a storage network operates by: receiving an access request for a data segment, wherein the data segment is encoded utilizing an error correcting information dispersal algorithm as a set of encoded data slices that are stored in a plurality of storage units of the storage network and wherein each encoded data slice of the set of encoded data slices includes a corresponding checksum of a plurality of checksums; retrieving, from the storage network, a subset of encoded data slices that includes a threshold number of encoded data slices of the set of encoded data slices; determining, based on ones of the plurality of checksums corresponding to the subset of encoded data slices, when the subset of encoded data slices includes at least one corrupted encoded data slice; retrieving from at least one of the plurality of storage units an addition number of encoded data slices required to generate a reconstructed data segment based on the subset of encoded data slices; generating the reconstructed data se

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

Abstract: A memory device includes a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to encrypt write data received via the communication interface to produce encrypted data, program a portion of the memory cells of the memory array with the encrypted data, read the encrypted data from the portion of the memory cells in response to a memory read request, decrypt the read encrypted data to produce read decrypted data only for portions of the read encrypted data not stored in purged regions of the memory array.

Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

Abstract: A flash translation layer with a rewind feature, and a method of operation. In some embodiments, the method includes: receiving, by a storage device, a first write command, for a first logical address; performing, by the storage device, a write to flash memory at a first physical address, corresponding to the first logical address; receiving, by the storage device, a first bookmarking command, for the first logical address; receiving, by the storage device, a second write command, for the first logical address; performing, by the storage device, a write to flash memory at a second physical address, corresponding to the first logical address; receiving, by the storage device, a first rewind command, for the first logical address; receiving, by the storage device, a read command, for the first logical address; and retrieving, by the storage device, in response to the read command, data from the first physical address.

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Abstract: Circuitry comprises memory access circuitry to control memory access by mapping virtual memory addresses in a virtual memory address space to physical memory addresses in a physical memory address space, the memory access circuitry being configured to provide a sparse mapping in which a mapped subset of the virtual memory address space is mapped to physical memory while an unmapped subset of the virtual memory address space is unmapped, the memory access circuitry being configured to discard write operations to virtual memory addresses in the unmapped subset of the virtual memory address space and processing circuitry to execute program code defining a processing operation to generate processed data and to store the processed data in a memory region of the virtual memory address space applicable to that processing operation; detector circuitry to detect whether the memory region is entirely within the unmapped subset of the virtual memory address space.

Abstract: Aspects of a storage device are provided that provide power control and power loss handling in a RAID system. The storage device may include a memory, a controller coupled to the memory, a power management circuit coupled to the memory and the controller, and a rechargeable battery coupled to the power management circuit. The controller may receive power supplied by a RAID controller, receive a notification of a loss in power supplied to another storage device, and cause the power management circuit to detect a charge of the rechargeable battery in response to the notification. The power management circuit may also detect another loss in power supplied by the RAID controller, cause the controller to send a message to the RAID controller indicating the loss in power, and receive power from the RAID controller in response to the message. As a result, UGSDs in RAID may be detected and addressed.

Abstract: A computer-implemented method according to one embodiment includes receiving a request to perform a transaction in persistent memory at a first node; implementing the transaction within a volatile transaction cache at the first node; determining parity data for the transaction at the first node; sending the parity data from the first node to a parity node; and transferring results of the transaction from the volatile transaction cache to the persistent memory at the first node.

Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.

Abstract: Disclosed systems and methods initiate an instance of an isolated application on a node computing device. The systems determine that the isolated application requests exclusive access to a block storage resource, create a control group associated with the block storage resource to provide access to members of the control group and set an access rate limit to zero for non-members of the control group, and assig the isolated application to the control group.

Abstract: Predicting failures in a storage system that includes a plurality of storage devices, including: gathering information describing a plurality of blocks within the storage devices; developing, using the information describing the plurality of blocks within the storage devices and information describing known dead block conditions, a block lifespan model; and determining, in dependence upon the information describing the plurality of blocks within the storage devices and the block lifespan model, a predicted lifespan for the plurality of blocks within the storage devices.

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning. A method of embodiments, as described herein, includes limiting execution of workloads for the respective contexts of a plurality of contexts to a specified subset of a plurality of processing resources of a processing system according to physical resource slices of the processing system that are associated with the respective contexts of the plurality of contexts.

Abstract: Chiplet systems may include a memory controller that has programmable atomic units that execute programmable atomic transactions. These instructions are stored in one or more memory partitions of memory in the programmable atomic unit. Since the programmable atomic unit executes programmable atomic transactions that are customized for various processes, and since the programmable atomic unit is a physical resource shared by multiple processes, the processes need a way of both loading the programmable atomic unit memory with instructions and a method of calling those instructions. Disclosed are methods, systems, and devices for registering, calling, and virtualizing programmable atomic transactions.

Abstract: A method includes receiving, by a storage unit of a set of storage units of a storage network, a write request regarding an encoded data slice, where the write request includes a slice payload and a corresponding revision level of the encoded data slice. The method further includes determining whether the corresponding revision level of the encoded data slice is a next revision level. The method further includes generating a write response message that includes a status message for the encoded data slice based on the determining whether the corresponding revision level of the encoded data slice is the next revision level, where when the corresponding revision level is the next revision level, the status message includes an operation succeeded message. The method further includes sending the write response message to a computing device of the storage network.

Abstract: In a complex system including; one or more storage systems including a cache and a storage controller; and one or more storage boxes including a storage medium, the storage box generates redundant data from write data received from a server, and writes the write data and the redundant data to the storage medium. The storage box transmits the write data to the storage system when it is difficult to generate the redundant data or it is difficult to write the write data and the redundant data to the storage medium. The storage system stores the received write data in the cache.

Abstract: A system and a method are disclosed that efficiently supports an append operation in an object storage system. A size of data received with a request for an append operation from an application is determined based on a data-alignment characteristic of a storage medium. Data that is not aligned with the data-alignment characteristic is stored in persistent memory and aggregated with other data from the application that is not aligned with the data-alignment characteristic, while data that is aligned with the data-alignment characteristic is stored directly in the storage medium. Aggregated data that becomes aligned with the data-alignment characteristic as additional requests for append operations are received are migrated to the storage medium.

Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

Abstract: Certain embodiments described herein relate to an improved selective data backup system. In some embodiments, one or more components in an information management system can determine that a portion of the primary data scheduled for backup was previously backed up or is scheduled to be backed up as part of another backup operation. For example, a data agent performing a cluster-level backup operation for an entire cluster of storage servers may check whether any part of the primary data was previously backed up by a prior server-level backup operation for one of the storage servers in the cluster. If so, the data agent may skip, in the cluster-level backup operation, any portion of the primary data stored in the storage server previously backed up as part of the prior server-level backup operation.

Abstract: An all flash array storage device includes a flash memory array including multiple flash memories and a microprocessor. The flash memories correspond to multiple logical aggregation units. Each logical aggregation unit includes multiple stripes. Each stripe includes multiple storage units, including multiple data units and at least one parity unit. The microprocessor detects a status of the flash memories. In response to a detection result indicating that one of the flash memories has been removed from the flash memory array, the microprocessor sequentially performs a repair operation on the stripes comprised in one or more logical aggregation units that have been written with data. In the repair operation of one stripe, the microprocessor recalculates protection information of the stripe according to content stored in a portion of data units of the stripe and writes the recalculated protection information in one or more storage units of the stripe.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

Abstract: Apparatus and methods are disclosed, including a memory device with circuitry to generate an amount of parity data, and to store at least a portion of the parity data within a dummy data location. Selected examples include storing meta data with the parity data to further facilitate data recovery. Selected examples include a memory device with circuitry to generate one or more parity data index entries that map protected data to parity data.

Abstract: A processor performance measurement apparatus according to an embodiment includes a processor, in which the processor detects that a memory access occurs, the memory access being required to execute processing units or execute execution units by a processor to be measured, performs first estimation for estimating switching of the processing units or the execution units and second estimation for estimating which of the one or more processing units the processing unit being executed is or to which of the one or more processing units the execution unit being executed corresponds based on an address of an access destination of the memory access, measures respective performances in the processing units or the execution units based on an estimation result of the first estimation, and aggregates respective measurement results of the performances for each of the processing units based on an estimation result of the second estimation.

Abstract: Generally discussed herein are systems, devices, and methods for prefetcher in a multi-tiered memory (DSM) system. A node can include a network interface controller (NIC) comprising system address decoder (SAD) circuitry configured to determine a node identification of a node to which a memory request from a processor is homed, and prefetcher circuitry communicatively coupled to the SAD circuitry, the prefetcher circuitry to determine, based on an address in the memory request, one or more addresses from which to prefetch data, the one or more addresses corresponding to respective entries in a memory of a node on a different network than the NIC.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: Systems and methods for retrieving a set of ordered items from a distributed database. A plurality of ordered items may be stored at a cache. The plurality of ordered items may have a length of N+B at a first instant in time. A first instruction to delete a first item of the plurality of ordered items may be received. A second instruction to add a second item to the plurality of ordered items may be received. The first instruction and the second instruction may be stored in a change log. A request for the first N items of the plurality of ordered items may be received. The first instruction may be executed by deleting the first item from the plurality of ordered items. The second instruction may be executed by adding the second item to the plurality of ordered items. The first N items of the plurality of ordered items may be sent in response to the request.

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

Abstract: A storage reclamation orchestrator is implemented to identify and recover unused storage resources on a storage system. The storage reclamation orchestrator analyses storage usage attributes of storage groups occupying storage resources of the storage system. The storage reclamation orchestrator assigns individual usage point values to each storage usage attribute of a given storage group. The individual usage point values are combined to assign a final usage point value to the storage group. Storage groups with usage point values above a threshold are candidate storage groups for recovery on the storage system. Example storage usage attributes include whether the storage group has been masked to a host device, an amount of time since IO activity has occurred on the storage group, an amount of time since local protection was implemented on the storage group, and an amount of time since remote protection was implemented on the storage group.

Abstract: An example printing method can involve a memory buffer of a printing system containing image data, and the method can include (i) issuing, by an initiator of the printing system, a single read-then-clear memory command; (ii) receiving, by a memory controller of the printing system, the single read-then-clear memory command; and (iii) in response to receiving the single read-then-clear memory command, the memory controller both (a) reading the image data from the memory buffer of the printing system and (b) after reading the image data, clearing the image data from the memory buffer of the printing system.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: storing first management information in a rewritable non-volatile memory module, wherein the first management information reflects a storage status of abnormal data in a first physical unit in the rewritable non-volatile memory module; receiving a read command from a host system, wherein the read command instructs to read data stored in a logical unit corresponding to a physical node in the first physical unit; inquiring the first management information according to the read command; transmitting data read from the physical node to the host system if an inquiring result reflects that the abnormal data is not stored in the physical node; and transmitting error information to the host system if the inquiring result reflects that the abnormal data is stored in the physical node.

Abstract: A RAID storage-device-assisted data update system includes a RAID storage controller coupled to first RAID storage devices each including respective first RAID storage subsystems. Each first RAID storage devices receives a command from the RAID storage controller that identifies a second RAID buffer subsystem as a target memory location and, in response, retrieves respective first RAID storage device data from its respective first RAID storage subsystem and performs DMA operations to provide that first RAID storage device data on the second RAID buffer subsystem. A second RAID storage device that includes the second RAID buffer subsystem and a second RAID storage subsystem receives a command from the RAID storage controller and, in response, performs an XOR operation using the first RAID storage device data in the second RAID buffer subsystem to produce update data that it stores in its second RAID storage subsystem.

Abstract: In an approach to failed media channel recovery throttling, responsive to detecting a programming error on an addressable unit during programming of a block stripe, the block stripe is placed on a recovery/data migration queue. An error counter for the addressable unit on which the programming error occurred is incremented. The block stripes from the recovery/data migration queue are built excluding a specific channel containing the addressable unit on which the programming error occurred. Responsive to determining that the queue for the recovery/data migration is empty, building the block stripes resumes using the plurality of channels, where the specific channel containing the addressable unit on which the programming error occurred is included. Responsive to determining that a number of errors on a specific addressable unit exceeds a predetermined threshold based on the error counter for the specific addressable unit, the specific addressable unit is decommissioned.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: A storage system for continuing I/O without affecting drive box addition to a host computer includes: a plurality of drive boxes for connecting to a computer device that transmits commands for data reads or writes; and a storage controller connected to the drive boxes. A first drive box provides a first storage region to the computer device. The storage controller manages correspondence between the first storage region and a physical storage region of the drives constituting the first storage region. The first drive box receives a command for the first storage region from the computer device and transfers the command to the storage controller. The storage controller generates a data transfer command including a data storage destination based on the address management table, and transfers the command to the first drive box. The first drive box then transfers the data transfer command to the second drive box.

Abstract: In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to determine whether to effect the update and to make the update. Updates can include one or more of incrementing and swapping values. An update request may specify one of a pre-determined set of update types. Some update types may be conditional and others unconditional. The update unit can be coupled to receive update requests from a plurality of computation units. The computation units may not have privileges to directly generate write requests to be effected on at least some of the locations in memory. The computation units can be fixed function circuitry operating on inputs received from programmable computation elements. The update unit may include a buffer to hold received update requests.

Abstract: A data processing method for a convolutional neural network includes: (a) obtaining a matrix parameter of an eigenmatrix; (b) reading corresponding data in an image data matrix from a first buffer space based on the matrix parameter through a first bus, to obtain a next to-be-expanded data matrix, and sending and storing the to-be-expanded data matrix to a second preset buffer space through a second bus; (c) reading the to-be-expanded data matrix, and performing data expansion on the to-be-expanded data matrix to obtain expanded data; (d) reading a preset number of pieces of unexpanded data in the image data matrix, sending and storing the unexpanded data to the second preset buffer space, and updating, based on the unexpanded data, the to-be-expanded data matrix; and (e). repeating (c) and (d) until all data in the image data matrix is completely read out on the to-be-expanded data matrix.

Abstract: A computer-implemented method according to one embodiment includes initiating a read-modify-write (RMW) operation; assigning the RMW operation to a thread; identifying a storage device associated with the RMW operation; assign a log block within the storage device to the thread; determining a free shadow block location within the storage device; creating a copy of data to be written to the storage device during the RMW operation; writing the copy of the data to the free shadow block location within the storage device; updating the log block within the storage device to point to the free shadow block location to which the copy of the data is written; and writing the data to one or more blocks of a home area of the storage device.

Abstract: A processing device, operatively coupled with a memory device, is configured to receive a write request identifying data to be stored in a segment of the memory device. The processing device determines a write-to-write (W2W) time interval for the segment and determines whether the W2W time interval falls within a first W2W time interval range, the first W2W time interval range corresponds to a first pre-read voltage level. Responsive to the W2W time interval for the segment falling within the first W2W interval range, the processing device performs a pre-read operation on the segment using the first pre-read voltage level. The processing device identifies a subset of the data to be stored in the segment comprising bits of data that are different than corresponding bits of the data stored in the segment. The processing device further performs a write operation to store the subset of the data in the segment.

Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

Abstract: A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

Abstract: A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data. A processor of the DSD receives a command from a host to access data in the NVM, and performs the command to access data in the NVM. The DSD further includes a host-trusted module functionally isolated from at least a portion of the DSD. The host-trusted module is configured to receive an instruction from the host, and perform an operation based on the instruction. According to one aspect, the operation includes a predetermined atomic operation to modify data stored in the NVM.