Read-modify-write (rmw) Patents (Class 711/155)
  • Patent number: 10503642
    Abstract: A data processing method includes allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 10, 2019
    Assignees: Huawei Technologies Co., Ltd., National University of Singapore
    Inventors: Yuan Yao, Tulika Mitra, Zhiguo Ge, Naxin Zhang
  • Patent number: 10482337
    Abstract: Convolutional neural network (CNN) components can operate to provide various speed-ups to improve upon or operate as part of an artificial neural network (ANN). A convolution component performs convolution operations that extract data from one or more images, and provides the data to one or more rectified linear units (RELUs). The RELUs are configured to generate non-linear convolution output data. A pooling component generates pooling outputs in parallel with the convolution operations via a pipelining process based on a pooling window for a subset of the non-linear convolution output data. A fully connected (FC) component configured to form an artificial neural network (ANN) that provides ANN outputs based on the pooling outputs and enables a recognition of a pattern in the one or more images based on the ANN outputs. Layers of the FC component are also able to operate in parallel in another pipelining process.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventor: Prakash Kalanjeri Balasubramanian
  • Patent number: 10459850
    Abstract: Systems, apparatuses, and methods for implementing virtualized process isolation are disclosed. A system includes a kernel and multiple guest virtual machines (VMs) executing on the system's processing hardware. Each guest VM includes a vShim layer for managing kernel accesses to user space and guest accesses to kernel space. The vShim layer also maintains a set of page tables separate from the kernel page tables. In one embodiment, data in the user space is encrypted and the kernel goes through the vShim layer to access user space data. When the kernel attempts to access a user space address, the kernel exits and the vShim layer is launched to process the request. If the kernel has permission to access the user space address, the vShim layer copies the data to a region in kernel space and then returns execution to the kernel. The vShim layer prevents the kernel from accessing the user space address if the kernel does not have permission to access the user space address.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 29, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David A. Kaplan
  • Patent number: 10445242
    Abstract: The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 15, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Pulkit Misra
  • Patent number: 10447316
    Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Bing Shang, Yu Zhang, Hong Wen Li, Yu Peng Fan, Zhong Lai Liu, En Peng Gao, Liang Zhang
  • Patent number: 10423215
    Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 24, 2019
    Assignee: Cavium, LLC
    Inventors: Kalyana S. Venkataraman, Gregg A. Bouchard, Eric Marenger, Ahmed Shahid
  • Patent number: 10402937
    Abstract: A method for rendering graphics frames allocates rendering work to multiple graphics processing units (GPUs) that are configured to allow access to pages of data stored in locally attached memory of a peer GPU. The method includes the steps of generating, by a first GPU coupled to a first memory circuit, one or more first memory access requests to render a first primitive for a first frame, where at least one of the first memory access requests targets a first page of data that physically resides within a second memory circuit coupled to a second GPU. The first GPU requests the first page of data through a first data link coupling the first GPU to the second GPU and a register circuit within the first GPU accumulates an access request count for the first page of data. The first GPU notifies a driver that the access request count has reached a specified threshold.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 3, 2019
    Assignee: NVIDIA Corporation
    Inventors: Rouslan L. Dimitrov, Kirill A. Dmitriev, Andrei Khodakovsky, Tzyywei Hwang, Wishwesh Anil Gandhi, Lacky Vasant Shah
  • Patent number: 10394487
    Abstract: A memory system may include: a memory device including memory blocks each memory block including pages, each page including memory cells which are coupled to a word line for storing data; and a controller including a memory, the controller receiving a write command and a read command from a host, storing write data corresponding to the write command in the memory, transmitting and storing the write data stored in the memory to and in at least one first memory device buffer coupled to a first memory block in a page of which the write data are to be stored, reading read data corresponding to the read command from a page of a second memory block, storing the read data in at least one second memory device buffer coupled to the second memory block, and storing the read data stored in the second memory device buffer, in the memory.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10331559
    Abstract: Exemplary methods, apparatuses, and systems include a first input/output (I/O) filter receiving, from a first filter module within a virtualization stack of a host computer, an input/output (I/O) request originated by a virtual machine and directed to a first virtual disk. The first I/O filter determines to redirect the I/O request to a second virtual disk and, in response, forwards the I/O request to a second I/O filter associated with the second virtual disk. The first I/O filter is a part of a first instance of a filter framework within the host computer and the second I/O filter is part of a second, separate instance of the filter framework.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 25, 2019
    Assignee: VMware, Inc.
    Inventors: Christoph Klee, Adrian Drzewiecki, Aman Nijhawan
  • Patent number: 10297298
    Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jens Polney
  • Patent number: 10198373
    Abstract: Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips and a methodology for operating the computer system. The memory buffer chips may be communicatively coupled to at least one memory module which can be configured for storing memory lines and assigned to the memory buffer chip. The processor chips can include a cache configured for caching memory lines. The processor chips may be communicatively coupled to the memory buffer chips via a memory-buffer-chip-specific bidirectional serial point-to-point communication connection. The processor chips can be configured for transferring memory lines between the cache of the processor chip and the memory modules via the respective memory-buffer-chip-specific bidirectional serial point-to-point communication connection.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 10114557
    Abstract: Systems, methods and/or devices are used to enable identification of hot regions to enhance performance and endurance of a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region is accessed by the plurality of I/O requests more than a predetermined threshold number of times during a predetermined time period, (b) if so, marking the region with a hot region indicator, and (c) while the region is marked with the hot region indicator, identifying open blocks associated with the region, and marking each of the identified open blocks with a hot block indicator.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Dharani Kotte, Akshay Mathur, Chayan Biswas, Sumant K. Patro
  • Patent number: 10108569
    Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez
  • Patent number: 10102165
    Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez
  • Patent number: 9880764
    Abstract: Systems, methods, and computer readable media are disclosed. A map including the number of dirty cache pages stored in the flash disk cache for each VLUN of the plurality of VLUNs on the storage system is maintained, by the storage system. A flash disk cache error requiring the storage system to take the flash disk cache offline is detected. In response to detecting the flash disk cache error a first one or more VLUNs of the plurality of VLUNs with at least one dirty cache page stored in the flash disk cache are identified by the storage system based on the map. The first one or more VLUNs are taken offline by the storage system. The flash disk cache is taken offline by the storage system. A second one or more VLUNs comprising VLUNs of the plurality of VLUNs without dirty cache pages stored in the flash disk cache are maintained online by the storage system.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Xinlei Xu, Jian Gao, Lifeng Yang, Geng Han, Jibing Dong, Lili Chen
  • Patent number: 9875039
    Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Chetan Agrawal, Dinesh Agarwal, Vijay Sivasankaran
  • Patent number: 9854072
    Abstract: An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: December 26, 2017
    Assignee: Netronome Systems, Inc.
    Inventors: Chirag P. Patel, Gavin J. Stark
  • Patent number: 9830281
    Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichiro Omura, Ryohei Yoshida, Takanobu Naruse, Seiichi Saito
  • Patent number: 9818462
    Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 14, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Jens Polney
  • Patent number: 9812177
    Abstract: A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu
  • Patent number: 9804842
    Abstract: An apparatus and method for efficiently managing the architectural state of a processor.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 31, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jesus Corbal San Adrian, Dennis R. Bradford, Benjamin C. Chaffin, Taraneh Bahrami, Jonathan C. Hall, Thomas B. Maciukenas, Roger Gramunt, Rohan Sharma
  • Patent number: 9734063
    Abstract: A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA uses a remote memory controller—an architecturally-exposed hardware block integrated into the node's local coherence hierarchy.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 15, 2017
    Assignee: ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE (EPFL)
    Inventors: Stanko Novakovic, Alexandros Daglis, Boris Robert Grot, Edouard Bugnion, Babak Falsafi
  • Patent number: 9645924
    Abstract: A computer processor determines an over-provisioning ratio and a host write pattern. The computer processor determines a write amplification target based on the host write pattern and the over-provisioning ratio. The computer processor determines a staleness threshold, wherein the staleness threshold corresponds to a ratio of valid pages of a block to total pages of the block. The computer processor erases a first block having a staleness which exceeds the staleness threshold.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Aaron D. Fry, Samuel K. Ingram, Lincoln T. Simmons
  • Patent number: 9626260
    Abstract: A read/write cache device and method persistent in the event of a power failure are disclosed herein. The read/write cache device includes a meta-information part, a recency/frequency (RF) table part, a mapping table part, and a log area. The meta-information part provides information about whether metadata has integrity and information about the version of metadata stored in two metadata regions. The RF table part provides information about the recency and frequency of each of low-speed segments of a plurality of high-speed and low-speed segments and information about whether each of the low-speed segments is cached, in order to maintain the consistency of the metadata. The mapping table part provides information about a low-speed segment that is cached to each of the high-speed segments. The log area provides changed caching information that is not applied into the mapping table part.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: April 18, 2017
    Assignee: JUNGWON UNIVERSITY INDUSTRY ACADEMY COOPERATION CORPS.
    Inventor: Sung Hoon Baek
  • Patent number: 9558821
    Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: January 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Dae-Seok Byeon, Yeong-Taek Lee, Hyo-Jin Kwon, Yong-Kyu Lee
  • Patent number: 9558796
    Abstract: Enhanced memory circuits are described that maintain coherency between concurrent memory reads and writes in a pipelined memory architecture. The described memory circuits can maintain data coherency regardless of the amount of pipelining applied to the memory inputs and/or outputs. Moreover, these memory circuits may be implemented as dedicated hard circuits in a field programmable gate array (FPGA) or other programmable logic device (PLD), and can be supplemented with user-configurable logic to achieve coherency in a variety of applications.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventors: Carl Ebeling, Pohrong Rita Chu
  • Patent number: 9535842
    Abstract: Each computing node of a distributed computing system may implement a hardware mechanism at the network interface for message driven prefetching of application data. For example, a parallel data-intensive application that employs function shipping may distribute respective portions of a large data set to main memory on multiple computing nodes. The application may send messages to one of the computing nodes referencing data that is stored locally on the node. For each received message, the network interface on the recipient node may extract the reference, initiate the prefetching of referenced data into a local cache (e.g., an LLC), and then store the message for subsequent interpretation and processing by a local processor core. When the processor core retrieves a stored message for processing, the referenced data may already be in the LLC, avoiding a CPU stall while retrieving it from memory. The hardware mechanism may be configured via software.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: January 3, 2017
    Assignee: Oracle International Corporation
    Inventors: Herbert D. Schwetman, Jr., Mohammad Arslan Zulfiqar, Pranay Koka
  • Patent number: 9513830
    Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Holloway H. Frost, Charles J. Camp, Kenneth Scianna, Lance W. Shelton
  • Patent number: 9448946
    Abstract: Systems, methods and/or devices are used to enable a stale data mechanism. In one aspect, the method includes (1) receiving a write command specifying a logical address to which to write, (2) determining whether a stale flag corresponding to the logical address is set, (3) in accordance with a determination that the stale flag is not set, setting the stale flag and releasing the write command to be processed, and (4) in accordance with a determination that the stale flag is set, detecting an overlap, wherein the overlap indicates two or more outstanding write commands are operating on the same memory space.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James M. Higgins, Theron W. Virgin
  • Patent number: 9424443
    Abstract: In general, embodiments of the invention include methods and apparatuses for securely storing computer system data. Embodiments of the invention encrypt and decrypt SATA data transparently to software layers. That makes it unnecessary to make any software modifications to the file system, device drivers, operating system, or application. Encryption key management is performed either remotely on a centralized Remote Management System or locally. Embodiments of the invention implement background disk backups using snapshots. Additional security features that are included in embodiments of the invention include virus scanning, a virtual/network drive, a RAM drive and a port selector that provides prioritized and/or background access to SATA mass storage to a secure subsystem.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 23, 2016
    Assignee: Janus Technologies, Inc.
    Inventors: Michael Wang, Joshua Porten, Sofin Raskin, Mikhail Borisov
  • Patent number: 9372751
    Abstract: A mechanism is provided for optimizing free space collection in a storage system having a plurality of segments. A collection score value is calculated for least one of the plurality of segments. The collection score value is calculated by determining a sum, across tracks in the segment, of the amount of time over a predetermined period of time during which the track has been invalid due to a more recent copy being written in a different segment. Segments are chosen for free space collection based on the determined collection score value.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 21, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Bruce McNutt
  • Patent number: 9324361
    Abstract: A method including: reading a portion of stored data from a storage medium, decrypting the portion of stored data, then if changes are requested, making the changes to the portion of stored data to produce changed data, encrypting the changed data, and writing the encrypted changed data to the storage medium. An apparatus that performs the method is also included.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: April 26, 2016
    Assignee: Seagate Technology LLC
    Inventor: Laszlo Hars
  • Patent number: 9323666
    Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises determining whether to reclaim one or more blocks of a memory. The method further comprises allocating at least one of the blocks to be written in accordance with the equalizing, in response to the determining, and selected from a subset of the blocks, wherein a respective lifetime factor is below a threshold set prior to the allocating.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 26, 2016
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • Patent number: 9286230
    Abstract: A method, computer program product, and computer system for instantiating, by a computing device, a slice-object associated with a slice when the slice-object is accessed. The slice-object is released to a slice object cache when accessing is complete. It is determined whether the slice is accessed within a threshold period of time. If the slice is accessed within the threshold period of time, the slice-object is retrieved from the slice-object cache. If the slice is not accessed within the threshold period of time, memory used for the slice-object is released.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 15, 2016
    Assignee: EMC Corporation
    Inventors: Ye Zhang, Jean-Pierre Bono, William C. Davenport, Yining Si, Qi Mao, Alexander M. Daniel
  • Patent number: 9251062
    Abstract: An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device. A conditional storage request is provided, which causes data to be stored to the non-volatile storage device on the condition that the address space of the device can satisfy the entire request. If only a portion of the request can be satisfied, the conditional storage request may be deferred or fail. An atomic storage request is provided, which may comprise one or more storage operations. The atomic storage request succeeds if all of the one or more storage operations are complete successfully. If one or more of the storage operations fails, the atomic storage request is invalidated, which may comprise deallocating logical identifiers of the request and/or invalidating data on the non-volatile storage device pertaining to the request.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: February 2, 2016
    Assignee: Intelligent Intellectual Property Holdings 2 LLC
    Inventors: David Flynn, David Nellans, Xiangyong Ouyang
  • Patent number: 9218858
    Abstract: An operating method of a data storage device may include performing a first write operation on a first memory region, and performing a second write operation on a second memory region to store position information on the first write operation.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 22, 2015
    Assignee: SK Hynix Inc.
    Inventor: Ju Yong Shin
  • Patent number: 9213546
    Abstract: Embodiments of the present invention relate to a method and system for performing a memory copy. In one embodiment of the present invention, there is provided a method for performing memory copy, including: decoding a memory copy instruction into at least one microcode in response to receipt of the memory copy instruction, transforming the at least one microcode into a ReadWrite Command for each of the at least one microcode, and notifying a memory controller to execute the ReadWrite Command, wherein the ReadWrite Command is executed by the memory controller and comprises at least a physical source address, a physical destination address and a ReadWrite length that are associated with the ReadWrite Command. In another embodiment of the present invention, there is provided a system for performing a memory copy.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Xiao T. Chang, Fei Chen, Kun Wang, Wen X. Wang, Yu Zhang, Wei Wang
  • Patent number: 9128876
    Abstract: Contents of a memory are encrypted using an encryption key that is generated based on a random number and a memory location at which the contents are stored. Each of a plurality of locations of a memory can be associated with a respective unique pointer value, and an encryption key may be generated based on the unique pointer value and the random number. In some examples, the random number is unique to a power-up cycle of a system comprising the memory or is generated based on a time at which the data to be stored by the memory at the selected memory location is written to the memory.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 8, 2015
    Assignee: Honeywell International Inc.
    Inventors: Thomas Cordella, John Profumo, James L. Tucker
  • Patent number: 9058162
    Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 16, 2015
    Assignee: Sony Corporation
    Inventors: Naohiro Adachi, Keiichi Tsutsui, Kenichi Nakanishi, Hideaki Okubo, Yasushi Fujinami, Ken Ishii
  • Patent number: 9043565
    Abstract: A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Tanaka, Takeyuki Minamimoto
  • Patent number: 9021316
    Abstract: A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Frederic Bancel
  • Publication number: 20150081988
    Abstract: A method for executing a program in parallel includes creating a program replica, which includes a write operation on and an identifier of an object and is a copy of the program, for a thread. The identifier specifies whether the object is thread-local. The method includes modifying the write operation based on a speculation that the write operation uses only thread-local objects. The write operation executes in a transaction of the thread. The method includes determining, while executing the program replica and using the identifier, that the object used by the write operation is not thread-local, de-optimizing the write operation by adding instrumentation to implement a software transactional memory (STM) system for the write operation to obtain a de-optimized write operation, and performing the de-optimized write operation on the object to obtain a result and store the result in a redo log.
    Type: Application
    Filed: January 31, 2014
    Publication date: March 19, 2015
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Daniele Bonetta, Thomas Wuerthinger
  • Publication number: 20150074358
    Abstract: A method of writing data to a range of logical blocks in a storage medium includes: receiving a command including a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data; storing the logical block in a first temporary storage; generating a logical page by duplicating the logical block a plurality of times corresponding to a number of logical blocks in a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage; writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address; and performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicants: Skyera, Inc., Western Digital Technologies, Inc.
    Inventors: JACK W. FLINSBAUGH, JUSTIN JONES, RODNEY N. MULLENDORE, ANDREW J. TOMLIN
  • Patent number: 8977730
    Abstract: A method, a system, and a computer program product are provided for reducing message passing for contention detection in distributed SIP server environments. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to determine that a first site is waiting for a first object locked by a second site. The programming instructions are further operable to determine that a third site is waiting for a second object locked by the first site, and to send a first probe to the second site to determine whether the second site is waiting. A second probe is received and indicates that a site is waiting for an object locked by the first site. The second probe further indicates a deadlock in a distributed server environment to be resolved.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Abhinay R. Nagpal, Sandeep R. Patil, Sri Ramanathan, Gandhi Sivakumar, Matthew B. Trevathan
  • Publication number: 20150039844
    Abstract: A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 5, 2015
    Inventors: Wing-Hin Kao, Jongsik Na
  • Patent number: 8949312
    Abstract: An embodiment generally relates to a method of updating clients from a server. The method includes maintaining a master copy of a software on a server and capturing changes to the master copy of the software on an update disk image, where the changes are contained in at least one chunk. The method also includes merging the update disk image with one of two client disk images of the client copy of the software.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: February 3, 2015
    Assignee: Red Hat, Inc.
    Inventors: Mark McLoughlin, William Nottingham, Timothy Burke
  • Patent number: 8938591
    Abstract: A new data block to be stored in the dispersed storage system is received. When it is determined that a previous data segment contains sufficient space for the new data block, the previous data segment is retrieved from a plurality of dispersed storage units. A revised data segment is generated by aggregating the new data block with at least one existing data block of the previous data segment. A plurality of slices are generated for the revised data segment. The plurality of slices are stored in the plurality of dispersed storage units.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 20, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Zachary J. Mark, S. Christopher Gladwin
  • Publication number: 20140379953
    Abstract: In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Peter J. Heyrman, Venkat R. Indukuru, Carl E. Love, Aaron C. Sawdey, Philip L. Vitale
  • Patent number: 8914592
    Abstract: According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akinori Harasawa, Tohru Fukuda
  • Publication number: 20140359201
    Abstract: A technique includes identifying a dependency between a first persistent memory region and at least one other persistent memory region. The technique includes using a process having access to the first persistent memory region to selectively perform garbage collection for the first persistent memory region based at least in part on whether the process has access to the other persistent memory region(s) from which the first persistent memory region depends.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventor: Dhruva Chakrabarti