Control Technique Patents (Class 711/154)
  • Patent number: 10353454
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, a second memory, and a controller. The processing device is configured to process first data. The first memory is configured to store at least part of the first data and has an active region supplied with power necessary for holding data. The second memory is configured to store part of the first data. The controller is configured to change number of active regions such that processing information is not more than a threshold. The processing information indicates an amount of processing for moving at least part of second data stored in the first memory to the second memory and for moving at least part of third data stored in the second memory to the first memory, in a certain period for processing the first data having a size larger than active regions.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura, Satoshi Shirai
  • Patent number: 10353589
    Abstract: A data management method includes steps of: receiving a read command; reading a page containing target data from a non-volatile memory when the target data corresponding to the read command is stored in the non-volatile memory; determining whether a count of reading of the page is greater than a read threshold; and if false, storing at least one record of subsequent data into a first storage space of a data buffering storage device; or if true, storing the at least one record of subsequent data into a second storage space of the data buffering storage device. Both of the target data and the at least one record of subsequent data are stored in the page, and the target data and the at least one record of subsequent data have a sequential relationship in terms of data reading. Another data management method and a corresponding data storage device are also provided.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: July 16, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Teng-Chi Liang, Yen-Ting Yeh
  • Patent number: 10353768
    Abstract: A computer including a processor and a memory and a storage device that is connected to the computer and stores data has an FPGA that acquires data and an operation command from a control unit that controls reading and writing with respect to a non-volatile semiconductor storage unit to perform a data operation. The computer generates and transmits the operation command from an access request that has been received to the storage device. The computer receives execution results for the operation command from the storage device, and when the number of execution results for the operation command reaches a prescribed value, instructs the FPGA to detect a soft error, receives all execution results with respect to the generated operation command, and if there is no soft error, transmits the execution results.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 16, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Watanabe, Yoshiki Kurokawa, Yoshitaka Tsujimoto
  • Patent number: 10346419
    Abstract: A system for data conversion comprises an interface and a processor. The interface is to receive a data conversion definition. The processor is to store an indication of data requiring data conversion; launch a data traverser and an on-the-fly converter; and in the event that data requested to be accessed requires data conversion: convert, using the on-the-fly converter, data to a converted data using the data conversion definition and provide the converted data.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 9, 2019
    Assignee: Workday, Inc.
    Inventors: Salvador Maiorano Quiroga, Vishal Garg, Zhenpeng Li
  • Patent number: 10340018
    Abstract: A memory device having an improved program speed may include a memory cell array including a plurality of memory cells, each being programmed to one of a plurality of program states; a peripheral circuit configured to perform a program operation to one or more of the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation; and a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Hee Youl Lee, Sung Ho Bae
  • Patent number: 10331296
    Abstract: A dual-screen user device and methods for launching applications from a revealed desktop onto a logically chosen screen are disclosed. Specifically, a user reveals the desktop and then launches a selected application from one of two desktops displayed on a primary and secondary screen of a device. When the application is launched, it is displayed onto a specific screen depending on the input received and the logical rules determining the display output. As the application is displayed onto the specific screen, the desktop is removed from display and the opposite screen can display other data.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 25, 2019
    Assignee: Z124
    Inventors: Sanjiv Sirpal, Martin Gimpl
  • Patent number: 10331587
    Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 25, 2019
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Thomas J. Giovannini
  • Patent number: 10324846
    Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin Recktenwald, Willm Hinrichs
  • Patent number: 10324847
    Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin Recktenwald, Willm Hinrichs
  • Patent number: 10324832
    Abstract: Embodiments include a multi-stream storage device, a system including a multi-stream storage device, and a method, comprising: receiving an access to a logical address associated with a multi-stream storage device; converting the logical address into a stream identifier; and accessing the multi-stream storage device using the logical address and the stream identifier.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jingpei Yang, Changho Choi, Rajinikanth Pandurangan
  • Patent number: 10327235
    Abstract: Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 18, 2019
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Feng Liu
  • Patent number: 10324802
    Abstract: In one embodiment, a computer-implemented method of a dedupe storage network includes the step of providing one or more replication-site dedupe storage nodes. Another step includes providing an onsite-dedupe storage node, wherein the onsite dedupe node initiates a replication operation, wherein the replication operation comprises the onsite dedupe storage node operation pushing or fetching a dedupe-image data from the one or more replication-site dedupe storage nodes. The replication from local dedupe storage node to remote dedupe storage node pushes data not present at remote. The replication from remote dedupe storage node to local dedupe storage node fetches data not present at local.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: June 18, 2019
    Inventors: Ashish Govind Khurange, Kuldeep Sureshrao Nagarkar, Sachin Baban Durge, Ravender Goyal
  • Patent number: 10324799
    Abstract: A method, computer system, and a computer program product for enhanced application write operations is provided. The present invention may include performing a write operation by an application node. The present invention may then include committing the write operation to a local buffer cache. The present invention may then include sending the application node an indication that the write operation was successful. The present invention may then include flushing the local buffer cache to a disk, and the present invention may lastly include sending a Remote Procedure Call (RPC) to a gateway node.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shankar Balasubramanian, Venkateswara R. Puvvada, Frank B. Schmuck
  • Patent number: 10324838
    Abstract: Systems, methods, and computer program products to manage an address translation in a virtually segmented memory system, with included processes comprising a process scoped segment table (STAB) consisting of segment table entries (STEs) that contain effective address segment number (ESID) to system wide unique virtual segment identifier (VSID) mappings, and creating a global kernel segment table (STAB) that itself is translated using a pinned page table entry (PTE). A switch to the global kernel STAB is initiated in response to a page fault interrupt on a process STAB PTE and a PTE reload handler invoked to reload that process STAB PTE. A switch to an original STAB is initiated in order to resume the address translation and resolve the page fault or the interrupt by an operating system executing on the processor.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Arnold Flores, Bruce G. Mealey, Mark D. Rogers
  • Patent number: 10318162
    Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 11, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Raviprasad Venkatesha Murthy Mummidi, Matthew Shawn Wilson, Anthony Nicholas Liguori, Nafea Bshara, Saar Gross, Jaspal Kohli
  • Patent number: 10317982
    Abstract: The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated with a number of commands, wherein a number of logical unit (LUN) controllers execute the number of sequences by locating power consumption information and a starting address of the number of sequences stored in a data structure on the number of LUN controllers.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Laszlo Borbely-Bartis
  • Patent number: 10320522
    Abstract: A method for encoding and decoding information data using a polar code is provided. The method for encoding includes segmenting information data into a plurality of first packets, generating a plurality of second packets corresponding to the plurality of first packets by adding a corresponding packet Cyclic Redundancy Check (CRC) code to each of the plurality of first packets, fragmenting each of the plurality of second packets into a plurality of data blocks, polar code encoding each of the plurality of data blocks included in a corresponding second packet of the plurality of second packets, and generating a plurality of third packets corresponding to the plurality of second packets by concatenating each polar code encoded data block included in the corresponding second packet. The method for decoding includes decoding the third packet to obtain the information data based on the method for encoding.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 11, 2019
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Research & Business Foundation
    Inventors: Hongsil Jeong, Sang-Hyo Kim, Jong-Hwan Kim, Daehyeon Ryu, Seho Myung
  • Patent number: 10318153
    Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g., computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 11, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Mitesh Ramesh Meswani, Gabriel H. Loh, Mauricio Breternitz, Jr., Mark Richard Nutter, John Robert Slice, David Andrew Roberts, Michael Ignatowski, Mark Henry Oskin
  • Patent number: 10318359
    Abstract: Various embodiments are generally directed to techniques to remotely access object events. An apparatus may comprise a processor and a memory communicatively coupled to the processor. The memory may be operative to store a remote event bridge having a surrogate object that when executed by the processor is operative to allow an observer object for a first process to subscribe to an event of a subject object for a second process using the surrogate object. In this manner, the remote event bridge and the surrogate object operates as an interface between subject objects and observer objects without any modifications to either class of objects.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 11, 2019
    Assignee: SAS INSTITUTE INC.
    Inventor: Cummins Aiken Mebane, III
  • Patent number: 10303384
    Abstract: One or more control circuits of a storage system are configured to intelligently set a task readiness indicator for tasks on a task command queue. A memory controller may divide each of the tasks into one or more chunks. The memory controller initiates processing of at least some of the chunks for at least two tasks and determines a task readiness factor each of the tasks based on how far respective chunks have progressed in the processing. The memory controller sets a ready indicator in a task status register for a selected task based on the task readiness factor of the tasks. Therefore, task latency may be reduced. In one aspect, the memory controller allocates a ring buffer to chunks of an executing task. This ring buffer may assure that there will always be memory for the chunks of the task.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Agarwal
  • Patent number: 10296314
    Abstract: Exemplary methods, apparatuses, and systems parse programming code to identify instructions within the programming code to allocate objects and instructions within the programming code to create, delete, and/or update references to the objects. Based upon the identified instructions, a model of memory used when the programming code is executed is generated. The model includes representations of the objects and representations of changes to the references to the objects. Based upon the representations in the model, it is determined that each of a plurality of the objects is connected to another of the plurality of objects by one of the references but unreachable by any variable at a point of execution of the programming code. In response to the determination that the plurality of objects is unreachable, a report is generated to flag the unreachable plurality of objects as a potential memory leak for correction.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 21, 2019
    Assignee: Facebook, Inc.
    Inventors: Dino Salvo Distefano, Cristiano Calcagno, Dulma Churchill
  • Patent number: 10296216
    Abstract: Executing connections from a data processing system to a storage controller using ports specified in a TPG report. The storage controller receives a RTPG SCSI request from the data processing system via a FC fabric. The storage controller determines whether NPIV is enabled on the storage controller and, if so, the storage controller modifies the TPG report to include one or more dedicated N-Ports and one or more multi-purpose N-Ports, where AAS bits of a dedicated N-Port descriptor associated with the dedicated N-Ports are set as Active/optimized. The storage controller sends the modified TPG report to the data processing system. The storage controller then processes an access request received from the data processing system where the access request is received on one of the one or more dedicated N-Ports and the one or more multi-purpose N-Ports according to the TPG report and a device type of the data processing system.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher W. Bulmer, Timothy A. Moran
  • Patent number: 10296263
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device receives a store data object request and facilitates distributed storage of the data object in storage units (SUs). the computing device applies unique deterministic functions to the object name to generate deterministic values. For a deterministic value, the computing device identifies a corresponding SU based on the deterministic value and the bucket mapping scheme. The computing device transmits an update bucket request to the corresponding SU to be used by the corresponding SU to update a state value of a bucket that is locally stored by the corresponding SU to indicate an active state.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Jason K. Resch
  • Patent number: 10296451
    Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage controller is configured to receive a plurality of logical addresses. Each logical address has one of a content-based mapping type and an address-based mapping type. Responsive to a first logical address of the plurality of logical addresses having the content-based mapping type, the storage controller is configured to utilize a content-based mapping generated based on content of a data page associated with the first logical address to identify a corresponding physical address. Responsive to a second logical address of the plurality of logical addresses having the address-based mapping type, the storage controller is configured to utilize an address-based mapping generated based on the second logical address to identify a corresponding physical address.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 21, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Amitai Alkalay, Assaf Natanzon
  • Patent number: 10289570
    Abstract: Embodiments of this disclosure are directed to an execution profiling handler configured for intercepting an invocation of memory allocation library and observing memory allocation for an executable application process. The observed memory allocation can be used to update memory allocation meta-data for tracking purposes. The execution profiling handler can also intercept indirect branch calls to prevent heap allocation from converting to execution and intercept exploitation of heap memory to block execution.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 14, 2019
    Assignee: McAfee, LLC
    Inventors: Xiaoning Li, Lixin Lu, Ravi Sahita
  • Patent number: 10291264
    Abstract: General polar codes are disclosed that encode symbols of a q-ary alphabet, where q?2. Systems and methods are also disclosed for performing code rate matching when using general polar codes. In one embodiment, a method performed at a transmitter includes receiving a plurality of bits at a polar encoder. The plurality of bits represent a plurality of q-ary symbols, where q>2. The method further includes encoding the plurality of bits using the polar encoder to generate a codeword of q-ary symbols represented by bits. The method further includes puncturing the codeword according to a puncturing pattern to obtain a punctured codeword having a reduced bit length.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: May 14, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ran Zhang, Wuxian Shi, Nan Cheng, Yiqun Ge
  • Patent number: 10282134
    Abstract: A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Frank F. Ross
  • Patent number: 10282122
    Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 7, 2019
    Assignee: INTEL CORPORATION
    Inventor: David R. Cheriton
  • Patent number: 10275167
    Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor updates the service address space with storage delta packets received from the main processor, and the service co-processor performs diagnostic services based on command packets received from the main processor.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Harman, Neil W. Leedham, Kim P. Walsh, Andrew Wright
  • Patent number: 10275168
    Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Harman, Neil W. Leedham, Kim P. Walsh, Andrew Wright
  • Patent number: 10270465
    Abstract: Embodiments include method, systems and computer program products for data compression in storage clients. In some embodiments, a storage client for accessing a storage service from a computer program is provided. A compression method is provided in the storage client to reduce a size of data objects. A frequency of compressing data from the computer program or modifying a compression algorithm based on assessing costs and benefits of compressing the data is varied.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventor: Arun K. Iyengar
  • Patent number: 10261690
    Abstract: A method of operating a storage system is disclosed. The method includes determining a storage cluster among storage arrays of the storage system. Each storage array includes at least two controllers and at least one storage shelf. The at least two controllers are configured to function as both a primary controller for a first storage array and a secondary controller for a second storage array.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 16, 2019
    Assignee: Pure Storage, Inc.
    Inventor: Ori Shalev
  • Patent number: 10248590
    Abstract: A computing system for supporting a plurality of different types of memory devices includes a memory voltage regulator. The memory voltage regulator adjusts a supply voltage to a requisite voltage for a detected memory device based on serial presence detect (SPD) data. The computing system further includes a memory controller that supports a plurality of types of memory devices. The memory controller receives data regarding the type of the detected memory device, and controls input/output signals relative to the type of the detected memory device based on the SPD data and the GPIO data of the detected memory device.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: April 2, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jen-Chun Hsu, Roger A. Pearson
  • Patent number: 10248324
    Abstract: A secure parallel processing technique for converting any parallel random access machine (PRAM) into an oblivious parallel random access machine (OPRAM), whose distribution of memory accesses is statistically independent of the data (with negligible error), while only inducing a polylogarithmic slowdown to both the total and parallel complexities of the program.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 2, 2019
    Assignees: Cornell University, Technion Research & Development Limited, Academia Sinica
    Inventors: Rafael Pass, Elette Boyle, Kai-Min Chung
  • Patent number: 10241690
    Abstract: Technical solutions are described for shifting wearout of an array of storage disks in a storage system. In an aspect, a method includes staggering completion of maximum number of writes for each storage disk in the array. The method also includes copying data from a storage disk in the array to a replacement disk and redirecting a request to access the data from the storage disk to the replacement disk. The method also includes, in response to passage of a predetermined duration of time since copying the data from the storage disk to the replacement disk, copying the data from the replacement disk to the storage disk and directing the request to access the data from the storage disk back to the storage disk.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffery M. Franke, James A. O'Connor
  • Patent number: 10241793
    Abstract: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 26, 2019
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Michael G. Perkins, John L. Redford, Kaushal Sanghai
  • Patent number: 10238359
    Abstract: There is provided with an imaging control apparatus. A reception unit receives an imaging order. A control unit permits adding identification information if the received imaging order includes no identification information and to inhibit correction of the identification information upon determining that the identification information is included in the imaging order. An obtaining unit obtains information to be added as the identification information if the identification information is not included in the imaging order. A transmission unit transmits an image captured in accordance with the imaging order and either the obtained identification information or the identification information included in the imaging order, in association with each other, to an external image archiving apparatus.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: March 26, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Daiya Semba
  • Patent number: 10241894
    Abstract: A dynamic shared-memory data race detection tool with data-scoping capabilities to reduce runtime overheads is disclosed. The tool allows users to restrict analysis of memory locations to heap and/or stack variables that are of interest to them using explicit calls to functions provided in a library that is part of the race detection tool. The application code is instrumented to insert probes at all memory instructions and linked with the data race detection library to perform data-scoped race detection.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yuan Zhang, Hazim Shafi, Khaled S. Sedky
  • Patent number: 10235085
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit that includes a processor includes generating storage unit heat data based on a plurality of temperature readings received from each of a plurality of storage units, where the storage unit heat data indicates a first hot storage unit. A pair of storage units is selected from the plurality of storage units based on the storage unit heat data, where the pair of storage units includes the first hot storage unit and a second storage unit. A data swap request is generated for transmission to the pair of storage units, where the data swap request includes an instruction to transfer at least one first data slice from the first hot storage unit to the second storage unit and to transfer at least one second data slice from the second storage unit to the first hot storage unit.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Teague S. Algie, Andrew G. Peake
  • Patent number: 10236043
    Abstract: Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 19, 2019
    Assignee: Altera Corporation
    Inventor: Pohrong Rita Chu
  • Patent number: 10233028
    Abstract: A conveyor controller for being implemented into a conveyor system includes control circuitry and one or more network interfaces for coupling with other conveyor controllers. In one embodiment, the control circuitry configured for detecting whether a another conveyor controller is connected and to determine which network interface is used in order to set the direction of the conveyor system. In another embodiment, the control circuitry is configured, to receive configuration data from a conveyor controller connected to a network interface, and to detect if another conveyor controller is and to transmit configuration message to another conveyor controller that includes additional configuration data associated with the conveyor controller. In still another embodiment, the control circuitry transmits configuration data to a replacement conveyor controller upon getting a request from the replacement conveyor controller that has been connected to a network interface.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 19, 2019
    Assignee: Insight Automation Inc.
    Inventors: Charles R. Combs, James P. Knapke, Dimitar Ivanov Petrov, Timothy A. Barnes, David W. Sellers
  • Patent number: 10229063
    Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Katsushige Matsubara, Keisuke Matsumoto, Seiji Mochizuki
  • Patent number: 10223218
    Abstract: A mechanism is provided for disaster recovery of managed systems. Responsive to an identification of a virtual machine recovery condition occurring at a first node site, one or more virtual machines to be recovered to a second site node are identified. Further responsive to the identification of the virtual machine recovery condition occurring at the first node site and responsive to the identification of the one or more virtual machines to be recovered, at least some of records/metadata state data associated with the one or more virtual machines are transmitted to the second site node.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Josep Cors, Richard E. Harper, Naresh Nayar, Gerhard A. Widmayer
  • Patent number: 10223222
    Abstract: Methods, systems, and computer program products for storage system-based replication for disaster recovery in virtualized environments are provided herein.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Harigovind Ramasamy, Soumitra Sarkar, Mahesh Viswanathan, Long Wang
  • Patent number: 10216423
    Abstract: A processing device of a storage server that manages a plurality of SSDs receives a request to write data. The processing device determines one or more attributes associated with the request, generates a stream tag for the request based on the one or more attributes, and sends a first write command to a first SSD of the plurality of SSDs. The first write command comprises at least a portion of the data and the stream tag that causes the first SSD to write the portion of the data to a first stream block of the first SSD.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 26, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Kiron Balkrishna Malwankar, Karagada Ramarao Kishore, Sundar Kanthadai
  • Patent number: 10216446
    Abstract: A solution to deduplication in a storage system is disclosed herein. In this solution, a controller stores, at a first storage address, a data block that is written for the first time, and inserts, in a fingerprint table, a first fingerprint of first data that is written for the first time, but does not establish a mapping relationship between the first fingerprint and the first storage address. When receiving subsequently written second data to be written, the controller allocates a second storage address to the duplicate second data, stores the second data at the second storage address, and establishes a mapping relationship between the first fingerprint and the second storage address in the fingerprint table. This reduces an amount of data in the fingerprint table.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 26, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wenhai Lan, Wei Zhang, Xiaoan Yu, Xuyou Liu, Zhixiong Zhang
  • Patent number: 10210081
    Abstract: Methods and systems for performing garbage collection involving sensitive information on a mobile device are described herein. Secure information is received at a mobile device over a wireless network. The sensitive information is extracted from the secure information. A software program operating on the mobile device uses an object to access the sensitive information. Secure garbage collection is performed upon the object after the object becomes unreachable.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: February 19, 2019
    Assignee: Citrix Systems International GmbH
    Inventors: Herbert Anthony Little, Neil Patrick Adams, Stefan E. Janhunen, John Fredric Arthur Dahms
  • Patent number: 10203880
    Abstract: A technique writes data to a storage array. The technique involves operating storage circuitry in a “FILL HOLE” mode in which the circuitry writes a stream of first data portions within storage portions of used storage stripes of the array. The technique further involves, after operating the circuitry in the “FILL HOLE” mode and in response to a first event, transitioning the circuitry from the “FILL HOLE” mode to a “STRIPE WRITE” mode in which the circuitry writes a stream of second data portions within unused storage stripes of the array. The technique further involves, after operating the circuitry in the “STRIPE WRITE” mode and in response to a second event, transitioning the circuitry from the “STRIPE WRITE” mode back to the “FILL HOLE” mode in which the circuitry writes a stream of third data portions within storage portions of used storage stripes of the array.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Bruce E. Caram, Christopher A. Seibel, Christopher Jones
  • Patent number: 10204108
    Abstract: The method for manufacturing a file system update package includes: file information of each source file in a file system to be updated is acquired; an operation type of a target file corresponding to each source file is determined according to the file information of each source file, the operation type including one of a dynamic type, a static type and a recently-added type; when the operation type of the target file is the dynamic type or the recently-added type, the target file is compressed to form a compressed file package, and when the operation type of a certain target file is the static type, a differential operation is executed according to a difference between the target file and the corresponding source file to form a differential file package; and all the compressed file packages and all the differential file packages are packaged to form a file system update package.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: February 12, 2019
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Xi Chen, Jianping Shuang, Chong Zhang
  • Patent number: 10198190
    Abstract: A system and method for data storage management is disclosed. The method includes determining, by an access tracking component, a quantity of access requests for at least one data block, and determining a quantity of current copies of the data block. The method also includes creating, by a duplication component, at least one additional copy of the data block when the quantity of the access requests exceeds an access request threshold. Additionally, a deduplication component removes at least one current copy of the data block when the quantity of the access requests falls below the access request threshold. The access request threshold can be a threshold number of access requests for the data block, the presence of an input/output bottleneck, or a given length of a read latency when accessing the data block. Further, data coloring techniques can be used to distribute current copies of the data block.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Dain, Itzhack Goldberg, Gregory T. Kishi, Daniel I. Tan