Control Technique Patents (Class 711/154)
  • Patent number: 11687278
    Abstract: A data storage system can connect a data storage controller to a host and a data storage device. A first reference state corresponding to a first zone of the data storage device can be incremented in response to a first version of data being assigned to the first zone by the data storage controller. A second version of the data may be written to a second zone of the data storage device prior to populating a recently freed list with the first zone having an incorrect reference state. The first zone can be allocated by the data storage controller for new data without altering the incorrect reference state that is subsequently written to the first zone as directed by the data storage controller.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 27, 2023
    Assignee: Seagate Technology LLC
    Inventors: Douglas Dewey, Ian Davies, Ryan Phillips
  • Patent number: 11681462
    Abstract: A memory system may include a storage medium including a buffer region and a main region; and a controller configured to, when performing a flush operation, move normal data from the buffer region to the main region and maintain pinned data in the buffer region, wherein the pinned data is data which is determined by a host device to be maintained in the buffer region irrespective of the flush operation.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventor: Kyu Ho Choi
  • Patent number: 11681527
    Abstract: An electronic device includes a memory, a processor, and functional hardware. The memory includes a queue. The processor is configured to write a processing instruction into a target area of the queue. The functional hardware is configured to read the processing instruction from the target area and reserve the target area. The functional hardware generates a completion message according to the processing instruction, and writes the completion message into the target area after the processing instruction is executed. The completion message corresponds to the processing instruction.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: June 20, 2023
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Shuai Lin, Zhaoyao Hu
  • Patent number: 11681633
    Abstract: A memory system may include a memory device suitable for storing data and a controller suitable for generating and managing map data comprising a logical address of an external device and a physical address of the memory device corresponding to the logical address. The controller uploads at least some of the map data to the external device and uploading a latest version of the uploaded map data to the external device again based on dirty information or access information. The dirty information indicates whether a physical address corresponding to a logical address included in the uploaded map data has been changed. The access information indicates whether an access request for the logical address included in the uploaded map data from the external device has been made.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11669266
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system writes, when performing the sudden power-off recovery operation, a plurality of target segments which are segments most recently written to each of the plurality of open memory blocks among the plurality of memory blocks to a target memory block among the plurality of memory blocks.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 6, 2023
    Assignee: SK hynix Inc.
    Inventors: Sung Jin Park, Beom Rae Jeong
  • Patent number: 11669260
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Patent number: 11669270
    Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: June 6, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Wan-Jun Hong, Qi-Ao Zhu, Xin Wang, Yang Zhang, Xu Hui Cheng, Jian Hu
  • Patent number: 11669366
    Abstract: Methods, systems, and apparatuses for graph streaming processing system are disclosed. One system includes a plurality of graph streaming processors operative to process a plurality of threads, wherein the plurality of threads is organized as nodes. The system further includes a scheduler that includes a plurality of stages. Each stage includes a command parser operative to interpret commands within a corresponding input command buffer, an alternate command buffer, and a thread generator coupled to the command parser. The thread generator is operative to generate the plurality of threads, and dispatch the plurality of threads, where the processing of the plurality of thread for each stage includes storing write commands in the corresponding output command buffer or in the alternate command buffer.
    Type: Grant
    Filed: July 16, 2022
    Date of Patent: June 6, 2023
    Assignee: Blaize, Inc.
    Inventors: Lokesh Agarwal, Sarvendra Govindammagari, Venkata Ganapathi Puppala, Satyaki Koneru
  • Patent number: 11662941
    Abstract: Methods and systems for increasing reliability of a data storage device are disclosed. During fabrication runs of a non-volatile memory (NVM) die, such as a NAND, there may be a number of memory cells designated as erase cells. When one or more erase cells are physically adjacent to programmed memory cell, electrical effects of the erase cell may cause a bit to flip in the adjacent good memory cell. To mitigate this effect, an LDPC engine is used to generate additional parity bits for the erased bit/cells. When a host requests data from the NVM, the parity bits may be used to correct additional errors because of the erased state to programmed state bit flips.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 30, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bhavadip Bipinbhai Solanki, Dharmaraju Marenahally Krishna
  • Patent number: 11656790
    Abstract: Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: May 23, 2023
    Assignee: SK HYNIX INC.
    Inventors: Seung Gu Ji, Hyung Min Lee
  • Patent number: 11657875
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: May 23, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Patent number: 11656777
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may repeatedly execute, when entering a low power mode, iterations of a target operation according to a temperature of the memory system until a stop condition is satisfied. In this case, the target operation may be a garbage collection operation for the plurality of memory blocks or a migration operation of moving data stored in a first area including at least one of the plurality of memory blocks to a second area including at least one of the plurality of memory blocks. The operation speed of the memory block included in the first area may be higher than the operation speed of the memory block included in the second area.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventors: Young Mi Yoon, Hyoung Suk Jang
  • Patent number: 11656793
    Abstract: A memory system includes a memory device including memory blocks, and a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host, store first data to which a first logical address is allocated in a cache group, generate a first entry for the first data stored in the cache group, and in response to second data to which the first logical address is allocated being stored in the cache group after the first data is stored in the cache group, generate a second entry for the second data.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventors: Soo Jin Park, Ji Yeun Kang, Won Hyoung Lee
  • Patent number: 11650759
    Abstract: Various implementations described herein relate to systems and methods for managing metadata using an in-memory journal, including determining metadata for data, storing the metadata in an in-memory journal, detecting an imminent interruption to operations of the storage device, in response to detecting the imminent interruption, program the in-memory journal to a non-volatile memory device of the storage device, detect that the operations of the storage device are being restored, and in response to detecting that the operations of the storage device are being restored, performing metadata update. The first data is read from first original areas of a non-volatile memory. The first metadata includes a first physical address for each of first new areas of the non-volatile memory. The metadata is programmed in a metadata area of the non-volatile memory device.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: May 16, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Andrew John Tomlin
  • Patent number: 11644991
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages memory area sets. The controller distributes a first memory area set into a first group. The controller distributes a second memory area set into a second group. The controller comprises first to fourth circuits. The first circuit processes a first read request from a host to the first memory area set. The second circuit processes a first write request from the host to the first memory area set. The third circuit processes a second read request from the host to the second memory area set. The fourth circuit processes a second write request from the host to the second memory area set.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 9, 2023
    Assignee: Kioxia Corporation
    Inventors: Makiko Numata, Mitsunori Tadokoro
  • Patent number: 11645255
    Abstract: The present disclosure provides a method for storing data, including: storing data in a first node, the first node being selected from a first node set including a first edge node and child nodes thereof; selecting, from a second node set including a second edge node and child nodes thereof, a second node for storing the data, the first edge node being a child node of the second edge node; and storing the data in the second node. The present disclosure further provides a method for searching for data. The present disclosure can reduce the time for searching for data in a distributed storage system.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: May 9, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Zhenzhen Lin, Si Chen, Qiang Chen, Bin He
  • Patent number: 11637565
    Abstract: One example method includes file specific compression selection. Compression metrics are generated for a chunk of a file using a reference compressor. Compression metrics for other compressors are determined from the metrics of the reference compressor. A compressor is then selected to compress the file.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 25, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: RĂ´mulo Teixeira De Abreu Pinho, Vinicius Michel Gottin, Joel Christner
  • Patent number: 11627087
    Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 11, 2023
    Assignee: MARVELL ASIA PTE, LTD
    Inventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 11620057
    Abstract: A storage device includes: a nonvolatile memory including power loss protector (PLP) memory blocks configured to store at least one of meta data or user data for data backup; a buffer memory configured to store at least one of the meta data or the user data stored in the PLP memory blocks; a charging circuit configured to generate electric power for data backup in response to a sudden power off (SPO) occurrence, and transmit a first charging complete signal or a second charging complete signal to a processor according to a level of the electric power, and; and the processor configured to control at least one of the nonvolatile memory and the buffer memory to execute a first request from a host related to the meta data with priority in response to the first charging complete signal, and execute a second request from the host related to the meta data or the user data in response to the second charging complete signal.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwoo Lim, Seongnam Kwon, Haeri Lee, Donghwan Jeong, Unseon Cho, Moonsung Choi
  • Patent number: 11620062
    Abstract: In at least one embodiment, processing can include receiving a metadata (MD) structure including MD pages; and performing a MD split operation with respect to a first of the MD pages, wherein said performing the MD split operation includes: generating a first ALI (abstract logical index) representing a new MD page that is unallocated and is a child of the first MD page; and storing an entry in a bucket of an in-memory MD log for the first ALI, wherein the entry denotes a mapping between the first ALI and a corresponding LI (logical index), wherein the entry indicates that the corresponding LI associated with the first ALI is invalid since the first ALI represents a new MD page which is unallocated and not associated with physical storage; and destaging the in-memory MD log, wherein said destaging includes allocating first physical storage for the new MD page.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: April 4, 2023
    Assignee: Dell Products L.P.
    Inventors: Vladimir Shveidel, Ronen Gazit, Bar David
  • Patent number: 11615019
    Abstract: A non-volatile storage device according to an embodiment of the present technology includes a storage section and a calculation section. The storage section includes a plurality of block sections each including a plurality of page sections into which data can be written independent of each other, the plurality of block sections being capable of collectively deleting the data written in the plurality of page sections. The calculation section calculates, on the basis of information about write conditions of the plurality of page sections included in the storage section, candidate addresses that are candidates of logical addresses of the data to be written into the plurality of page sections.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 28, 2023
    Assignee: SONY CORPORATION
    Inventor: Kazuyuki Date
  • Patent number: 11614886
    Abstract: A memory system may write, when operating in a force unit access mode, first write data requested by the host to a buffer for temporarily storing data to be written the memory device and a first memory block among the plurality of memory blocks, and may write, when the size of the data accumulatively stored in the buffer is greater than or equal to A which is a unit of a size in which data is written to a second memory block among the plurality of memory blocks, second write data of size A among the data stored in the buffer to the second memory block. The operation speed of the first memory block may be set faster than the operation speed of the second memory block and the storage capacity of the first memory block may be set smaller than the storage capacity of the second memory block.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: March 28, 2023
    Assignee: SK hynix Inc.
    Inventor: Jae Il Lee
  • Patent number: 11614891
    Abstract: Devices and techniques for communicating a programmable atomic operator to a memory controller are described herein. A memory controller can receive a memory request and extract a command indicator that indicates a programmable atomic operator (PAO) command from the memory request. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Tony Brewer
  • Patent number: 11609705
    Abstract: Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: March 21, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhe Zhao, Longjie Sun, Lung Yang, Yung-Shiuan Chen, Lanping Xu
  • Patent number: 11604635
    Abstract: Embodiments of the present application provide an online program updating method, including: receiving an external command, acquiring an updated program file, and storing the updated program file into the backup area through a program in the application area, where the external command includes the updated program file, and running the updated program file when a program counter jumps to the backup area. This solution, after the program counter jumps to the backup area, runs the updated program file, thereby providing power continuously while updating the online program and improving the reliability of the power supply system.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: March 14, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hui Huang, Kai Dong, Ke Chen
  • Patent number: 11605016
    Abstract: A quantum computing service includes connections to one or more quantum hardware providers that are configured to execute quantum circuits using quantum computers based on one or more quantum technologies. The quantum computing service also includes at least one edge computing device located adjacent to a quantum computer at one of the quantum hardware provider facilities. The edge computing device is configured to execute classical computing portions of a hybrid algorithm in coordination with the quantum computer, which executes quantum computing portions of the hybrid algorithm. Results of the execution of the hybrid algorithm are automatically stored to a data storage service accessible to the customer.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 14, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey Paul Heckey, Cody Aoan Wang, John Totah, Christopher Kasprowicz, William Vass
  • Patent number: 11604601
    Abstract: A memory sub-system to, in response to a power up, initiate a first loading process associated with a set of trim values, wherein the first loading process includes loading a sequence of the set of trim values to one or more registers of the memory sub-system. An operation associated with a memory unit of the memory sub-system is identified. A portion of the set of trim values corresponding to the operation associated with the memory unit is identified. The memory sub-system executes a second loading process comprising loading the portion of the set of trim values corresponding to the operation associated with the memory unit. The operation is executed using the portion of the set of trim values loaded into the one or more registers associated with the memory unit.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Steven Michael Kientz, Vamsi Pavan Rayaprolu
  • Patent number: 11599474
    Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11593198
    Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: February 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shemmer Choresh, Tomer Tzvi Eliash
  • Patent number: 11592982
    Abstract: An electronic device comprising a nonvolatile memory, a memory controller configured to control the nonvolatile memory, and a host connected to the memory controller. In response to a first write signal received from the host, the memory controller is configured to provide the first write signal to the nonvolatile memory, the nonvolatile memory is configured to perform a write operation based on the provided first write signal, generate first metadata based on a result of performing the write operation, and provide the generated first metadata to the host. The host is configured to determine whether to perform garbage collection for the nonvolatile memory using a neural network model trained based on the provided first metadata or the first write signal, provide a garbage collection request signal to the memory controller in response to determining to perform garbage collection.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hoon Kim, Seong Hun Kim, Hong Kug Kim, Won Jung
  • Patent number: 11593025
    Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 28, 2023
    Assignee: Arm Limited
    Inventors: Gurunath Ramagiri, Jamshed Jalal, Mark David Werkheiser, Tushar P Ringe, Klas Magnus Bruce, Ritukar Khanna
  • Patent number: 11579808
    Abstract: In some examples, fabric driven NVMe subsystem zoning may include receiving, from a non-volatile memory express (NVMe) Name Server (NNS), a zoning specification that includes an indication of a host that is to communicate with a given NVMe subsystem of an NVMe storage domain. Based on the zoning specification, the host may be designated as being permitted to connect to the given NVMe subsystem of the NVMe storage domain. An NVMe connect command may be received from the host. Based on the designation and an analysis of the NVMe connect command, a connection may be established between the given NVMe subsystem of the NVMe storage domain and the host.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 14, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Asutosh Satapathy, Komateswar Dhanadevan, Krishna Babu Puttagunta, Vivek Agarwal, Rupin T. Mohan, Govind Chandru Rathod
  • Patent number: 11580028
    Abstract: The present technology relates to an electronic device. A memory device having improved memory block management performance according to the present technology includes a memory block, a peripheral circuit, and a control logic. The peripheral circuit performs a read operation and a program operation on a selected physical page among a plurality of physical pages. The control logic controls the peripheral circuit to read first logical page data stored in a first physical page and second logical page data stored in a second physical page among the plurality of physical pages, and additionally program the second logical page data into the first physical page using the read first and second logical page data.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 14, 2023
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 11582299
    Abstract: A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 14, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Ilir Iljazi, Jason K. Resch, Ethan S. Wozniak
  • Patent number: 11574662
    Abstract: A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 7, 2023
    Inventors: Sucheol Lee, Younghoon Son, Hyunyoon Cho, Youngdon Choi, Junghwan Choi
  • Patent number: 11573721
    Abstract: An approach is provided for providing optimized identification of duplicate data in a networked computing environment. An aggregate feature vector is created that is specific to an attribute of the data (e.g., a field that holds specific informational content). The aggregate feature vector has a set of dimensions that each define a specific comparison function used to test for similarity between data entries in the attribute. Each dimension in the aggregate feature vector is assigned an effectiveness, and a cost is computed for each dimension. Based on these two, a subset of dimensions is selected to form an optimized feature vector. This optimized feature vector can then be used to analyze a dataset to find matching data.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: February 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Soma Shekar Naganna, Abhishek Seth, Neeraj Ramkrishna Singh
  • Patent number: 11567555
    Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Jason Seung-Min Kim, Sundar Ramani, Yogesh Bansal, Nitin N. Garegrat, Olivia K. Wu, Mayank Kaushik, Mrinal Iyer, Tom Schebye, Andrew Yang
  • Patent number: 11561728
    Abstract: Methods, computer program products, computer systems, and the like for efficient metadata management are disclosed, which can include receiving a subunit of storage, storing a first metadata portion of the subunit of storage in a first unit of storage, and storing a second metadata portion of the subunit of storage in a second unit of storage.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 24, 2023
    Assignee: Veritas Technologies LLC
    Inventors: Jialun Liu, Xianbo Zhang, Weibao Wu
  • Patent number: 11550483
    Abstract: Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Olivier Duval, Lance Dover
  • Patent number: 11550724
    Abstract: The present disclosure provides a method of logical to physical mapping for a data-storage device comprising a non-volatile memory device. The method comprises maintaining a first type of information representing at least a part of a logical-to-physical address translation map. Further, the method comprises maintaining a second type of information pertaining to the logical-to-physical translation map as a part of a physical page. Further, the method comprises completing a logical-to-physical mapping based on the first and second type of information to thereby determine a physical location, within one or more of the physical pages, of the data stored in each logical page.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Saugata Das Purkayastha
  • Patent number: 11550674
    Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 10, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Sriramakrishnan Govindarajan, Mihir Narendra Mody, Prithvi Shankar Yeyyadi Anantha
  • Patent number: 11537293
    Abstract: A data storage device includes a memory device that includes a plurality of zones of a zoned namespace and a controller coupled to the memory device. During operation, the controller maintains a window-based read and write monitor data structure to determine the read density and write density of each of the zones. The read density and write density are utilized to determine a cost for allocating wear leveling data for each zone. Based on the cost and the available storage capacity of the storage class memory, data, in a data management operation, is moved to either the storage class memory or the zone with the low cost. The host device is informed of the storage class memory usage for future data management operations.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Xinde Hu, Dejan Vucinic
  • Patent number: 11537303
    Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Rakesh Balakrishnan, Eldhose Peter, Judah Gamliel Hahn
  • Patent number: 11514163
    Abstract: A terminal device includes an abstraction unit for generating abstracted operation information acquired by abstracting operation information indicating a result of operation of an own device, based on an abstraction rule; a computation unit for computing, based on the abstracted operation information, a forecast score indicating a level of forecast possibility relating to the operation information; and a determination unit for determining, based on the forecast score, whether to transmit the operation information to a detection device for detecting that the own device operates in an illicit manner, and thus retains that the detection device securely captures an illicit operation by the terminal device, and efficiently reduces the operation information being transmitted from the terminal device to the detection device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 29, 2022
    Assignee: NEC CORPORATION
    Inventor: Satoshi Ikeda
  • Patent number: 11516287
    Abstract: A method for performing Simple Storage Service (S3) seamless migration using index objects and associated apparatus are provided. The method includes: in response to a request of migrating user data of a user of the storage server from a remote S3-compatible server into the storage server, during an index stage, utilizing an index-object-based S3 migration management module among multiple program modules running on a host device within the storage server to create and store multiple index objects into a storage device layer of the storage server to be respective representatives of multiple normal objects of the user data at the storage server, and migrate respective Access Control Lists (ACLs) of the multiple normal objects to the storage server to be respective ACLs of the multiple index objects; and during a data stage, utilizing the index-object-based S3 migration management module to trigger one or more migration agents to migrate object data.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: November 29, 2022
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Chi-En Chang, Kuan-Kai Chiu
  • Patent number: 11507316
    Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Akio Sugahara, Yuji Nagai
  • Patent number: 11494114
    Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert B. Eisenhuth
  • Patent number: 11494307
    Abstract: A computing system includes a host and a storage device. The host includes a host memory, and the storage device includes a processor, a semiconductor memory device and a device memory which caches mapping information of the semiconductor memory device. In operation, the processor transmits to the host read data and mapping table entry information of a logical address region corresponding to the read data in response to a read request. The mapping table entry information is transmitted to the host based on features of the logical address region. Additionally, the host may transmit a read buffer request corresponding to the mapping table entry information to the storage device, and the storage device may transmit mapping information corresponding to the read buffer request to the host, which then stores the mapping information in the host memory.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hoon Seok
  • Patent number: 11487576
    Abstract: A memory controller is disclosed. The memory controller is configured to control the execution of a suspend operation by a memory device. The memory controller includes: a processor configured to output an operation control signal when the memory device is performing a program/erase operation; and a suspend operation manager configured to output suspend mode change information based on the operation control signal and suspend information, wherein the processor is further configured to control the memory controller such that the memory controller outputs a suspend mode change command and a suspend command based on the suspend mode change information.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: November 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sng-Hoon Park, In-Soo Kim, Jong-Won Kim, Sang-Kwon Moon
  • Patent number: 11481116
    Abstract: A computing device comprises two or more compute nodes, that each include two or more processor cores. Each compute node comprises an independently coherent domain that is not coherent with other compute nodes. A central IO die is communicatively coupled to each of the two or more compute nodes. A plurality of natively-attached volatile memory units are attached to the central IO die via one or more memory controllers. The central IO die includes one or more home agents for each compute node. The home agents are configured to map memory access requests received from the compute nodes to one or more addresses within the natively attached volatile memory units.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: October 25, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Siamak Tavallaei, Ishwar Agarwal