Control Technique Patents (Class 711/154)
  • Patent number: 11516287
    Abstract: A method for performing Simple Storage Service (S3) seamless migration using index objects and associated apparatus are provided. The method includes: in response to a request of migrating user data of a user of the storage server from a remote S3-compatible server into the storage server, during an index stage, utilizing an index-object-based S3 migration management module among multiple program modules running on a host device within the storage server to create and store multiple index objects into a storage device layer of the storage server to be respective representatives of multiple normal objects of the user data at the storage server, and migrate respective Access Control Lists (ACLs) of the multiple normal objects to the storage server to be respective ACLs of the multiple index objects; and during a data stage, utilizing the index-object-based S3 migration management module to trigger one or more migration agents to migrate object data.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: November 29, 2022
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Chi-En Chang, Kuan-Kai Chiu
  • Patent number: 11514163
    Abstract: A terminal device includes an abstraction unit for generating abstracted operation information acquired by abstracting operation information indicating a result of operation of an own device, based on an abstraction rule; a computation unit for computing, based on the abstracted operation information, a forecast score indicating a level of forecast possibility relating to the operation information; and a determination unit for determining, based on the forecast score, whether to transmit the operation information to a detection device for detecting that the own device operates in an illicit manner, and thus retains that the detection device securely captures an illicit operation by the terminal device, and efficiently reduces the operation information being transmitted from the terminal device to the detection device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 29, 2022
    Assignee: NEC CORPORATION
    Inventor: Satoshi Ikeda
  • Patent number: 11507316
    Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Akio Sugahara, Yuji Nagai
  • Patent number: 11494114
    Abstract: Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert B. Eisenhuth
  • Patent number: 11494307
    Abstract: A computing system includes a host and a storage device. The host includes a host memory, and the storage device includes a processor, a semiconductor memory device and a device memory which caches mapping information of the semiconductor memory device. In operation, the processor transmits to the host read data and mapping table entry information of a logical address region corresponding to the read data in response to a read request. The mapping table entry information is transmitted to the host based on features of the logical address region. Additionally, the host may transmit a read buffer request corresponding to the mapping table entry information to the storage device, and the storage device may transmit mapping information corresponding to the read buffer request to the host, which then stores the mapping information in the host memory.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hoon Seok
  • Patent number: 11487576
    Abstract: A memory controller is disclosed. The memory controller is configured to control the execution of a suspend operation by a memory device. The memory controller includes: a processor configured to output an operation control signal when the memory device is performing a program/erase operation; and a suspend operation manager configured to output suspend mode change information based on the operation control signal and suspend information, wherein the processor is further configured to control the memory controller such that the memory controller outputs a suspend mode change command and a suspend command based on the suspend mode change information.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: November 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sng-Hoon Park, In-Soo Kim, Jong-Won Kim, Sang-Kwon Moon
  • Patent number: 11481116
    Abstract: A computing device comprises two or more compute nodes, that each include two or more processor cores. Each compute node comprises an independently coherent domain that is not coherent with other compute nodes. A central IO die is communicatively coupled to each of the two or more compute nodes. A plurality of natively-attached volatile memory units are attached to the central IO die via one or more memory controllers. The central IO die includes one or more home agents for each compute node. The home agents are configured to map memory access requests received from the compute nodes to one or more addresses within the natively attached volatile memory units.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: October 25, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Siamak Tavallaei, Ishwar Agarwal
  • Patent number: 11468011
    Abstract: A method for managing log files for recording operations on data stored in a database is provided, wherein a set of log files having an allocated first portion of storage is updated, the allocated first portion of storage is monitored, and a second portion of storage is allocated in dependence on a determination that an available portion of storage is below a predetermined size. A method for generating a snapshot is provided, wherein data entries are included in the snapshot in dependence on a determined relative order of log records in a set of log files. A method of replicating a binary large object is provided, wherein the binary large object is sent to a second database in response to identifying a log record comprising data indicating the binary large object.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 11, 2022
    Assignee: SingleStore, Inc.
    Inventors: Adrian Birka, Rodrigo Toste Gomes
  • Patent number: 11461044
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell array, first and second storage units, and control unit. The memory cell array includes erase unit areas. The first storage units correspond respectively to the erase unit areas and store items of first information indicating whether a first usage restriction is to be imposed on the corresponding erase unit areas. The second storage units correspond respectively to the erase unit areas and store items of second information indicating whether a second usage restriction is to be imposed on the corresponding erase unit areas. The control unit executes switching control on whether the first usage restriction is to be imposed or not and whether the second usage restriction is to be imposed or not on the memory cell array based on the first and second information.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventor: Tomoya Hiraishi
  • Patent number: 11461363
    Abstract: Methods, systems, and computer-readable storage media for receiving a first storage request indicating a first type of data and a first size, identifying a first sub-space based on the first type, the first sub-space including a dense group of dense segments and a sparse group of sparse segments, and determining that the dense group of the first sub-space is absent a dense segment to store data of the first storage request based on the first size, and in response: determining whether the sparse group of the first sub-space includes a sparse segment to store the data of the first storage request based on the first size, and storing the data of the first storage request to the sparse group of the first sub-space in response to determining that the sparse group of the first sub-space includes a sparse segment to store the data of the first storage request.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 4, 2022
    Assignee: SAP SE
    Inventors: Seungho Yoo, Ji Hoon Jang, Seyeong Bae, Yong Sik Kwon, Hyeong Seog Kim
  • Patent number: 11461142
    Abstract: Methods, microprocessors, and systems are provided for implementing an artificial neural network. Data buffers in virtual memory are coupled to respective processing layers in the artificial neural network. An ordered visiting sequence of layers of the artificial neural network is obtained. A virtual memory allocation schedule is produced as a function of the ordered visiting sequence of layers of the artificial neural network, the schedule including a set of instructions for memory allocation and deallocation operations applicable to the data buffers. A physical memory configuration dataset is computed as a function of the virtual memory allocation schedule for the artificial neural network, the dataset including sizes and addresses of physical memory locations for the artificial neural network.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: October 4, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Emanuele Plebani, Mirko Falchetto, Danilo Pietro Pau
  • Patent number: 11461049
    Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11461051
    Abstract: The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Jun Sun Hwang, Jung Hwan Lee, Kwan Su Shon
  • Patent number: 11455118
    Abstract: Implementations of the present disclosure provide a memory apparatus that includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. The apparatus also includes a controller configured to determine J layers in the memory block in each of the M planes and in each of the N dies, each of the J layers comprising a pair of adjacent gate conductive layers. The controller is also configured to determine M sets of stripes. Each of the M sets of stripes comprising a plurality of data portions stored in a respective one of the M planes. The controller is further configured to determine M sets of parity data portions. The controller is further configured to control a temporary storage unit to store the M sets of parity data portions.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: September 27, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Weizhen Kong, Jian Cao, Wei Tao, Ling Du, Yuan Tao
  • Patent number: 11456022
    Abstract: The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Srinivas Rajendra, Sayed Mobin, Rehan Ahmed Zakai
  • Patent number: 11449418
    Abstract: A method for operating a controller for controlling a memory device including memory blocks, the method includes: determining candidate blocks based on erase counts of the memory blocks; determining a victim block among the candidate blocks based on data update counts of logical addresses associated with a plurality of pages in each of the candidate blocks; and moving data of the victim block into a destination block.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Won Yang
  • Patent number: 11449247
    Abstract: A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Curtis Wortman, Jeffrey Erik Schulz
  • Patent number: 11435953
    Abstract: A method for predicting logical blocks address (LBA) information, including: receiving, by a Solid State Drive (SSD), a trace sent from a host, wherein the host can acquire the trace in a reusable environment; determining, by the SSD, one or more LBAs received by the SSD according to the trace; obtaining, by the SSD, a distribution of the LBAs by learning the LBAs based on a preset learning algorithm; and predicting, by the SSD, one or more subsequent LBAs based on the distribution of the LBAs. As a result, it can perform heat classification and prediction of the following LBA used in the SSD by means of learning the LBA distribution of the SSD in a certain reusable environment of the host, thus to improve the hit rate of reading and writing and the efficiency of classification of hot and cold data in garbage collection.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 6, 2022
    Assignee: SHENZHEN DAPU MICROELECTRONICS CO., LTD.
    Inventors: Li Jiang, Xiang Chen, Weijun Li
  • Patent number: 11435929
    Abstract: A system update appliance includes a processor and a memory device with a Content Addressable Storage (CAS) space and a location addressable storage space. The location addressable storage space partitioned into an object storage space and a device storage space. The processor stores a device entry in the device storage space. The device entry is associated with a device external to the system update appliance and includes a component entry for a component of the device. The component operates based on an update. The component entry includes a description of the component and a pointer to a record stored in the CAS space. The processor stores the record in the CAS space. The record is associated with a combination of the component and the first update. The record includes the description, a second pointer to an update repository, and a third pointer to the object storage space.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 6, 2022
    Assignee: Dell Products L.P.
    Inventors: Vaideeswaran Ganesan, Hemant Gaikwad, Pravin Janakiram
  • Patent number: 11436045
    Abstract: Methods, systems and apparatuses for graph streaming processing system are disclosed. One system includes a plurality of graph streaming processors operative to process a plurality of threads, wherein the plurality of threads is organized as nodes. The system further includes a scheduler that includes a plurality of stages. Each stage includes a command parser operative to interpret commands within a corresponding input command buffer, an alternate command buffer, and a thread generator coupled to the command parser. The thread generator is operative to generate the plurality of threads, and dispatch the plurality of threads, where the processing of the plurality of thread for each stage includes storing write commands in the corresponding output command buffer or in the alternate command buffer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 6, 2022
    Assignee: Blaize, Inc.
    Inventors: Lokesh Agarwal, Sarvendra Govindammagari, Venkata Ganapathi Puppala, Satyaki Koneru
  • Patent number: 11435905
    Abstract: Techniques for DNA-based storage of electronic data are described herein. In an example embodiment, a plurality of files is stored in deoxyribonucleic acid (DNA)-based storage. The plurality of files is encoded in a set of DNA oligos, where a DNA synthesizer system synthesizes first DNA oligos that encode first type of segments from the plurality of files and second DNA oligos that encode second type of segments from the plurality of files, and where the first DNA oligos are synthesized in excess compared to the second DNA oligos.
    Type: Grant
    Filed: September 15, 2019
    Date of Patent: September 6, 2022
    Inventor: Bahram Ghaffarzadeh Kermani
  • Patent number: 11436064
    Abstract: A processing method includes: performing an I/O preparation process and an I/O request for a data block in an application program thread; activating, by the application program thread, a journaling thread; waiting for completion of an I/O for the data block and a commit of the journaling thread; preparing an I/O for the journal block and requesting the I/O for the journal block during the waiting for the completion of the I/O for the data block and the commit of the journaling thread, in the journaling thread; preparing an I/O for a journal commit block, before waiting for completion of the I/O for the journal block after the requesting of the I/O for the journal block; after waiting for the completion of the I/O for the journal block, requesting the I/O for the journal commit block; and waiting for completion of the I/O for the journal commit block.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 6, 2022
    Assignees: Research & Business Foundation Sungkyunkwan University, HIGH PERFORMANCE COMPUTING RESEARCH CENTER
    Inventors: Jinkyu Jeong, Gyusun Lee
  • Patent number: 11423989
    Abstract: A processing device establishes a first data group of memory cells of a memory sub-system and a second data group of memory cells of the memory sub-system. A first portion of the first data group is programmed at a threshold voltage level to set a first embedded data value. A second portion of the second data group of memory cells is programmed at the threshold voltage level offset by an offset voltage level to set a second embedded data value.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
  • Patent number: 11422887
    Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 11420117
    Abstract: A method provides for requesting data in a cloud gaming system that includes a cloud storage system and a cloud compute system, each of which has a respective peripheral component interconnect express (PCIe) interface and a respective computer memory. The cloud gaming system includes a PCIe switch connected to both the PCIe interface of the cloud storage system and the PCIe interface of the cloud compute system. The PCIe switch exposes a doorbell register that is monitored by the cloud storage system. The cloud compute system writes to the doorbell register, which causes an interrupt to fire on the cloud storage system. The cloud storage system handles the interrupt, which directs the cloud storage system to read a message from a specified computer memory location. The message directs the cloud storage system to read requested data from a storage device accessible by the cloud storage system.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 23, 2022
    Assignee: Sony Interactive Entertainment LLC
    Inventor: Roelof Roderick Colenbrander
  • Patent number: 11422751
    Abstract: Creating a virtual storage system, including: instantiating one or more virtual storage controllers; instantiating one or more virtual storage devices each including multiple storage tiers; and constructing a virtual storage system in which the one or more virtual storage devices are coupled to each of the one or more virtual storage controllers.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 23, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Ronald Karr, Par Botes
  • Patent number: 11416403
    Abstract: A method for performing pipeline-based accessing management in a storage server and associated apparatus are provided. The method includes: in response to a request of writing user data into the storage server, utilizing a host device within the storage server to write the user data into a storage device layer of the storage server and start processing an object write command corresponding to the request of writing the user data with a pipeline architecture of the storage server; utilizing the host device to input metadata corresponding to the user data into at least one pipeline within the pipeline architecture; and utilizing the host device to cache the metadata with a first cache module of the pipeline, for controlling the storage server completing the request without generating write amplification of the metadata, wherein the first cache module is a hardware pipeline module outside the storage device layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 16, 2022
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Guo-Fu Tseng, Cheng-Yue Chang, Kuan-Kai Chiu
  • Patent number: 11416601
    Abstract: A method for backing up data includes: receiving, by a driver in a host controller of a data storage device, an indication of a threatening event identifying one or more data files in the data storage device; delaying, by the driver, the threatening event; and backing up, by the driver, the one or more data files in the data storage device, prior to allowing the threatening event.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: August 16, 2022
    Assignee: CIGENT TECHNOLOGY, INC.
    Inventor: Tony Edward Fessel
  • Patent number: 11409648
    Abstract: An electronic apparatus is provided. The electronic apparatus according to an embodiment includes a memory configured to store computer executable instructions, and a processor configured to, by executing the computer executable instructions, based on a request for executing a program being received and an available capacity of a first area of the memory to be allocated to the program being insufficient, swap-out page data stored in the first area to a second area of the memory, wherein the processor is further configured to swap out the page data partially or entirely based on an attribute of the page data.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 9, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Youngho Choi, Young Ik Eom, Jaeook Kwon
  • Patent number: 11410638
    Abstract: Methods and systems for causing a voice-activated electronic device to identify that a step of a series of steps can begin while a previous step is ongoing. In some embodiments, a first step will have a waiting period. The methods and systems, in some embodiments, identify this waiting period and determine that a second step can begin during the waiting period of step one. In some embodiments, nested sets of sequential steps are identified within the series of steps. The nested sets of sequential steps, in some embodiments, can be called upon.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 9, 2022
    Assignee: Amazon Technologies, Inc.
    Inventor: Eshan Bhatnagar
  • Patent number: 11409678
    Abstract: A computer system includes a BMC and a host of the BMC. The BMC redirect, through a BMC communication channel, a local media including a disk management tool to a host of the BMC as a particular drive. The host is a storage device connected to one or more storage drives. The disk management tool is configured to prepare a storage area of the one or more storage drives for installation of storage service on the host. The storage service managing a RDMA controller at the host. The BMC configures the host to boot from the particular drive. The BMC sends a first instruction to the host instructing the BMC to reboot. The BMC receives from the host a command for reading the disk management tool. The BMC sends the disk management tool to the host.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 9, 2022
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Anurag Bhatia, Sanjoy Maity
  • Patent number: 11409767
    Abstract: A method for execution by a rebuilding module includes detecting that less than a pillar width number of encoded data slices of a common revision are retrievable from a set of storage units. A decode threshold number of encoded data slices are retrieved and decoded to reproduce a data segment. The data segment is encoded to produce at least one encoded data slice and storage of the at least one encoded data slice in the set of storage units is facilitated in accordance with the common revision when determining to rebuild the at least one encoded data slice. The data segment is encoded to reproduce the set of encoded data slices and storage of the reproduced set of encoded data slices is facilitated in the set of storage units in accordance with a new revision when determining to not rebuild the at least one encoded data slice.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 9, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Asimuddin Kazi, Jason K. Resch
  • Patent number: 11409676
    Abstract: Provided is a SoC, a memory device, an electronic device and a method for storing data in an electronic device. The electronic device comprises a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Hyun Choi, Hyun-Joong Kim, Joon Sik Sohn, Woong-Jae Song, Soo-Woong Ahn, Seung-Hyun Cho
  • Patent number: 11403033
    Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
  • Patent number: 11402999
    Abstract: A storage device for adaptive wear leveling within a data storage system is provided. The storage device includes a host interface configured to receive storage operations for storage and retrieval of data on storage media, a media interface configured to read and write data to the storage media, and a storage controller configured to provide wear leveling for the storage media using a plurality of partitions within the storage media.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: August 2, 2022
    Assignee: Burlywood, Inc.
    Inventors: Nathan Koch, John William Slattery, Amy Lee Wohlschlegel, Kevin Darveau Landin, Christopher Bergman
  • Patent number: 11397540
    Abstract: An apparatus comprises at least one processing device that is configured to send write requests to a first storage system. The first storage system is configured to participate in a replication process in which data associated with the write requests is replicated from the first storage system to a second storage system that is separate from the first storage system. The at least one processing device is further configured to receive from the first storage system an indication of a write pressure condition arising in the second storage system and relating to replication of the data associated with the write requests from the first storage system to the second storage system, and to at least temporarily limit a manner in which additional write requests are sent to the first storage system responsive to the received indication of the write pressure condition arising in the second storage system.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: July 26, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Krishna Deepak Nuthakki, Arieh Don
  • Patent number: 11392303
    Abstract: A scanner is used to generate a set of processing power consumption metrics for a memory subsystem. From the set of processing power consumption metrics, a number of in-memory computations is determined. From the number of in-memory computations, a total computing score is determined. A user is notified of the total computing score.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: July 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Grzegorz Piotr Szczepanik, Vinod A. Valecha, Lukasz Jakub Palus, Krzysztof Rudek
  • Patent number: 11385834
    Abstract: A data storage device and a storage system including the same are disclosed. The data storage device includes a nonvolatile memory device configured to store user data and metadata including data type identification information matched with the user data, and a controller to control the nonvolatile memory device to be switched to a cold data storage device for storing cold data only when a number of program-erase (PE) cycles of the nonvolatile memory device is equal to or larger than a reference value.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventors: Yong Jin, Jun Hee Ryu, Jong Chan Kim, Kyong Seon Lim
  • Patent number: 11386024
    Abstract: According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: July 12, 2022
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 11379596
    Abstract: A method and a system for providing a bridging solution in order to ensure that a current authentication protocol remains effective when a new authentication protocol is to be introduced but has not yet been implemented at both ends of an interaction between a requesting application and a database are provided. The method includes determining whether a first authentication protocol that is currently implemented by the application is the same protocol as a second authentication protocol that is currently implemented by the database. When the two protocols are different, the first protocol is used to validate a request for data submitted by the application in conjunction with authentication information; the authentication information is converted into a format that is usable by the second protocol; and the converted information is used with the second protocol to generate information that indicates that the request has been authenticated.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 5, 2022
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Robert Macandrew, Miklos Kalman, Joel Klein
  • Patent number: 11379128
    Abstract: Systems, storage devices, and methods for application-based storage device configuration settings are described. A storage device may receive a storage command and dynamically select an application set of configuration settings for processing the storage command, where the configuration settings include trim parameters for writing data units to the storage medium of the storage device.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11372554
    Abstract: A method, computer program product, and computing system for receiving one or more IO requests at a cache system for storing content in a storage array. A maximum number of concurrent backend IO requests may be associated with the storage array based upon, at least in part, a change in size of the storage array. The one or more TO requests may be flushed to the storage array via one or more backend IO requests from the cache system based upon, at least in part, the maximum number of concurrent backend IO requests associated with the storage array.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 28, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Changyu Feng, Henry Austin Spang, IV, Jian Gao, Xinlei Xu, Ruiyong Jia, Yousheng Liu
  • Patent number: 11372756
    Abstract: Adding, by a memory management process executing in a computing device, a physical address of each of a plurality of available blocks of memory to a binary search tree based on the physical address. After the adding, receiving, by the memory management process, a request for a memory allocation, the memory allocation to be from the plurality of available blocks. Allocating, by the memory management process and in response to the request, blocks of memory in physical address order from the binary search tree.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Rajesh Kemisetti, Joseph Gee, Rex Perkins, Surendra Nallam
  • Patent number: 11372785
    Abstract: A server system is provided that includes one or more compute nodes that include at least one processor and a host memory device. The server system further includes a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device is configured to virtualize hardware resources of the plurality of SSD devices. The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: June 28, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vadim Makhervaks, Aaron William Ogus, Jason David Adrian
  • Patent number: 11372548
    Abstract: Some systems compress data utilized by a user mode software without the user mode software being aware of any compression taking place. To maintain that illusion, such systems prevent user mode software from being aware of and/or accessing the underlying compressed states of the data. While such an approach protects proprietary compression techniques used in such systems from being deciphered, such restrictions limit the ability of user mode software to use the underlying compressed forms of the data in new ways. Disclosed herein are various techniques for allowing user-mode software to access the underlying compressed states of data either directly or indirectly. Such techniques can be used, for example, to allow various user-mode software on a single system or on multiple systems to exchange data in the underlying compression format of the system(s) even when the user mode software is unable to decipher the compression format.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 28, 2022
    Assignee: NVIDIA Corporation
    Inventors: Ram Rangan, Patrick Richard Brown, Wishwesh Anil Gandhi, Steven James Heinrich, Mathias Heyer, Emmett Michael Kilgariff, Praveen Krishnamurthy, Dong Han Ryu
  • Patent number: 11372794
    Abstract: A data processing apparatus may include a master device, a slave device, and a controller configured to arbitrate communication between the master device and the slave device by: setting a respective Time-out Counter (TC) for each of requests transmitted from the master device, allocating one or more virtual channels to each of one or more request groups, the one or more virtual channels respectively corresponding to priority levels, associating a request with a virtual channel corresponding to the priority level of the request, for each request group, selecting one of the leading requests of the respective virtual channels according to the TCs and transmitting the selected request to the slave device.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventor: Soo Hong Ahn
  • Patent number: 11366617
    Abstract: Example methods are provided for unbalanced storage resource usage configuration for a distributed storage system in a virtualized computing environment. An example method may include obtaining usage data associated with multiple storage resources forming the distributed storage system. The multiple storage resources are supported by the multiple hosts. Based on the usage data, the method may further include determining a higher usage set and a lower usage set of one or more storage resources from the multiple storage resources and configuring the multiple hosts to use the multiple storage resources in an unbalanced manner by using the higher usage set of one or more storage resources at a higher usage level compared to the lower usage set of one or more storage resources.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 21, 2022
    Assignee: VMWARE, INC.
    Inventors: Zongliang Li, Wenguang Wang, Christian Dickmann, Mansi Shah, Tao Xie, Ye Zhang
  • Patent number: 11366591
    Abstract: A data system includes a plurality of storage drives each comprising a multi-lane serial drive interface. The data system also includes a control system configured to receive, over a host link, a write operation for storage of data, process a storage address of the write operation against storage allocation information to apportion the data for storage among more than one target storage drive, and transfer corresponding portions of the data to the target storage drives.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 21, 2022
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Alok Gupta, Himanshu Desai, Angelo Campos
  • Patent number: 11360701
    Abstract: A controller device is disclosed. The controller device comprises a communication interface that is configured to receive a data operation request via an interconnect bus. The controller device comprises an integrated interconnect protocol component that is configured to handle communication via the interconnect bus that supports coherency across a plurality of different processing devices external to the controller device. An integrated memory or storage controller component on the same controller device is configured to handle the data operation request including by being configured to manage communication with a memory or data storage device external to the controller device.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 14, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Narsing Krishna Vijayrao, Christian Markus Petersen
  • Patent number: 11360885
    Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang