Abstract: Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

Abstract: The invention addresses individual electronic components on a shared communication bus by using spatial indexing to route data based on the physical location of the electronic components. The spatially indexed two-line data bus maps a spatial grid to a plurality of indexed connection points, which are geometrically arranged in physical space, to a set of electrically conductive grid lines. The grid lines form a communication network which can be connected to electronic components physically located on the mapped spatial grid. In the preferred embodiment, the grid lines are comprised of copper traces on a printed circuit board (PCB). In another embodiment, the grid lines are comprised of connecting wires. The electronic components are connected electrically in parallel with the grid lines.

Abstract: Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).

Abstract: A processor to generate accumulated data comprising, for an operation cycle: performing an operation on a first bit range of a set of first input data to generate a set of operation data, which is accumulated with stored data within a first storage device. A lowest n bits of the accumulated data are accumulated with first further stored data within a first bit range of a second storage device, and are bit-shifted from the first storage device. Further accumulated data is generated, comprising, for an operation cycle: performing the operation on a second bit range of the set of first input data to generate a further set of operation data, which is accumulated with the stored data within the first storage device. A lowest m bits of the further accumulated data is accumulated with second further stored data within a second bit range of the second storage device.

Abstract: One aspect of the instant application can provide a storage system. The storage system can include a plurality of byte-addressable storage devices and a plurality of media controllers. A respective byte-addressable storage device is to store a parity block or a data block of a data stripe, and a respective media controller is coupled to a corresponding byte-addressable storage device. Each media controller can include a tracker logic block to serialize critical sections of multiple media-access sequences associated with an address on the corresponding byte-addressable storage device. Each media-access sequence comprises one or more read and/or write operations, and the data stripe may be inconsistent during a critical section of a media-access sequence.

Abstract: In some implementations, an integrated circuit may receive a read command associated with a data structure of the integrated circuit. The integrated circuit may determine that requested data, of the data structure and associated with an element within the data structure, is not ready for reading. The integrated circuit may output, based on determining that the requested data is not ready for reading, generated delay data. The integrated circuit may determine that the requested data, of the data structure and associated with the element, is ready for reading. The integrated circuit may output, based on determining that the data is ready for reading, the requested data.

Abstract: An apparatus includes a first die connected to a second die through a die-to-die (D2D) interface. The first die includes a first interconnect configured to provide first lanes communicating with the second die to the D2D interface, the first interconnect includes a first logic circuit configured to indicate a correlation between a number of chiplet dies connected to the first lanes and connected signal pins from among a plurality of signal pins of the connected chiplet dies. The second die includes the number of connected chiplet dies each including a second interconnect configured to provide second lanes to the D2D interface from each of the connected chiplet dies. The second lanes are configured to be set according to a number of the connected signal pins of the connected chiplet dies.

Abstract: Ransomware activity detection and data protection is implemented by a remote R2 storage array on an asynchronous remote data replication facility, on which data from a primary R1 storage array is replicated to the remote storage array. Write operations on storage volumes in a remote data replication group are collected in a capture cycle on the primary storage array, along with IO pattern metadata describing both read and write operations on the storage volumes. At the end of the capture cycle, the update and metadata is transmitted to the remote storage array. The remote storage array receives the update and metadata and temporarily stores the update prior to applying it to its copy of the storage volumes. Ransomware anomaly detection is implemented using the update and metadata, and if ransomware activity is detected, the data on the remote R2 storage array is protected, and the update is not applied.

Abstract: The present disclosure is directed toward systems, methods, and non-transitory computer readable media for generating and maintaining an intelligent, web-based digital content clipboard for viewing and performing batch actions on copied content items. In particular, based on a client device request to copy a content item from a web-based folder, the disclosed systems can generate and add an item reference for the copied content item to a batch action clipboard. The disclosed systems can perform batch actions on multiple digital content items together with a single web-based batch action. The disclosed systems can also intelligently provide a clipboard element for display that is selectable to view item references representing content items copied to the batch action clipboard, along with a set of available batch actions for performing on one or more of the copied content items.

Abstract: A write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. The write pattern of the host device is based on a number of I/O commands received from the host device and on a number of available memory blocks in the data storage device. If the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional I/O commands are received, the garbage collection process is initiated. An amount of valid data that is transferred from one memory location to another memory location during the garbage collection process is also dynamically determined. Thus, a garbage collection process may be tailored to a specific host device.

Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.

Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.

Abstract: According to one embodiment, a memory system includes a non-volatile memory including a plurality of physical blocks and a controller. The controller is configured to allocate the plurality of physical blocks to a plurality of first block sets each including physical blocks among the plurality of physical blocks, generate a plurality of groups obtained by grouping the plurality of first block sets by the number of defective physical blocks included in each of the plurality of first block sets, and select a plurality of the first block sets from at least two groups of the plurality of groups to generate a second block set from the plurality of selected first block sets.

Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

Abstract: Various embodiments include systems, methods, and non-transitory computer-readable media for managing data using persistent storage. Consistent with these embodiments, a method includes receiving a write request that includes a value and a key; processing the write request, the processing of the write request including generating a message that includes the value; transmitting the message to an external system for storage of the value; generating an index based on a mapping of the key to an offset; and storing the value and the index in a local persistent storage.

Abstract: In certain aspects, the memory controller includes a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a controller processor configured to control a memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by replacing original logical addresses of logical block address (LBA) segments of the file with new continuous logical addresses of a merged LBA segment of the file, and changing an original mapping relation between the original logical addresses of the LBA segment of the file and physical addresses of the file, to a new mapping relation between the new continuous logical addresses of the merged LBA segment of the file and the physical addresses of the file.

Abstract: A data storage device and method for host-determined proactive block clearance are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a command from a host that specifies a parameter of an upcoming burst mode; and in response to receiving the command, proactively perform a garbage collection operation according to the parameter to create available storage space in the memory to store data from the host during the upcoming burst mode. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A method, apparatus, and computer program product for tier-specific data compression, comprising comparing costs associated with a plurality of storage configurations for storing data based on one or more usage characteristics of data, wherein each storage configuration of the plurality of storage configurations corresponds to a particular storage tier of a plurality of storage tiers and a particular compression algorithm of a plurality of compression algorithms and based on the comparison of the costs, storing the data using a storage configuration of the plurality of storage configurations.

Abstract: A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.

Abstract: When having detected that key data set to an accelerator by command information is not key data permitted to use, a monitor unit issues, to a storage control unit, a suspension request for suspending processing related to writing of data, a compute unit having received an instruction from an application program reads data from the storage device, encrypts read data using the accelerator, and issues, to the storage control unit, an instruction to write encrypted data to the storage device, and when having received the suspension request, the storage control unit suspends processing related to writing of data to the storage device.

Abstract: Systems and techniques for application profiling to resize and reconfigure compute instances are generally described. In some examples, a first application executing in a user space of a first compute instance may be determined. A Berkeley Packet Filter (BPF) process may be executed in the user space of the first compute instance. The BPF process monitors resource consumption of a first resource of the first compute instance. First consumption data for the first resource may be determined. The first consumption data may be associated with a first process of the first application over a first period of time. The first consumption data may be evaluated using first criteria. A configuration of a second compute instance may be determined based on evaluation of the first consumption data using the first criteria. The second compute instance may be deployed according to the configuration.

Abstract: A data storage device comprising a non-volatile storage medium configured to store data, a data port configured to receive and transmit data between a host computer system and the data storage device and a controller. The controller is configured to receive, via the data port, a first command data structure comprising a status reporting activation and receive, via the data port, a second command data structure. In response to receiving the second command data structure, the controller is configured to, determine a response information associated with the second command data structure, and in response to the status reporting activation, determine a status information, and transmit, via the data port, a response data structure comprising the response information and the status information.

Abstract: A data storage device and method for accident-mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises single-level cell (SLC) memory and multi-level cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter accident mode; and in response to receiving the command from the vehicle to enter accident mode, relocate vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.

Abstract: Various devices, such as storage devices or systems are configured to efficiently process and update logical mappings within control table sets. Control table sets are often groupings of logical mapping corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these mappings must be updated within the control table set. Received changes to these mappings are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.

Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANS). In some examples, a GAN-based decoding reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Abstract: Provided are a method, a system, and a computer program product in which metadata associated with encrypted data is maintained in a cloud computing environment, where the metadata indicates whether reading of information in the encrypted data is restricted geographically. A controller provides a decryption code to a cloud server located in a geographical location. The decryption code is for decrypting the encrypted data. The controller provides the decryption code, based on a determination as to whether the metadata indicates whether the reading of information in the encrypted data is restricted geographically.

Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

Abstract: Methods, systems, and devices for capability messaging for memory operations across banks with multiple page access are described. Techniques are described for a memory system to use a same bank for first and second access operations of data associated with an access command. The data corresponding to the second access operation may be communicated after the data corresponding to the first access operation on the same data channels. Techniques are further described for including one or more additional access commands with the access command that use other banks. Techniques are further described for interleaving data sets communicated as a result of the access commands and for abutting data sets based on parameters obtained by the memory device. Techniques are further described for the generation and performance of internal access commands in accordance with a data transfer type indicated by a host system.

Abstract: A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.

Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: The present disclosure is directed to an operating method of a memory controller, a memory controller, a memory system, and an electronic device. Herein, the operating method can include determining a backup region to be used in an idle state from a memory array, when detecting that remaining capacity of a currently used backup region for storing redundancy parity data in the memory array is less than a required capacity of redundancy parity data to be written, determining the quantity of all backup regions for storing redundancy parity data including the backup region to be used in the memory array, deciding whether the quantity is larger than a preset threshold, and erasing backup regions having stored redundancy parity data in the memory array when the quantity is larger than the preset threshold.

Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.

Abstract: Systems, apparatuses and methods may provide for technology that prefetches compressed data and a sparsity bitmap from a memory to store the compressed data in a decode buffer, where the compressed data is associated with a plurality of tensors, wherein the compressed data is in a compressed format. The technology aligns the compressed data with the sparsity bitmap to generate decoded data, and provides the decoded data to a plurality of processing elements.

Abstract: One or more aspects of the present disclosure relate to performant destaging of write pending (WP) data to disk. In embodiments, an input/output (IO) workload is received at a storage array. Additionally, the IO workload can include an IO request with a random write request. Further, a write destage context for write-pending (WP) data corresponding to the random write request can be generated by a data services engine of the storage array. In addition, using the write destage context, a disk adapter (DA), at a backend of the storage array, is enabled to destage write-pending (WP) data without reading from a target write location of the random write request on a storage device on the storage array.

Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.

Abstract: One example method includes receiving, by a first computing entity from a second computing entity, a request for data, providing, by the first computing entity, a compliance API (Application Program Interface) to the second computing entity, receiving, by the first computing entity from the second computing entity, location information and/or data compliance information, by way of the compliance API, consulting, by the first computing entity, a mapping, and determining, based on information in the mapping and the location information and/or data compliance information, whether or not the data is permitted to be transmitted by the first computing entity to the second computing entity, and either transmitting the data to the second computing entity, or not transmitting the data to the second computing entity, based on data tags, the information in the mapping and the location information and/or data compliance information.

Abstract: A differential logger stores, into a log storage from a device memory, a differential log being a log of a device value that has changed at each execution of a control program. A collective logger collectively stores, at a set time, collection target device values into the log storage as reference data to be used to collect the differential log. A split logger acquires as split logs, after the set time, logs of the device values multiple times, and stores the split logs into the reference data storage. The differential logger overwrites data in the log storage with the differential log after new reference data is stored into the log storage.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

Abstract: One or more aspects of the present disclosure relate to relate to analyzing and mitigation storage array latency. In embodiments, an input/output (IO) workload is received by a storage array. Additionally, a latency corresponding to processing one or more IO requests of the IO workload is determined. For example, a factor corresponding to a significant portion of the latency is identified. Further, a remediation action is performed based on the factor identified.

Abstract: Embodiments of this application are applicable to the field of terminal technologies, and provide a file storage location determining method and apparatus, and a terminal. The method includes: A first terminal determines a plurality of candidate paths corresponding to a target file. Each candidate path points to one file storage location. The first terminal obtains file information of the target file. The first terminal determines, based on the file information and the plurality of candidate paths, a file storage location pointed to by a first candidate path in the plurality of candidate paths as a storage location of the target file. A matching degree of the first candidate path is a highest matching degree in matching degrees of the plurality of candidate paths. According to the foregoing method, accuracy of determining the file storage location is improved.

Abstract: A method of synchronously executing input/output operations (IOs) for a plurality of applications using a storage device with a file system includes the steps of: receiving a first write IO including an instruction to write first data at a first address of the file system; determining that, within a first range of the file system comprising the first address, there are no pending unmap IOs for deallocating storage space of the storage device from files of the plurality of applications; after determining that there are no pending unmap IOs within the first range, locking the first range to prevent incoming unmap IOs from deallocating storage space within the first range from the files of the plurality of applications; after locking the first range, writing the first data to the storage device at the first address; and after writing the first data, unlocking the first range.

Abstract: An image processing system capable of managing image data using a plurality of boxes, comprises a microphone that obtains a sound, an obtaining unit that obtains a user identifier based on voice information of a user obtained via the microphone, a specifying unit that specifies one box among the plurality of boxes based on specification information including at least the user identifier, and an informing unit that informs the user of information related to the specified one box.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: A system, method, and computer-readable medium for performing a data center monitoring and management operation, The data center monitoring and management operation includes receiving data center data for a data center, the data center data comprising data center memory associated data; receiving data center asset data for a plurality of data center assets, the data center asset data comprising data center asset memory associated data; providing the data center memory associated data and the data center asset memory associated data to a memory failure prediction model; and, training the memory failure prediction model using the data center memory associated data and the data center asset memory associated data.

Abstract: A memory system includes a memory area. A controller controls data. A first connector inputs the data and/or outputs the data, and is removable from the host. A first holding part is electrically disconnected from the memory area and the first connector and including a first port, and holds identification information used to authenticate an authority to initialize the memory area. The first port outputs the identification information to the host when receiving, from the host, an initialization command that instructs initialization of at least the part of the memory area. The controller includes a second port and an authentication part. The second port receives the initialization command from the host and receives the identification information via the first port. The authentication part executes initialization of at least the part of the memory area based on the initialization command and the identification information received at the second port.

Abstract: Systems, apparatus and methods are provided for determining an optimal performance profile and a predicted temperature. A method may include receiving a command from a host. The command may contain a logical block address (LBA) for data stored in a data storage system, a length for a data size associated with the command, and a timestamp associated with the command. The method may further include obtaining LBA information, the timestamp, the data size from the command, providing the LBA information, the timestamp, the data size, along with temperature readings, and a performance profile as inputs to a machine learning model, determining an optimal performance profile and a predicted temperature using the machine learning model and configuring a storage controller with settings of the optimal performance profile.

Abstract: An object storage system, a migration control device, and a migration control method are provided. The migration control method includes observing a plurality of total target input/output (I/O) throughputs, inferring a plurality of reference I/O throughputs by using a first neural network, observing a plurality of target I/O throughputs with respect to an i-th storage device, determining a target object to be migrated and a target storage device, in which the target object will be stored, by using a second neural network, and generating a command instructing to migrate the target object to the target storage device.

Abstract: Techniques are provided for creating secure IO (input/output) user connections between IO users and storage volumes. One method comprises establishing an IO user connection between a processor-based IO user and at least a portion of a storage volume on a storage array; obtaining IO user context information associated with the IO user connection, wherein the IO user context information comprises one or more keys for signature verification; and transmitting one or more IO operations over the IO user connection, wherein a signature associated with a given IO operation is evaluated to verify that the signature is a valid signature of one or more of the processor-based IO user and the storage array. The obtained IO user context information may further comprise an identifier of a signature generation function that generates the signature associated with the given IO operation and a connection identity string identifying the IO user connection.

Abstract: A direct-attached storage device software RAID crash dump system includes a chassis housing a software RAID subsystem coupled to physical storage devices, controller devices, and a hypervisor subsystem. The software RAID subsystem presents a primary controller device to the hypervisor subsystem as being connected to a logical storage device provided by the physical storage devices. When the software RAID subsystem receives a first crash dump command from the hypervisor subsystem directed to the primary controller device and identifying a crash dump logical storage subsystem in the logical storage device, it transmits a respective second crash dump command to each of a subset of the physical storage devices that provide the crash dump logical storage subsystem via a respective controller device that couple the software RAID subsystem to that physical storage device, confirms completion of the respective second crash dump commands, and transmits a crash dump confirmation to the hypervisor subsystem.