Control Technique Patents (Class 711/154)
  • Patent number: 11144527
    Abstract: Optimizing database table scans in presence of SMDO records is provided. An SMDO record corresponding to a most recent span of rows for a column associated with a query predicate is read. It is determined whether a condition for excluding a span of rows is true for the SMDO record based on a type of the query predicate. In response to determining that a condition for excluding a span of rows is not true for the SMDO record, the most recent span of rows is added to a list of spans of rows to scan. It is determined whether a condition for excluding all preceding spans of rows is true for the SMDO record based on the type of the query predicate. In response to determining that a condition for excluding all preceding spans of rows is true for the SMDO record, reading the set of SMDO records is stopped.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sunil Sarin, Ronen Grosman, Adam J. Storm
  • Patent number: 11144247
    Abstract: An aspect includes reading a first page and a corresponding second page from a storage device. The first page specifies a metadata page stored in persistent storage and having logical addresses of metadata, and the second page associates logical block addresses (LBAs) with corresponding physical locations for the metadata. An aspect also includes reading data for a RAID stripe according to an associated physical offset in the second page, accessing a stripe counter from the second page, and comparing the stripe counter from the second page to a stripe counter held in memory. Upon determining the stripe counter from the second page is not the same, a third page is loaded, and a physical location of the data is read from the third page that provides a hash value of the data and corresponding physical location. The physical location of the data is accessed, and the second page is updated.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: October 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Amitai Alkalay, Assaf Natanzon
  • Patent number: 11144213
    Abstract: A metadata track stores metadata corresponding to both a first customer data track and a second customer data track. In response to receiving a first request to perform a write on the first customer data track from a two track write process, exclusive access to the first customer data track is provided to the first request, and shared access to the metadata track is provided to the first request. In response to receiving a second request to perform a write on the second customer data track from the two track write process, exclusive access to the second customer data track is provided to the second request, and shared access to the metadata track is provided to the second request prior to providing exclusive access to the metadata track to at least one process that is waiting for exclusive access to the metadata track.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: Intemational Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Jared M. Minch, Beth A. Peterson
  • Patent number: 11137925
    Abstract: A method, computer program product, and computer system for identifying, by a computing device, a current persisted value of a reclamation pool. A default value of the reclamation pool may be identified. The current persisted value may be compared with the default value to determine which is a higher value. The current persisted value may be selected as a minimum memory operating state of the reclamation pool when the current persisted value is higher than the default value. The default value may be selected as the minimum memory operating state of the reclamation pool when the default value is higher than the current persisted value plus a multiplier defining a threshold size.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: October 5, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Michael L. Burriss, Bolt Liangliang Liu, Eric Qi Yao, Doris Jia Qian
  • Patent number: 11138037
    Abstract: A multi-processor system includes multiple processors arranged in multiple clusters. Different clusters have different power and performance characteristics. The system includes a task scheduler to schedule tasks to the processors. The task scheduler, in response to detection of a scheduling event trigger, is operative to identify a scheduling objective between a first objective of energy optimization and a second objective of load balance. The scheduling objective is identified based on at least respective operating frequencies and loading of all processors in a highest-capacity cluster of the multiple clusters. According to the identified scheduling objective, the task scheduler schedules a given task to a processor selected among the processors in the multiple clusters.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: October 5, 2021
    Assignee: MediaTek Inc.
    Inventors: Ya-Ting Chang, Chien-Hao Chiang, Ting-Chang Huang, Jing-Ting Wu, Jia-Ming Chen
  • Patent number: 11132311
    Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
  • Patent number: 11134121
    Abstract: The time required for recovery in a distributed computing system can be reduced. At least one node (for example a server) or a different computer (for example a management server) are provided in the distributed computing system which includes a plurality of nodes existing at a plurality of sites. One or more sites at which one or more nodes that hold one or more datasets identical to one or more datasets held by a node to be recovered are identified. For the recovery, it is determined, on the basis of the one or more identified sites, a restore destination site that is a site of a node to which the one or more identical datasets are to be restored from among the plurality of sites.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 28, 2021
    Assignee: HITACHI, LTD.
    Inventors: Kaiho Fukuchi, Jun Nemoto, Masakuni Agetsuma
  • Patent number: 11124073
    Abstract: Apparatuses, systems, kits, methods and storage medium associated with using different electrical energy source types with an electric vehicle are disclosed herein.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 21, 2021
    Assignee: HYSTER-YALE GROUP, INC.
    Inventor: Benjamin Johnson
  • Patent number: 11119939
    Abstract: The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: September 14, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Xiaowei Jiang, Shu Li
  • Patent number: 11119784
    Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side-channel based attack, such as one or more classes of an attack commonly known as Spectre. Novel instruction prefixes, and in certain embodiments one or more corresponding instruction prefix parameters, may be provided to enforce a serialized order of execution for particular instructions without serializing an entire instruction flow, thereby improving performance and mitigation reliability over existing solutions. In addition, improved mitigation of such attacks is provided by randomizing both the execution branch history as well as the source address of each vulnerable indirect branch, thereby eliminating the conditions required for such attacks.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Rodrigo Branco, Kekai Hu, Ke Sun, Henrique Kawakami
  • Patent number: 11120849
    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Chiaki Dono
  • Patent number: 11119952
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 14, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Brian Manula
  • Patent number: 11119654
    Abstract: Provided are a computer program product, system, and method for determining an optimal storage environment for data sets and for migrating data sets. Metadata for each application indicates storage pools used by the application to store data sets, wherein each storage pool is configured in one of a plurality of storage environments using different organization schemes to store data sets. The metadata for at least one application indicates storage pools to store the data sets for the application that are allocated from different storage environments. The metadata for an application is processed to determine a data set for the application stored in a first storage pool implemented in a first storage environment that should be stored in a second storage environment. The determined data set from the first storage pool to a second storage pool implemented in the second storage environment.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clea A. Zolotow, Thomas W. Bish, Bernhard J. Klingenberg, Petra Kopp, John V. Delaney
  • Patent number: 11113213
    Abstract: An interface of a memory sub-system can determine that a particular write command received from a host has a same address as a subsequently received write command from the host. The interface can delete the particular write command if it is still in the interface or send a signal to delete the particular write command if the write command has already been provided from the interface.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yue Chan
  • Patent number: 11113188
    Abstract: Combined operational steps and device characteristics help preserve data against integrity threats. Data is divided into critical data and non-critical data, based on criteria such as customer requirements, workload criticality, or virtual machine criticality. Data may be generated in a compute node for storage in a storage node, for example. Critical data is stored in a battery-backed memory aperture at physical addresses where it will be flushed ahead of the non-critical data due to a flush order imposed by or on the battery-backed memory, e.g., a bottom-up NVDIMM flush order. Redundant copies of the data (especially non-critical data) may also be kept in case it does not get flushed in time. Battery-backed memory apertures are sized and located according to their battery's characteristics, and may be relocated or resized as conditions change. Flush defragging is performed to optimize use of the aperture, especially within the portion that holds critical data.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mallik Bulusu, Tom L. Nguyen, Neeraj Ladkani, Ravi Mysore Shantamurthy
  • Patent number: 11108559
    Abstract: A method of integrating a distributed ledger represented by a blockchain with a distributed storage network (DSN) begins by sending a proof of existence request to the DSN, the proof of existence request including an object name, an object version, a start time and an end time. The method continues by reading the object metadata for the sent object name. The method continues by checking a revision history from object metadata associated with the sent object name to ensure the object existed by the start time through the end time with no deletions and, if the object did not exist by the start time through the end time with no deletions, rejecting the proof of existence request and returning an error response. If the object did exist by the start time on through the end time with no deletions, the method continues by producing and returning an attestation comprising verification information related to the object.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Vita Bortnikov, Michele Martino Franceshini, Ravi V. Khadiwala, Michael E. Factor, Roberta Jo Cochrane
  • Patent number: 11106391
    Abstract: A first set of characteristics corresponding to a first memory device and a second set of characteristics corresponding to a second memory device are received. A first usage threshold for the first memory device based on the first set of characteristics and a second usage threshold for the second memory device based on the second set of characteristics are determined. Data is stored at the first memory device or the second memory device based on the first usage threshold for the first memory device and the second usage threshold for the second memory device.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael B. Danielson, Paul A. Suhler
  • Patent number: 11106381
    Abstract: An apparatus comprises a host device configured to communicate over a network with first and second storage systems. The host device detects an association in at least one of the first and second storage systems between a source logical storage device of the first storage system and a target logical storage device of the second storage system, and responsive to the detected association, establishes a migration session in the host device for migration of the source logical storage device to the target logical storage device. The host device also obtains an indication from at least one of the first and second storage systems that a corresponding migration session has been activated in the first and second storage systems, and activates the previously-established migration session in the host device based at least in part on the obtained indication for migration of the source logical storage device to the target logical storage device.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinay G. Rao, Sanjib Mallick, Arieh Don
  • Patent number: 11108413
    Abstract: Disclosed are devices, systems and methods for polar coding and decoding for correcting deletion and insertion errors caused by a communication channel. One exemplary method for error correction includes receiving a portion of a block of polar-coded symbols that includes d?2 insertion or deletion symbol errors, the block comprising N symbols, the received portion of the block comprising M symbols; estimating, based on one or more recursive calculations in a successive cancellation decoder (SCD), a location or a value corresponding to each of the d errors; and decoding, based on estimated locations or values, the portion of the block of polar-coded symbols to generate an estimate of information bits that correspond to the block of polar-coded symbols, wherein the SCD comprises at least log2(N)+1 layers, each comprising up to d2N processing nodes arranged as N groups, each of the N groups comprising up to d2 processing nodes.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 31, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kuangda Tian, Arman Fazeli Chaghooshi, Alexander Vardy
  • Patent number: 11099981
    Abstract: An operating method of a memory system includes determining whether a write command currently provided is a sequential write command or a random write command, performing a garbage collection operation based on whether a total capacity of data provided after a preceding garbage collection operation exceeds a sequential command threshold value, when it is determined that the write command is a sequential write command, and performing the garbage collection operation based on whether a number of sequential write commands among a set number of commands currently provided, is greater than or equal to a predetermined number and whether the total capacity of the data provided after the preceding garbage collection operation exceeds the sequential command threshold value, when it is determined that the write command is a random write command.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong-Min Lee, Hyeong-Ju Na
  • Patent number: 11099788
    Abstract: An approach is provided for implementing near-memory data reduction during store operations to off-chip or off-die memory. A Near-Memory Reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced and when a store operation specifies an address within the range of addresses, the NRM unit performs data reduction by adding the data value specified by the store operation to an accumulated reduction result. According to an embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that are used to determine when data reduction has been completed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 24, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan Jayasena, Shaizeen Aga
  • Patent number: 11099900
    Abstract: A memory reclamation method and apparatus, where the method includes determining a target process from a background process list when current available memory of a system is less than a memory threshold, where the background process list includes a process of one or more applications, the target process is a process among the process of the one or more applications meeting a condition that an absolute value of a difference between memory occupied by the process and a memory pressure value is less than a preset threshold, and the memory pressure value is a difference between the memory threshold and the current available memory of the system, and sending a processing instruction to a system kernel to trigger the system kernel to reclaim the memory occupied by the target process.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 24, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qibin Yang, Xiaojun Duan
  • Patent number: 11093133
    Abstract: According to one or more embodiments of the present invention, computer implemented method includes obtaining by an input/output (I/O) subsystem a request block that includes a command code indicating a STORE IOP-UTILIZATION DATA command for tracking resource utilization during an asynchronous execution of an instance of a CPU DEFLATE command. The method further includes, based on the command code, initiating a command response block. The command response block includes multiple entries for input/output processor (IOP) utilization, each entry corresponding to resource utilization measurements of each IOP in the I/O subsystem. The method further includes, storing, in a command response code field of the command response block, a response code indicating that the resource utilization measurements have been recorded in the entries for IOP utilization. The response block includes a length code indicating a length of the response block and the response code field.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis P. Gomes, Anthony Thomas Sofia
  • Patent number: 11086638
    Abstract: The present disclosure discloses a method and apparatus for loading an application. An embodiment of the method comprises: selecting, in a programmable read-only memory, a storage space for storing a preset data section in an executable file of an application; copying the preset data section to a memory, and relocating the preset data section based on a start address of the storage space; and copying the relocated preset data section to the storage space. A relocation of a code portion of the executable file in the memory is implemented, and the relocated code portion is then written back into the programmable read-only memory, so that the relocation of the code portion can be completed only by one erase operation for a memory block, thereby reducing system overheads during the application loading process, and reducing wear of the programmable read-only memory.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 10, 2021
    Assignee: Baidu Online Network Technology (Beijing) Co., Ltd.
    Inventors: Haijun Pan, Hua Zhou, Lian Duan, Qingxing Wang, Guohua Zhang, Hao Su
  • Patent number: 11086820
    Abstract: A method and apparatus for reserving a usable storage space on a storage device is provided. The method includes collecting context data representing an environment surrounding the storage device; selecting at least one file from among files stored in the storage device by using at least one of the context data and user profile data; and processing the selected file and reserving a usable storage space on the storage device. The method reserves the usable storage space by using the context data or user profile data, thereby allowing efficient reserving of usable storage space without a user's manual intervention and preventing waste of unnecessary resources.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Muthukumar Subramanian, Revoti Prasad Bora
  • Patent number: 11086533
    Abstract: Disclosed herein is method and system for managing storage space complexity in a storage unit. In an embodiment, operational parameters related to memory operations and storage parameters related to memory blocks of the storage unit are analyzed to estimate storage capacity of each of the memory blocks. Subsequently, the memory blocks are clustered into plurality of clusters based on the storage capacity. Further, one or more of the plurality of clusters are selected for performing future memory operations based on ranking of the plurality of clusters. In some embodiments, the present disclosure helps in dynamically managing storage space complexity in the storage unit and optimizes the storage space utilization. Also, the present disclosure automatically handles storage volumes, thereby reducing latency in memory backup operations and reducing amount of buffer/cache memory required.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 10, 2021
    Assignee: Wipro Limited
    Inventors: Rishav Das, Sourav Mudi
  • Patent number: 11089097
    Abstract: The time required for recovery in a distributed computing system can be reduced. At least one node (for example a server) or a different computer (for example a management server) are provided in the distributed computing system which includes a plurality of nodes existing at a plurality of sites. One or more sites at which one or more nodes that hold one or more datasets identical to one or more datasets held by a node to be recovered are identified. For the recovery, it is determined, on the basis of the one or more identified sites, a restore destination site that is a site of a node to which the one or more identical datasets are to be restored from among the plurality of sites.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 10, 2021
    Assignee: HITACHI, LTD.
    Inventors: Kaiho Fukuchi, Jun Nemoto, Masakuni Agetsuma
  • Patent number: 11086736
    Abstract: A method, computer program product, and computer system for identifying, by a computing device, a pattern in a super block of a logger tier. It may be determined that the pattern in the super block of the logger tier is a known pattern, wherein the known pattern indicates invalid data in the logger tier. The logger tier may be booted up by storing an unknown pattern in the super block into the logger tier, wherein the unknown pattern indicates valid data in the logger tier.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 10, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Geng Han, Vamsi K. Vankamamidi, Socheavy D. Heng, Shuyu Lee, Jian Gao
  • Patent number: 11079962
    Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 3, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Davis, John Hayes, Brian Gold, Shantanu Gupta, Zhangxi Tan
  • Patent number: 11079966
    Abstract: A method, computer system, and a computer program product for soft fencing is provided. The present invention may include identifying a logical device swap occurred. The present invention may also include, in response to a logical device swap, creating a soft fence command. The present invention may then include issuing the created soft fence command.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Scott B. Compton, Tariq Hanif, Tri M. Hoang, Gregory E. McBride, Carol S. Mellgren, William J. Rooney
  • Patent number: 11068189
    Abstract: A control method of a storage device may include the steps of determining, by a storage device controller of the storage device, whether the storage device has to move internal data; deciding, by the storage device controller, a data movement allocation ratio based on at least some of internal data movement requests and the number of free pages in the storage device, when it is determined that the storage device has to move internal data; and allocating, by the storage device controller, one or more programming times to complete a first data number of internal data movement operations corresponding to at least some of the internal data movement requests and a second data number of host data write operations, such that the ratio of the first and second data numbers coincides with the data movement allocation ratio.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: July 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee, Chun-Shu Chen
  • Patent number: 11061851
    Abstract: A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 13, 2021
    Assignee: HITACHI, LTD.
    Inventors: Noboru Morishita, Masakuni Agetsuma, Akihiko Araki, Tomoki Sekiyama
  • Patent number: 11062026
    Abstract: Disclosed aspects relate to counter-fraud operation management. A counter-fraud operation may be executed using an initial set of parameter values for a set of parameters of the counter-fraud operation. A set of user counter-fraud activities of a user may be monitored corresponding to a user interface. A set of user feedback data may be captured to determine a feedback-driven set of parameter values for a set of parameters of the counter-fraud operation. The feedback-driven set of parameter values may be determined for the set of parameters of the counter-fraud operation. The counter-fraud operation using the feedback-driven set of parameter values may be executed.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian P. Byrne, Sushain Pandit, Kalaivanan Saravanan, Yogendra K. Srivastava
  • Patent number: 11062507
    Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: July 13, 2021
    Assignee: Apple Inc.
    Inventors: Anthony P. DeLaurier, Karl D. Mann, Tyson J. Bergland, Winnie W. Yeung
  • Patent number: 11055124
    Abstract: An information processing system comprises one or more processing platforms and implements a centralized storage provisioning and management system and a plurality of service provider storage systems coupled to the centralized storage provisioning and management system. The centralized storage provisioning and management system is configured to control provisioning and management of the service provider storage systems utilizing information collected from the service provider storage systems. The service provider storage systems may comprise respective service provider data centers, and the centralized storage provisioning and management system may comprise an additional data center separate from the service provider data centers. The centralized storage provisioning and management system may comprise a centralized control path implemented apart from the service provider storage systems.
    Type: Grant
    Filed: September 30, 2012
    Date of Patent: July 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Edward Brennan, Aaron T. Smith, Keith Meyer, Adnan Sahin, Mark Nadler, John O. Williams, II, Jesse D. Keefe
  • Patent number: 11048571
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolas Ioannou, Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Charalampos Pozidis, Aaron D. Fry, Timothy J. Fisher, Kevin E. Sallese
  • Patent number: 11050766
    Abstract: Methods, apparatus, and processor-readable storage media for generating unique virtual process identifiers are provided herein. An example computer-implemented method includes generating a virtual process identifier for a process within a given network, wherein the virtual process identifier is based at least in part on multiple items of process-related information; associating the virtual process identifier with one or more types of events to be carried out within the given network in connection with the process; filtering repetitive events from a set of processed events carried out in connection with the process, wherein filtering the repetitive events comprises identifying multiple instances of the virtual process identifier associated with multiple instances of the same type of event; and reporting, to at least one server, the processed events remaining subsequent to the filtering step.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vishnu C. Pedasingu, Phaneendra Mouli Ksl
  • Patent number: 11049546
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 29, 2021
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Patent number: 11048589
    Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 29, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
  • Patent number: 11036396
    Abstract: A data storage apparatus in accordance with an embodiment may include a memory device, a memory controller, and a media controller. The memory device may store data. The memory controller may output a packetized request signal for the memory device and receive a response signal to the packetized request signal according to a predetermined protocol. In response to a request packet provided from the memory controller, the media controller may generate a media command corresponding to the memory device, perform a read or write operation on the memory device, generate a response packet upon completion of the read or write operation, and transmit the generated response packet to the memory controller.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventor: Won Ha Choi
  • Patent number: 11036433
    Abstract: A memory controller includes a plurality of control signal pads and selectively controls a first-type memory and a second-type memory. The memory controller also includes a control signal generation unit configured to generate a control signal for controlling a selected memory. The memory controller further includes a control signal transfer unit configured to apply bits of a first control signal generated for controlling the first-type memory to respective control signal pads of the plurality of control signal pads, apply bits of a second control signal generated for controlling the second-type memory to a first control signal pad group selected among the plurality of control signal pads, and apply the second control signal to a second control signal pad group which is selected among the plurality of control signal pads independently of the first control signal pad group.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Geun Bae
  • Patent number: 11036409
    Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Zhenyu Zhu, Chai Huat Gan, Mikal Hunsaker
  • Patent number: 11029875
    Abstract: A data storage system includes an accelerator pool and data silos. The accelerator pool obtains a data storage request for first data; stores a copy of the first data locally in a memory of the accelerator pool; in response to storing the copy of the first data: sends an acknowledgement to a requesting entity that generated the data storage request; and, after sending the acknowledgement, stores at least one second copy of the first data in the data silos. The acknowledgement indicates that the first data is redundantly stored in at least two different fault domains.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Dell Products L.P.
    Inventors: Dharmesh M Patel, Rizwan Ali, Ravikanth Chaganti
  • Patent number: 11030198
    Abstract: Embodiments for reducing resource consumption of a similarity index in data deduplication by a processor. Only a latest generation of repository data is represented in the similarity index. Implicit deletion is applied in the similarity index. A subset of bytes of a full representative value is maintained in a similarity index entry. A respective one of a plurality of similarity units is deduplicated with a corresponding similarity unit of a previous snapshot, and a deduplication coverage thereof is examined. If a deduplication coverage threshold is not met, a similarity search is conducted and the respective one of the similarity units is deduplicated with a found similarity unit residing in the similarity index.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lior Aronovich
  • Patent number: 11029853
    Abstract: Apparatus and methods of operating solid-state drives in a storage system are described. A method includes adjusting, by a host controller of a storage system during run-time, storage bandwidth for a storage system process responsive to an input output (I/O) write request to write data to the storage system that includes multiple solid-state storage drives by determining an allocation share for the storage system process requesting to write the data, and responsive to determining an open segment usage by the storage system process is under the allocation share for the storage system process, opening a new segment for the storage system process.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 8, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Timothy W. Brennan, Nidhi Pankaj Doshi, Xiaohui Wang
  • Patent number: 11029864
    Abstract: A method and system for dynamic backup policy handshaking. Specifically, the method and system disclosed herein entail optimizing storage space utilization for backup, archiving, and/or disaster recovery-purposed data storage. That is, based on time projections until the data storage reaches capacity, the utilization of the remaining storage space may be optimized without compromising data protection in order to prolong the use of the data storage. In prolonging the utilization of the data storage, tiered data backup policies may be adjusted.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 8, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Supriya Kannery, Rahul Deo Vishwakarma
  • Patent number: 11029957
    Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Sahita, Deepak Gupta, Vedvyas Shanbhogue, David Hansen, Jason W. Brandt, Joseph Nuzman, Mingwei Zhang
  • Patent number: 11030153
    Abstract: System and method are provided for storing data using programmable rules on containers for collections of data items presented through the operating environment. This invention gives a container (folders or enhanced containers) the ability to be more than a straight-forward receptacle to contain a collection of data objects and other sub-containers. The invention provides for when data is added to a container system, collecting information from the data item and any pre-existing metadata, matching the information to a container using the container's rules, and if any matching containers are found, filing of the data item proceeds into any candidate locations.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 8, 2021
    Inventor: Charles Nicholls
  • Patent number: 11023392
    Abstract: Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Jean-Louis Labyre
  • Patent number: 11010081
    Abstract: An apparatus monitors an access load state of a plurality of logical volumes of a first storage device, and determines that an access load state of a subset of the plurality of logical volumes has changed from a high load state to a low load state. The apparatus migrates, when the subset of the plurality of logical volumes remains in a low load state after an elapsed setting time since the load state of the subset of the plurality of logical volumes changed from a high load state to a low load state, data stored in the subset of the plurality of logical volumes to a second storage device having an access rate lower than the first storage device.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 18, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe