Control Technique Patents (Class 711/154)
  • Patent number: 10810031
    Abstract: An example method of tracking memory modified by an assigned device includes allocating, by a hypervisor running a virtual machine, guest memory to a guest running on the virtual machine, where a device is assigned to the virtual machine. The method also includes reading, while the virtual machine is running on the hypervisor, a first input/output (I/O) state that indicates whether the device is currently processing one or more I/O requests, where the first I/O state is writable by the guest. The method further includes determining whether the first I/O state indicates that the device is currently processing one or more I/O requests. The method also includes determining to not transmit a memory page to a destination in response to determining that the first I/O state indicates that the device is currently processing one or more I/O requests. The memory page corresponds to the first I/O state.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 20, 2020
    Assignee: RED HAT ISRAEL, LTD.
    Inventor: Michael Tsirkin
  • Patent number: 10810133
    Abstract: Provided are systems and methods for an address translation circuit for a memory controller. In various implementations, the address translation circuit includes an address translation table operable to include a subset of address translations for a processor memory. An address translation memory can include all address translations for the processor memory. The address translation circuit can be operable to receive an input address for a transaction to processor memory. The address translation circuit can determine an index for the address translation table by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes an address translation for the input address. The address translation can generate and output a translated address using the address translation.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 20, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Steven Scott Larson
  • Patent number: 10802761
    Abstract: Systems and methods are provided for predicting commands. A controller of a memory system includes a receiver for sequentially receiving a plurality of commands for the memory device in a plurality of windows, and a control component including a finite state machine for training multiple groups of states based on characteristics of the plurality of windows, and predicting a characteristic of next commands, which is to be received in a next window subsequent to a last window among the plurality of windows, based on the multiple groups of states.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventors: Aliaksei Charnevich, Siarhei Zalivaka
  • Patent number: 10802743
    Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 13, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
  • Patent number: 10802739
    Abstract: A data storage device includes a disk and a plurality of actuators for reading and writing data on the disk in different physical realms. Each physical realm is associated with at least one logical zone domain including at least one logical zone. The at least one logical zone domain corresponds to an actuator of a plurality of actuators that accesses the physical realms associated with the at least one logical zone domain. In one aspect, reading and writing of data is enabled in one or more logical zones in response to a SATA zone activate command. In another aspect, a SATA read or write command is received indicating at least one logical address for data to read or written on the disk. Data is read or written in a physical realm using the actuator corresponding to a logical zone domain including the at least one logical address.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 13, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ralph O. Weber, William B. Boyle
  • Patent number: 10802718
    Abstract: A method for garbage collection of a volume in a log-structured file system is disclosed. The volume comprises a plurality of segments. Each of the segments comprises a plurality of blocks. An invalid block count of each of the segments is determined. The invalid block count is used as an index for ordering the segments in a garbage collection queue. A plurality of range areas are determined for the index. A migration rate of each range area is determined, and the migration rate of a given range area reflects an intensity of segment migration into/out of the given range area. A negative migration rate reflects a segment migration into the given range area. Garbage collection is performed based upon the migration rate.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 13, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Vyacheslav Anatolievich Dubeyko, Hongbo Zhang
  • Patent number: 10802989
    Abstract: Embodiments of this disclosure are directed to an execution profiling handler configured for intercepting an invocation of memory allocation library and observing memory allocation for an executable application process. The observed memory allocation can be used to update memory allocation meta-data for tracking purposes. The execution profiling handler can also intercept indirect branch calls to prevent heap allocation from converting to execution and intercept exploitation of heap memory to block execution.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: October 13, 2020
    Assignee: McAfee, LLC
    Inventors: Xiaoning Li, Lixin Lu, Ravi Sahita
  • Patent number: 10797804
    Abstract: A communication unit according to the present disclosure includes: a communication circuit section that receives transmission data divided into head data and one or more subsequent data from an communicated unit over a period of a plurality of time-segments; a storage section having a storage region in which at least the transmission data received by the communication circuit section is stored; and a control section that places a limitation on an access period to cause a period of access to the storage region in a period of a time-segment in which the subsequent data is transmitted to become shorter than a period of access to the storage region in a period of a time-segment in which the head data is transmitted.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 6, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Kenichi Kobayashi
  • Patent number: 10795609
    Abstract: Disclosed is a memory system includes a memory device including a plurality of memory blocks, a write operation management circuit configured to update write operation counts for the plurality of memory blocks, a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks, a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block, and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Sang-Gu Jo, Jong-Hyun Park
  • Patent number: 10795596
    Abstract: A method of performing deduplication by a computing device is provided. The method includes (a) as data is received by the computing device into blocks as part of write requests, creating an entry in a log for each of the blocks, each entry including information about that respective block and a digest computed from that respective block; and (b) after accumulating multiple entries in the log, processing the log for delayed deduplication, the processing including (i) retrieving digests from the log, (ii) performing lookups within a deduplication table of the retrieved digests, and (iii) performing deduplication operations based on the lookups using the information about blocks included within the log. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 6, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Vladimir Shveidel, Ronen Gazit, Alex Soukhman, Maor Rahamim
  • Patent number: 10789185
    Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 29, 2020
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
  • Patent number: 10783109
    Abstract: Embodiments provide a proxy between device management messaging protocols that are used to manage devices that are I2C bus endpoints coupled to a remote access controller. A map is generated of the detected I2C bus endpoints. Mapped I2C bus endpoints that support PLDM (Platform Level Data Model) messaging are identified. Next, the mapped I2C bus endpoints that do not correspond to an identified PLDM endpoint are presumed to be IPMI (Intelligent Platform Management Interface) endpoints and are mapped accordingly. A virtual PLDM endpoint for each of the presumed IPMI I2C bus endpoints. A remote access controller is configured for use of PLDM messaging with the virtual PLDM endpoints such that these PLDM messages are translated by the proxy to equivalent IPMI commands and transmitted to the IPMI endpoints. The proxy similarly converts IPMI messages from the IPMI endpoints to equivalent PLDM messages and provided to the remote access controller via the virtual PLDM endpoint.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 22, 2020
    Assignee: Dell Products, L.P.
    Inventors: Chitrak Gupta, Rama Rao Bisa, Rajeshkumar Ichchhubhai Patel
  • Patent number: 10776053
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 15, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Patent number: 10776273
    Abstract: A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, Nand pages, and multiple cache pages, wherein the Nand pages include current Nand pages and next Nand pages, wherein the current Nand pages is corresponding to a read command received from the controller, the memory page manager is configured to manage correlation of the Nand pages and the multiple cache pages, predict next Nand pages in accordance at least in part with the read command, the current Nand pages, or a combination thereof, and send the Nand pages to the controller, and the multiple cache pages contain pages loaded from the Nand pages.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Yungcheng Lo
  • Patent number: 10778815
    Abstract: A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth M Curewitz, Sean Eilert, Ameen D. Akel, Hongyu Wang
  • Patent number: 10768839
    Abstract: A memory system includes: a plurality of memory devices, each of which includes a first block and a second block; and a controller suitable for: storing data received from a host in a buffer; selecting a first block, of a memory device of the plurality of memory devices, to be programmed with the data; detecting a size of the data; controlling the memory device to program the data into the selected first block when the size is detected to be equal to a one-shot program size; determining a status of the memory device including the selected first block when the size is detected to be smaller than the one-shot program size; controlling the memory device to program the data into the selected first block when the memory device including the selected first block is determined to be in a first status; and controlling the memory device to program the data into the second block of the memory device when it is determined to be is a second status.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10769062
    Abstract: A Data Storage Device (DSD) includes a non-volatile memory configured to store data, and control circuitry configured to receive a memory access command from a host to access data in the non-volatile memory. A location is identified in the non-volatile memory for performing the memory access command using an Address Translation Layer (ATL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host or a granularity based on a memory Input/Output (IO) transaction size of a processor of the host. The non-volatile memory is accessed at the identified location to perform the memory access command.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: September 8, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 10771585
    Abstract: Embodiments of the present invention provide a method, system and computer program product for limiting client side data storage based upon client geolocation. In an embodiment of the invention, a method for the differentiated treatment of data at rest in a mobile device includes receiving in a cache manager a request to cache data in a cache of a mobile device. Also, a geolocation for the mobile device is retrieved contemporaneous with the receipt of the request. Thereafter, it is determined from the geolocation whether or not the mobile device is present within a restricted geographic zone. Finally, in response to determining that the mobile device is present within a restricted geographic zone, the cache manager is directed to cache the data in a cache in the mobile device. But, otherwise the cache manager is directed to cache the data in a cache disposed in the computer communications network.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Erin Bartholomew, Nicholas D. Gibson, M. Andrew Huffman, Spencer F. Hockeborn, Todd E. Kaplinger
  • Patent number: 10769115
    Abstract: The concepts relate to data handling, and more specifically to data handling scenarios where data is revised on one computer and stored on another computer. One example can obtain a set of blobs relating to revisions of a file. The example can determine a target size of datastore blobs. In an instance where a total size of the set of blobs is less than the target size, this example can aggregate the set of blobs into an individual datastore blob. Otherwise, the example can identify new or edited individual blobs of the set and aggregate the new or edited individual blobs into first datastore blobs. The example can also aggregate other individual blobs of the set into second datastore blobs.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: September 8, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mitesh Pankaj Patel, Miko Arnab Sakhya Singha Bose, Simon Peter Clarke, David Oliver, Andrew Watson, Ming-wei Wang, Steven Rayson
  • Patent number: 10768842
    Abstract: Technologies for providing shared memory for accelerator sleds includes an accelerator sled to receive, with a memory controller, a memory access request from an accelerator device to access a region of memory. The request is to identify the region of memory with a logical address. Additionally, the accelerator sled is to determine from a map of logical addresses and associated physical address, the physical address associated with the region of memory. In addition, the accelerator sled is to route the memory access request to a memory device associated with the determined physical address.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Henry Mitchel, Joe Grecco, Sujoy Sen, Francesc Guim Bernat, Susanne M. Balle, Evan Custodio, Paul Dormitzer
  • Patent number: 10770433
    Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 8, 2020
    Assignee: APPLE INC.
    Inventors: Chonghua Zhong, Jun Zhai, Kunzhong Hu
  • Patent number: 10761750
    Abstract: Techniques are provided for selectively storing data into allocation areas using streams. A set of allocation areas (e.g., ranges of block numbers such as virtual block numbers) are defined for a storage device. Data having particular characteristics (e.g., user data, metadata, hot data, cold data, randomly accessed data, sequentially accessed data, etc.) will be sent to the storage device for selective storage in corresponding allocation areas. For example, when a file system receives a write stream of hot data, the hot data may be assigned to a stream. The stream will be tagged using a stream identifier that is used as an indicator to the storage device to process data of the stream using an allocation area defined for hot data. In this way, data having different characteristics will be stored/confined within particular allocation areas of the storage device to reduce fragmentation and write amplification.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: September 1, 2020
    Assignee: NetApp Inc.
    Inventors: Ravikanth Dronamraju, Kyle Diggs Sterling, Mrinal K. Bhattacharjee, Mohit Gupta
  • Patent number: 10761779
    Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Steven C. Miller
  • Patent number: 10761775
    Abstract: According to some example embodiments, a method includes receiving, a first command from a host device; determining, if the first command is part of an association group of commands by determining a first value of a first parameter of the first command in an association context table entry is greater than zero, the first parameter including a total number of commands in the association group of commands; determining, a first value of a second parameter of the first command, the second parameter including a tag value identifying the association group of commands; decrementing, the first value of the first parameter of the first command in the association context table entry; determining, if the first value of the first parameter in the association context table entry is zero; and executing, an action indicated in a third parameter of the first command.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ramdas P. Kachare, Oscar P. Pinto, Xuebin Yao, Wentao Wu, Stephen G. Fischer, Fred Worley
  • Patent number: 10756975
    Abstract: Improving the multi-site software update for extension switches by automatically assigning extension switches at each data center with a role and then providing state messages between the extension switches to stage software update operations between the various extension switches that are involved. This allows the network administrator to commence the software update process on the extension switches at each data center without waiting for any extension switch to complete operations. The extension switches communicate with each other and the software update process completes automatically, with all extension switches at all data centers updated without further network administrator input.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 25, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Bao Vu, Todd Shoemaker, David Hegland, Gregory Wagner
  • Patent number: 10754571
    Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory device including a plurality of system blocks; and a memory controller configured to perform a read reclaim operation of copying system data stored in a selected system block to another one of the plurality of system blocks using information obtained during loading of the system data into the selected system block.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Jang Hwan Jun
  • Patent number: 10747891
    Abstract: Floating data protection is presented herein. The method comprises receiving a defined data protection policy; determining that the defined data protection policy is not susceptible to a single point of failure scenario; and in response to determining that the defined data protection policy is not susceptible to the single point of failure scenario, reducing a code fragment associated with a data portion based on the defined data protection policy.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Audrey Kurilov
  • Patent number: 10740130
    Abstract: A method, computer program product, and computing system for executing a first virtual machine on a hypervisor. A first communication channel is established between the first virtual machine and a first group of underlying hardware associated with the first virtual machine.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 11, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Jared C. Lyon
  • Patent number: 10742661
    Abstract: Implementations and methods herein provide a networked storage system including a plurality of physical storage devices configured to store data on a plurality of virtualized volumes, a key store configured to store a plurality of encryption keys, and a secure messaging manager configured to encrypt a message to each of the plurality of virtualized volumes using a different encryption key.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 11, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Christopher N. Allo, Richard O. Weiss
  • Patent number: 10740286
    Abstract: Validation of a migration task to migrate data from one data store to another may be performed prior to the migration of the data. Parameters associated with the migration may be evaluated according to one or more types of validations for the migration task. In some embodiments, users may specify the validations to perform for the migration task. A determination as to whether the migration task is valid may be performed for the migration task based on the parameter evaluations. A result indicating whether the migration task is valid may be provided to a user.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: August 11, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ilia Gilderman, Nicolas Anton Medhurst Hertl, Gal Eliraz Levonai, Edward Paul Murray, Michael J. Russo, John MacDonald Winford
  • Patent number: 10740033
    Abstract: A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: So-young Kim, Reum Oh, Haesuk Lee
  • Patent number: 10733027
    Abstract: This disclosure is directed to a technique for memory management where physical memory areas may be partitions into a hierarchy of portions, the hierarchy may include a domain level that includes a page level that includes a slice level that includes an object level. Objects within a slice are a consistent size but may be different sized for different slices. A set of states reflecting memory usage status for each of the slices includes: a clean state for unused; a partial state; a full state; and a dirty state. Responses to allocation requests may be performed by selecting objects that are in a most preferred state based on a state allocation cost and a memory allocation cost either alone or in combination. A compact memory layout may be used to reduce run-time fragmentation of memory.
    Type: Grant
    Filed: October 7, 2018
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Christopher J. Corsi, Sudhanshu Goswami, Kevin Kauffman
  • Patent number: 10725671
    Abstract: An information handling system for DIMM provisioning and RAS enablement may include a memory subsystem that may comprise a DIMM including a set of ranks, each rank of the set of ranks may include a set of DRAMs, each DRAM of the set of DRAMs including a set of rows, and a non-volatile memory associated with the DIMM. The DIMM may include a post package repair (PPR) history including a set of PPR history entries. Each PPR history entry of the set of PPR history entries may include a failed row count for each rank of a corresponding DRAM of the DIMM. The information handling system may also include a BIOS that may determine whether health of the DIMM is unhealthy that may be based on the PPR history. When the health of the DIMM may be unhealthy, the BIOS may also perform a PPR corrective action procedure.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Dell Products L.P.
    Inventors: Amit Sumanlal Shah, Ananya Mukherjee, Mark Lawrence Farley, Vadhiraj Sankaranarayanan
  • Patent number: 10725661
    Abstract: Provided are a computer program product, system, and method for selective write control in accordance with the present description. In one aspect, a write operation which is associated with a read operation, may be selectively discarded if write operations have been disabled and if the write operation is directed to update a designated write operation acceptance area such as metadata associated with the target data set, for example. As a result, the read operation may be permitted to proceed and will not fail because the associated write operation was discarded rather than attempting to commit the write operation to the designated write operation acceptance area, thereby avoiding an error condition for a storage unit such as a volume, in which write operations have been disabled. Accordingly, applications which seek to perform read operations may be permitted to access data stored on such a volume. Other aspects are described.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nikhil Khandelwal, Gregory E. McBride, David C. Reed, Richard A. Welp
  • Patent number: 10719245
    Abstract: In one embodiment, a storage system includes a processor, a memory coupled to the processor to store instructions for execution, and an IO tagging module executed by the processor to determine a plurality of child IO requests required to complete a plurality of received IO request transactions and to tag the IO request transaction and/or the associated child IO requests with a tag identifier uniquely identifying the IO request transaction. The system includes an IO scheduler module executed by the processor to prioritize the IO request transactions according to a policy by grouping the child IO requests based on the associated tag identifier. The grouped child IO requests of the IO request transactions are serviced by a plurality of storage devices of the storage system for an optimal performance.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 21, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Krishna Chaitanya Gudipati, Anil Ravindranath, Rahul Ugale
  • Patent number: 10719255
    Abstract: Systems and methods for migrating encrypted storage blocks in a security enhanced manner. An example method may comprise: selecting, by the hypervisor, a first storage block and a second storage block, the first storage block being associated with a virtual machine; associating the second storage block with the virtual machine; and providing, by the hypervisor, an instruction for the virtual machine to copy content of the first storage block to the second storage block.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 21, 2020
    Assignee: Red Hat, Inc.
    Inventors: Henri Han Van Riel, Michael Tsirkin
  • Patent number: 10719474
    Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas Kachare, Fred Worley, Xuebin Yao
  • Patent number: 10719269
    Abstract: There are provided a memory controller, a memory system including the memory controller, and a method of operating the memory controller. In a memory controller for accessing a plurality of memories in response to a request from a host, the memory controller includes: a processor for generating a command set, based on command generation information of a selected memory among the plurality of memories; and a storage circuit for storing command generation information of each of the plurality of memories.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Yeob Chun
  • Patent number: 10715622
    Abstract: An illustrative embodiment disclosed herein is an object store with distributed caching including a distributed cache cluster including a first cache on a first node device and a second cache on a second node device. The object store with distributed caching further includes a gateway server communicatively coupled to the distributed cache cluster. The gateway server receives a request to store an object from a client device, determines whether the object satisfies an object policy, determines whether the request indicates that the object is to be split up into a plurality of shards, and stores a first shard of the plurality of shards in the first cache and a second shard of the plurality of shards in the second cache.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 14, 2020
    Assignee: NUTANIX, INC.
    Inventors: Dezhou Jiang, Manik Taneja, Ranjan Parthasarathy, Xingchi Jin
  • Patent number: 10714169
    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Phil Reusswig, Pitamber Shukla, Sarath Puthenthermadam, Mohan Dunga, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Patent number: 10712973
    Abstract: A storage management apparatus includes a processor and a memory. The processor is configured to: identify a type of a storage apparatus based on a result of reception of a state information on the storage apparatus; execute first processing to receive, when the identified type is a first storage apparatus, first performance information on the first storage apparatus from the first storage apparatus, and store the first performance information in a database as data of a table coordinating the first performance information for each time period of reception; execute second processing to receive, when the identified type is a second storage apparatus, second performance information on the second storage apparatus from the second storage apparatus, and store the second performance information in the memory as data of a text-format file; and switch an execution between the first processing and the second processing depending on the identified type.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Tomoshi Takagawa, Fumihiko Kono
  • Patent number: 10706700
    Abstract: An apparatus for managing the storage of image data captured by a plurality of image capturing means is provided.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 7, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Christian Bergholdt Kvorning
  • Patent number: 10705925
    Abstract: Examples provided herein describe a system and method for satisfying recovery service level agreements (SLAs). For example, a first entity may determine that a first recovery operation is to be performed at a first storage device. The first entity may then determine that the first storage device is available. Responsive to determining that the first storage device is available, the first entity may establish a data connection with a first storage device and may perform a first recovery operation at the first storage device. The first entity may receive a second storage device availability message from a second entity that requests a second recovery operation at the first storage device and may facilitate communication with the second entity. The first entity may then perform the second recovery operation at the first storage device and communicate the recovered data to the second entity.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 7, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Mandar Nanivadekar, Veeresh Mallappa Anami
  • Patent number: 10694389
    Abstract: A network slice management method, a management unit, and a system, where the method includes receiving, by a first management unit, a first management request, where the first management request carries requirement information of a network slice or indication information, and the indication information is used to obtain the requirement information of the network slice. The method further includes determining, by the first management unit, requirement information of a subnet that forms the network slice. According to the method, the first management unit can determine the corresponding requirement information of the subnet based on the requirement information of the network slice.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 23, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ruiyue Xu, Lan Zou, Yan Zhou, Yan Li, Jun Wang
  • Patent number: 10691355
    Abstract: An apparatus in an illustrative embodiment comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to identify a storage volume to be migrated from a source storage system to a target storage system, and to issue one or more commands to at least one of the source storage system and a host device as part of a migration session for the storage volume. Responsive to the one or more commands, a plurality of data pages are received, with the data pages having respective hash values that are computed based at least in part on a native page size of the target storage system as specified in at least one of the one or more commands. The one or more commands illustratively comprise a plurality of read next page commands, with a given one of the read next page commands including information identifying the storage volume, the native page size of the target storage system, and the migration session.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 23, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Anton Kucherov, David Meiri
  • Patent number: 10684798
    Abstract: A memory controller includes a flash translation layer configured to output a descriptor including a command and physical information and logical information associated with the command, and a flash interface layer configured to receive the descriptor, individually store the command, the physical information, and the logical information that are included in the descriptor, adjust a queue of the command, and output the command to a memory device according to an adjusted queue of the command.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventor: Joo Young Lee
  • Patent number: 10678482
    Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Oluwatobi A. Ajila, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
  • Patent number: 10678446
    Abstract: Novel technology for data object processing may include a system comprising a non-transitory memory; a non-transitory storage device; and a storage logic communicatively coupled to the non-transitory storage device and the non-transitory memory. The storage logic may be executable to perform operations comprising preparing a first log payload in the non-transitory memory; generating a first log bitmap describing a set of states for a set of logical blocks of an erase block of the non-transitory storage device; generating a first log including the first log bitmap and the first log payload; and storing the first log in the erase block of the non-transitory storage device.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 9, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Viacheslav Anatolyevich Dubeyko
  • Patent number: 10678464
    Abstract: Embodiments of the present disclosure provide methods and apparatuses for data migration of storage devices including registering at least one executing unit for data migration, each of the at least one executing unit corresponding to description file; extracting and storing information contained in the description file corresponding to each of the at least one executing unit; receiving a data migration request from a user; in response to the data migration request from the user, selecting an executing unit for data migration of the user at least based on part of the stored information contained in the description file; and scheduling an instance of the selected executing unit to execute data migration of the user. The methods or apparatuses according to embodiments of the present disclosure can implement, in a uniform and scalable manner, data migration for various formats, various performance requirements, and application scenarios.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Junping Frank Zhao, Layne Lin Peng, Yu Cao, Sanping Li, Zhe Dong
  • Patent number: 10671572
    Abstract: A system includes reception of a first write request from a client including a first key and a first one or more stream, payload pairs associated with the first key, copying of the first key and the first one or more stream, payload pairs to a first buffer of a volatile memory, storage of data of the first buffer in one or more blocks of a raw block non-volatile memory device, providing of the first buffer to a stream store server, reception of the first buffer at the stream store server, adding of the first key and the first one or more stream, payload pairs to a second buffer of the volatile memory, in key-order, storage of the data of the second buffer in a filesystem storage device, according to stream, and transmission of an indication of the durability of the key to the tail store server.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 2, 2020
    Assignee: SAP SE
    Inventors: Nathan Auch, Scott MacLean, Peter Bumbulis, Jeffrey Pound, Anil Kumar Goel