Abstract: Systems, methods, and a multipath initiator for a data storage device array that presents a single path host interface are described. The multipath initiator includes at least two backend paths to multiport data storage devices and a single path host interface. The initiator may determine a queue pair identifier for a host connection and storage commands to that host connection. The initiator may assign a path identifier, such as for a first backend path or a second backend path, to use for storage commands and send the storage commands to the data storage devices using the selected backend path.

Abstract: This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function of a memory controller may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device for a group of data bits. For example, the data mask function may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

Abstract: Implementations described herein relate to host device initiated low temperature thermal throttling. A memory device may receive, from a host device, a low temperature thermal throttling command that indicates for the memory device to initiate a thermal throttling operation based on a temperature of the memory device not satisfying a temperature threshold. The low temperature thermal throttling command may indicate an amount of dummy data to be moved from the host device to a particular location of the memory device associated with the thermal throttling operation. The memory device may perform the thermal throttling operation based on moving the dummy data from the host device to the particular location of the memory device. The memory device may complete the thermal throttling operation based on moving the amount of data from the host device to the particular location of the memory device.

Abstract: An industrial system for controlling backplane communication, including: a cluster manager including a primary switch linked to a primary control module, at least one Input/Output, I/O, module including a secondary switch linked to a secondary control module, a unidirectional communication line linking the cluster manager to the at least one IO module through passive base plates, wherein the cluster manager includes a transmission port and a reception port on the unidirectional communication line and the at least one Input/Output module includes a reception port on the unidirectional communication line, wherein the primary control module is configured to generate a pulse via the transmission port on the unidirectional communication line, wherein, upon reception of the pulse, the primary control module is configured to create a primary timestamp from a primary clock of the primary switch and the secondary control module is configured to create a secondary timestamp from a secondary clock of the secondary sw

Abstract: A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller including an internal buffer including zone buffers, and configured to: allocate a plurality of zones to a storage space, select two or more erase units to be allocated to each zone based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones, based on reads for sequential logical addresses being requested by the external host device, read first data corresponding to the sequential logical addresses from the nonvolatile memory device, and output the first data to the external host device, and based on the reads being requested, perform a prefetch operation by reading second data corresponding to next sequential logical addresses, and storing the second data in the internal buffer, without receiving a next read request from the external host device.

Abstract: Aspects of a storage device are provided for handling detection and operations associated with an erase block type of the block. The storage device includes one or more non-volatile memories each including a block, and one or more controllers operable to cause the storage device to perform erase type detection and associated operations for single blocks or metablocks. For instance, the controller(s) may erase the block prior to a power loss event, perform at least one read of the block following the power loss event, identify the erase block type of the block in response to the at least one read, and program the block based on the identified erase block type without performing a subsequent erase prior to the program. The controller(s) may also perform metablock operations associated with the identified erase block type. Thus, unnecessary erase operations during recovery from an ungraceful shutdown (UGSD) may be mitigated.

Abstract: Contents of the next commands are considered as part of an arbitration between virtual functions (VFs). The device controller will hold the head of the submission queues (SQ) internally. The controller is able to do so by implementing a small first in first out (FIFO) per submission queue. The second arbiter and the main arbiter, which is responsible for the command scheduling, fetches the commands from the internal small FIFO. Using this technique, the second arbiter gains visibility of the next commands that participate in the arbitration since the next commands are held internally and not in host memory.

Abstract: A storage device of the present disclosure includes a memory device including a system memory storing system information used in an operation, and a register storing a register value indicating that the system information is a first state or a second state, and a memory controller configured to control the memory device to receive the register value from the memory device when power is turned on, and to initialize the system information stored in the system memory when the received register value indicates that the system information is the first state.

Abstract: An inflight-I/O-based storage emulation system includes a storage emulation device coupled to host devices, and to storage devices that provide primary, secondary, and metadata storage systems. The storage emulation device stores I/O commands directed to the primary storage system by the host devices in its I/O queue. If the storage emulation device predicts I/O operations for I/O commands in its I/O queue do not exceed a threshold, it executes at least some of those I/O commands to store first data in the primary storage system. If the storage emulation device predicts I/O operations for I/O commands in its I/O queue exceed the threshold, it executes at least some of those I/O commands to store second data in the secondary storage system, and provides mapping information in the metadata storage system that identifies storage location(s) in the primary storage system associated with the second data in the secondary storage system.

Abstract: A storage device minimizes updates to compressed msets based on a priority criterion. The storage device includes a memory including a logical-to-physical (L2P) table divided into msets that include a range of entries in the L2P table. The storage device also includes memory to cache a first set of msets. A controller on the storage device accesses the first set of msets to quickly read data from and write data to the memory device. The controller determines a uLayer state for a first mset in the first set of msets, a read ratio for the first mset, a prediction for the first mset, and/or a queue depth for the first mset in determining whether the first mset meets the priority criterion and is ready for compression. The controller assigns a high priority to the first mset if the first mset meets the priority criterion and compresses the first mset.

Abstract: A method for controlling a memory system is disclosed. For example, the method can include performing an operation on a memory device of the memory system, calculating a remaining payload based on a current total payload and a payload associated with the operation performed on the memory device, and when the remaining payload meets a predefined requirement, measuring a current temperature of the memory device and setting the current total payload associated with the current temperature for the memory device.

Abstract: A computing device includes a storage device and a memory. The storage device includes nonvolatile and internal buffer memories, and a storage controller that controls the nonvolatile and internal buffer memories and communicates with a bus. The memory includes a buffer memory and a memory controller that controls the buffer memory and communicates with the bus. The nonvolatile memory stores user data and map data. In an initialization operation, the storage controller sends the map data to the memory through the bus, and the memory controller stores the map data that is transferred from the storage device through the bus, in the buffer memory. After the initialization operation, the memory controller sends partial map data of the map data to the storage device through the bus, and the storage controller stores the partial map data that is transferred from the memory through the bus, in the internal buffer memory.

Abstract: The embodiments of the present disclosure are generally directed to zero-duplicate direct-memory-access data buffer management in a data communication interface and are particularly directed to an efficient and collaborative buffer management for data transmission and synchronization between a plurality of data sources (data producers) and a data destination (data consumers) via the data communication interface. In one example, the disclosed buffer management approach combines zero-duplicate buffers, priority-based buffer allocation, priority-based data synchronization, and a collaborative communicated buffer holding time to manage the direct-memory-access and release of buffered data in a real-time and continuous dataflow producer-consumer system.

Abstract: A multi-stream solid-state device (SSD) includes a normal-access memory associated with a first stream ID, a high-access memory having a higher endurance than the normal-access memory and being associated with a second stream ID, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform identifying a data stream ID of an input data stream as one of the first and second stream IDs, in response to identifying the data stream ID as the first stream ID, storing the input data stream in the normal-access memory, and in response to identifying the data stream ID as the second stream ID, storing the input data stream in the high-access memory.

Abstract: A storage device includes a nonvolatile memory device that stores user data, and a storage controller that controls the nonvolatile memory device under control of a host device. The storage controller includes a storage interface circuit that communicates with the host device through a compute express link (CXL) interface, a NAND interface circuit that communicates with the nonvolatile memory device, and a processor that loads map data from an external memory device through the storage interface circuit and controls the nonvolatile memory device through the NAND interface circuit based on the map data.

Abstract: Example implementations relate to data storage. An example includes inspecting a block level input/output (I/O) request to be executed by a block-based storage device, and in response to a determination that the block level I/O request includes a filesystem operation, generating a copy of the block level I/O request. The example also includes parsing the copy of the block level I/O request to extract a plurality of attributes of the filesystem operation, where the parsing is asynchronous to an execution of the block level I/O request by the block-based storage device. The example also includes storing the extracted plurality of attributes of the filesystem operation in an entry of a filesystem operation database, where each entry of the filesystem operation database is associated with a different filesystem operation in a filesystem stored on the block-based storage device.

Abstract: A controller of a storage device receives a stream of data from a host system. The stream of data corresponds to logical block addresses. The controller writes the stream of data to data block(s) in a device memory, each data block including respective super word line(s), each super word line including respective word line(s), and each word line corresponding to at least one logical block address. The controller generates a table for storing the logical block addresses in the order of data arrival. In response to receiving an update to one or more logical block addresses of the data block(s), the controller defragments at least one data block, based on the one or more logical block addresses, and writes data for one or more super word lines of the at least one data block to a new data block, based on the table, to retain the order.

Abstract: Systems and methods provide witness sled hardware that may be installed in a chassis and that is configurable using management resources of a chassis in which the witness sled is installed. The chassis may include data storage devices and Information Handling Systems (IHSs), each including one or more CPUs (Central Processing Units) that execute instructions that cause a respective IHS to store data redundantly to the plurality of data storage devices, such as part of a vSAN (Virtual Storage Area Network). The witness sled is configured to provide witness functions, such as arbitrating discrepancies in the redundantly stored data. The chassis includes a management controller that is configured to interface with the witness sled to set up high-speed network connections supported by the witness sled in order to configure the witness sled for providing witness functions within the vSAN, while accounting for the limited resources of the compute sled.

Abstract: Methods and apparatus for end-to-end data plane offloading for distributed storage using protocol hardware and Protocol Independent Switch Architecture (PISA) devices. Hardware-based data plane forwarding is implemented in compute and storage switches that comprise smart server switches running software executing in a kernel and user space. The compute switch is coupled to one or more compute servers/nodes and the storage server is coupled to one or more storage servers or storage arrays. The hardware-based data plane forwarding facilitates an end-to-end data plane between the computer server(s) and storage server(s)/array(s) that is offloaded to hardware. In one example the software comprises Ceph components used to implement control plane operations in connection with hardware offloaded data plane operations, and storage traffic employs the NVMe-oF protocol and the kernels include NVMe-oF modules. In one aspect the hardware-based data plane forwarding is implemented using programmable P4switch chips.

Abstract: The present application provides a sequential read prefetching method and apparatus based on an Inspur Cluster File System (ICFS) distributed block storage system, a device, and a non-volatile readable storage medium. The method includes: in response to an OSD receiving a read request issued by a client, determining whether the read request is a sequential read request; in response to the read request being the sequential read request, creating a prefetching sliding window according to a data object to be read in the read request; in response to completion of the creation of the prefetching sliding window, calculating, according to the data object to be read in the read request, anew volume object needing to be prefetched; and adding the calculated new volume object needing to be prefetched into a queue of objects to be prefetched of the prefetching sliding window and executing prefetching.

Abstract: A memory controller includes: a data separator configured to separate host write data into upper data and lower data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing the upper data into a first storage region that is selected based on the first address in a memory, and one or more second commands for writing the lower data into a second storage region that is selected based on the second address in the memory; and a control block configured to control the address generator and the command generator to make a difference in power consumption between the first storage region and the second storage region.

Abstract: An information storage device includes a storage unit, a control unit, an allocation information storage unit, a QoS parameter storage unit, and a monitoring result storage unit. The control unit creates and manages a logical storage area using the storage area of the storage unit when a storage area allocation request is received. The allocation information storage unit stores allocation information related to logical storage areas. The QoS parameter storage unit stores quality requests expected to be satisfied for a communication for using the logical storage area. The control unit monitors the operating state and characteristics of the storage unit and the communication status, and stores the results in the monitoring result storage unit. The control unit derives internal QoS parameters to be set in the information storage device from the information stored in the allocation information storage unit, the QoS parameter storage unit, and the monitoring result storage unit.

Abstract: This application discloses a storage space organization method and an electronic device. A kernel of the electronic device includes a file system and a block layer, and the method includes: monitoring, by the electronic device, input/output ports IOs through the block layer, and determining, by the block layer when there is IO release, whether all the IOs have been released; and updating, by the electronic device when all the IOs have been released, a state of the file system to an idle state through the block layer, to trigger the electronic device to perform first garbage collection processing through the file system, where the state of the file system includes the idle state and a busy state.

Abstract: This application describes a hardware accelerator and a device for accelerating neural network computations. An example accelerator may include multiple cores and a central processing unit (CPU) respectively associated with DDRs, a data exchange interface connecting a host device to the accelerator, and a three-layer NoC architecture. The three-layer NoC architecture includes an outer-layer NoC configured to transfer data between the host device and the DDRs, a middle-layer NoC configured to transfer data among the plurality of cores; and an inner-layer NoC within each core and including a cross-bar network for broadcasting weights and activations of neural networks from a global buffer of the core to a plurality of processing entity (PE) clusters within the core.

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the multi-bit wide logical column in the logical row stored in a different physical row and physical one-bit wide column in one of plurality of dies.

Abstract: A system includes a memory device containing multiple dies that each have multiple pages, and a processing device, operatively coupled with the memory device, to perform various operations including scanning a group of pages residing on a die and determining a value of one data state metric and a corresponding value of another state metric. The operations can also include recording a set of values of the first metric and a corresponding set of values of the second metric, as well as calculating the value of the second metric corresponding to a predetermined value of the first metric associated with a failure condition of the die. Additionally, the operations can include identifying a particular criterion that is satisfied by the calculated value, assigning, to the die, a rating corresponding to the identified criterion, and performing scans on the die at a frequency determined by the assigned rating.

Abstract: A data processing apparatus and method are disclosed. The data processing apparatus may include a host core configured to generate a control message to control a direct memory access (DMA), the DMA configured to generate a memory request based on the control message, a memory controller configured to generate a memory command based on the memory request, and a processor configured to perform an operation in a memory based on the memory command.

Abstract: This application discloses a method and system of using HMB as a cache of physical address mapping table. The method comprises: arranging physical addresses in order of logical addresses, physical mapping entries corresponding to a plurality of consecutive physical addresses form one table unit, and a logical address corresponding to a first entry of each table unit is used as an index of the table unit; determining HMB size, dividing all table units into a plurality of sections according to the HMB size, each section comprises a plurality of table units, each section is divided into a plurality of ways; calculating a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, the metadata comprises a section number and a way number; writing the metadata and the table unit to be stored into the HMB. This application uses HMB as L2P address mapping table cache of SSD controller, saving or avoiding use cost of DRAM on SSD, and reducing SSD size.

Abstract: Virtual memory pooling, including identifying GPUs of respective IHSs, wherein each of the GPUs is associated with a respective internal memory allocation; partitioning, for each GPU, the internal memory allocation associated with the GPU into a first memory allocation and a second memory allocation; allocating, for each GPU, the first memory allocation of the internal memory allocation associated with the GPU as accessible only by the associated GPU; pooling, for each GPU, the second memory allocation of the internal memory allocation associated with the GPU to define a virtual memory pool, the virtual memory pool accessible by each GPU; processing, at a first GPU, a computational task, including: accessing the first memory allocation associated with the first GPU; determining that processing of the computational task exceeds a capacity of the first memory allocation of the first GPU and in response, requesting access to the virtual memory pool.

Abstract: A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Abstract: Deferred memory page allocation commands and non-deferred memory page allocation commands are identified within host I/O commands received by a data storage system. For each one of those received host I/O commands that are identified as a deferred memory page allocation command, QoS (Quality of Service) policy enforcement is performed before any memory pages are allocated by the data storage system to store host data indicated by the received command. Host I/O commands that are identified as deferred memory page allocation commands include read commands, and host I/O commands that are identified as non-deferred memory page allocation commands include in-capsule write commands. For commands identified as deferred memory page allocation commands, enforcing QoS policy before any memory pages are allocated to store host data indicated by the command avoids the possibility of enqueueing the allocated memory pages onto the QoS wait queue, thus conserving data storage system memory resources.

Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

Abstract: A method for operating a computational storage device includes receiving by a storage controller and from a host device: (1) a compute namespace setting instruction instructing the setting of a compute namespace; (2) a latency threshold value related to the compute namespace; (3) a program; (4) a first execute command using the program; and (5) a second execute command using the program. Additionally, the method includes transmitting, by the storage controller and to the host device, a latency message in response to the second execute command.

Abstract: A system and method for inspecting virtual instances in a cloud computing environment for cybersecurity threats utilizing disk cloning. The method includes: selecting a virtual instance in a cloud computing environment, wherein the virtual instance includes a disk having a disk descriptor with an address in a cloud storage system; generating an instruction to clone the disk of the virtual instance, the instruction when executed causes generation of a cloned disk descriptor, the cloned disk descriptor having a data field including the address of the disk of the virtual instance; inspecting the cloned disk for a cybersecurity threat; and releasing the cloned disk in response to completing the inspection of the cloned disk.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: An electronic device includes a host device and a plurality of storage devices. The host device includes a processor and a baseboard management controller (BMC). Each of the plurality of storage devices includes a storage controller and a micro controller unit (MCU). The processor and the storage controller support in-band communication, and the BMC and the MCU support out-of-band communication. The BMC receives monitoring data from the MCU of each of the plurality of storage devices based on the out-of-band communication. The processor allocates a first workload among one or more workloads to a first storage device among the plurality of storage devices, based on a monitoring data set including the monitoring data. The first storage device executes the first workload based on the in-band communication.

Abstract: Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).

Abstract: A processor to generate accumulated data comprising, for an operation cycle: performing an operation on a first bit range of a set of first input data to generate a set of operation data, which is accumulated with stored data within a first storage device. A lowest n bits of the accumulated data are accumulated with first further stored data within a first bit range of a second storage device, and are bit-shifted from the first storage device. Further accumulated data is generated, comprising, for an operation cycle: performing the operation on a second bit range of the set of first input data to generate a further set of operation data, which is accumulated with the stored data within the first storage device. A lowest m bits of the further accumulated data is accumulated with second further stored data within a second bit range of the second storage device.

Abstract: Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

Abstract: The invention addresses individual electronic components on a shared communication bus by using spatial indexing to route data based on the physical location of the electronic components. The spatially indexed two-line data bus maps a spatial grid to a plurality of indexed connection points, which are geometrically arranged in physical space, to a set of electrically conductive grid lines. The grid lines form a communication network which can be connected to electronic components physically located on the mapped spatial grid. In the preferred embodiment, the grid lines are comprised of copper traces on a printed circuit board (PCB). In another embodiment, the grid lines are comprised of connecting wires. The electronic components are connected electrically in parallel with the grid lines.

Abstract: An apparatus includes a first die connected to a second die through a die-to-die (D2D) interface. The first die includes a first interconnect configured to provide first lanes communicating with the second die to the D2D interface, the first interconnect includes a first logic circuit configured to indicate a correlation between a number of chiplet dies connected to the first lanes and connected signal pins from among a plurality of signal pins of the connected chiplet dies. The second die includes the number of connected chiplet dies each including a second interconnect configured to provide second lanes to the D2D interface from each of the connected chiplet dies. The second lanes are configured to be set according to a number of the connected signal pins of the connected chiplet dies.

Abstract: The present disclosure is directed toward systems, methods, and non-transitory computer readable media for generating and maintaining an intelligent, web-based digital content clipboard for viewing and performing batch actions on copied content items. In particular, based on a client device request to copy a content item from a web-based folder, the disclosed systems can generate and add an item reference for the copied content item to a batch action clipboard. The disclosed systems can perform batch actions on multiple digital content items together with a single web-based batch action. The disclosed systems can also intelligently provide a clipboard element for display that is selectable to view item references representing content items copied to the batch action clipboard, along with a set of available batch actions for performing on one or more of the copied content items.

Abstract: In some implementations, an integrated circuit may receive a read command associated with a data structure of the integrated circuit. The integrated circuit may determine that requested data, of the data structure and associated with an element within the data structure, is not ready for reading. The integrated circuit may output, based on determining that the requested data is not ready for reading, generated delay data. The integrated circuit may determine that the requested data, of the data structure and associated with the element, is ready for reading. The integrated circuit may output, based on determining that the data is ready for reading, the requested data.

Abstract: One aspect of the instant application can provide a storage system. The storage system can include a plurality of byte-addressable storage devices and a plurality of media controllers. A respective byte-addressable storage device is to store a parity block or a data block of a data stripe, and a respective media controller is coupled to a corresponding byte-addressable storage device. Each media controller can include a tracker logic block to serialize critical sections of multiple media-access sequences associated with an address on the corresponding byte-addressable storage device. Each media-access sequence comprises one or more read and/or write operations, and the data stripe may be inconsistent during a critical section of a media-access sequence.

Abstract: Ransomware activity detection and data protection is implemented by a remote R2 storage array on an asynchronous remote data replication facility, on which data from a primary R1 storage array is replicated to the remote storage array. Write operations on storage volumes in a remote data replication group are collected in a capture cycle on the primary storage array, along with IO pattern metadata describing both read and write operations on the storage volumes. At the end of the capture cycle, the update and metadata is transmitted to the remote storage array. The remote storage array receives the update and metadata and temporarily stores the update prior to applying it to its copy of the storage volumes. Ransomware anomaly detection is implemented using the update and metadata, and if ransomware activity is detected, the data on the remote R2 storage array is protected, and the update is not applied.

Abstract: A write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. The write pattern of the host device is based on a number of I/O commands received from the host device and on a number of available memory blocks in the data storage device. If the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional I/O commands are received, the garbage collection process is initiated. An amount of valid data that is transferred from one memory location to another memory location during the garbage collection process is also dynamically determined. Thus, a garbage collection process may be tailored to a specific host device.