Abstract: The present disclosure is directed to an operating method of a memory controller, a memory controller, a memory system, and an electronic device. Herein, the operating method can include determining a backup region to be used in an idle state from a memory array, when detecting that remaining capacity of a currently used backup region for storing redundancy parity data in the memory array is less than a required capacity of redundancy parity data to be written, determining the quantity of all backup regions for storing redundancy parity data including the backup region to be used in the memory array, deciding whether the quantity is larger than a preset threshold, and erasing backup regions having stored redundancy parity data in the memory array when the quantity is larger than the preset threshold.

Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.

Abstract: One example method includes receiving, by a first computing entity from a second computing entity, a request for data, providing, by the first computing entity, a compliance API (Application Program Interface) to the second computing entity, receiving, by the first computing entity from the second computing entity, location information and/or data compliance information, by way of the compliance API, consulting, by the first computing entity, a mapping, and determining, based on information in the mapping and the location information and/or data compliance information, whether or not the data is permitted to be transmitted by the first computing entity to the second computing entity, and either transmitting the data to the second computing entity, or not transmitting the data to the second computing entity, based on data tags, the information in the mapping and the location information and/or data compliance information.

Abstract: One or more aspects of the present disclosure relate to performant destaging of write pending (WP) data to disk. In embodiments, an input/output (IO) workload is received at a storage array. Additionally, the IO workload can include an IO request with a random write request. Further, a write destage context for write-pending (WP) data corresponding to the random write request can be generated by a data services engine of the storage array. In addition, using the write destage context, a disk adapter (DA), at a backend of the storage array, is enabled to destage write-pending (WP) data without reading from a target write location of the random write request on a storage device on the storage array.

Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.

Abstract: Systems, apparatuses and methods may provide for technology that prefetches compressed data and a sparsity bitmap from a memory to store the compressed data in a decode buffer, where the compressed data is associated with a plurality of tensors, wherein the compressed data is in a compressed format. The technology aligns the compressed data with the sparsity bitmap to generate decoded data, and provides the decoded data to a plurality of processing elements.

Abstract: A method of synchronously executing input/output operations (IOs) for a plurality of applications using a storage device with a file system includes the steps of: receiving a first write IO including an instruction to write first data at a first address of the file system; determining that, within a first range of the file system comprising the first address, there are no pending unmap IOs for deallocating storage space of the storage device from files of the plurality of applications; after determining that there are no pending unmap IOs within the first range, locking the first range to prevent incoming unmap IOs from deallocating storage space within the first range from the files of the plurality of applications; after locking the first range, writing the first data to the storage device at the first address; and after writing the first data, unlocking the first range.

Abstract: Embodiments of this application are applicable to the field of terminal technologies, and provide a file storage location determining method and apparatus, and a terminal. The method includes: A first terminal determines a plurality of candidate paths corresponding to a target file. Each candidate path points to one file storage location. The first terminal obtains file information of the target file. The first terminal determines, based on the file information and the plurality of candidate paths, a file storage location pointed to by a first candidate path in the plurality of candidate paths as a storage location of the target file. A matching degree of the first candidate path is a highest matching degree in matching degrees of the plurality of candidate paths. According to the foregoing method, accuracy of determining the file storage location is improved.

Abstract: A differential logger stores, into a log storage from a device memory, a differential log being a log of a device value that has changed at each execution of a control program. A collective logger collectively stores, at a set time, collection target device values into the log storage as reference data to be used to collect the differential log. A split logger acquires as split logs, after the set time, logs of the device values multiple times, and stores the split logs into the reference data storage. The differential logger overwrites data in the log storage with the differential log after new reference data is stored into the log storage.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.

Abstract: One or more aspects of the present disclosure relate to relate to analyzing and mitigation storage array latency. In embodiments, an input/output (IO) workload is received by a storage array. Additionally, a latency corresponding to processing one or more IO requests of the IO workload is determined. For example, a factor corresponding to a significant portion of the latency is identified. Further, a remediation action is performed based on the factor identified.

Abstract: A system, method, and computer-readable medium for performing a data center monitoring and management operation, The data center monitoring and management operation includes receiving data center data for a data center, the data center data comprising data center memory associated data; receiving data center asset data for a plurality of data center assets, the data center asset data comprising data center asset memory associated data; providing the data center memory associated data and the data center asset memory associated data to a memory failure prediction model; and, training the memory failure prediction model using the data center memory associated data and the data center asset memory associated data.

Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Abstract: A memory system includes a memory area. A controller controls data. A first connector inputs the data and/or outputs the data, and is removable from the host. A first holding part is electrically disconnected from the memory area and the first connector and including a first port, and holds identification information used to authenticate an authority to initialize the memory area. The first port outputs the identification information to the host when receiving, from the host, an initialization command that instructs initialization of at least the part of the memory area. The controller includes a second port and an authentication part. The second port receives the initialization command from the host and receives the identification information via the first port. The authentication part executes initialization of at least the part of the memory area based on the initialization command and the identification information received at the second port.

Abstract: An image processing system capable of managing image data using a plurality of boxes, comprises a microphone that obtains a sound, an obtaining unit that obtains a user identifier based on voice information of a user obtained via the microphone, a specifying unit that specifies one box among the plurality of boxes based on specification information including at least the user identifier, and an informing unit that informs the user of information related to the specified one box.

Abstract: A direct-attached storage device software RAID crash dump system includes a chassis housing a software RAID subsystem coupled to physical storage devices, controller devices, and a hypervisor subsystem. The software RAID subsystem presents a primary controller device to the hypervisor subsystem as being connected to a logical storage device provided by the physical storage devices. When the software RAID subsystem receives a first crash dump command from the hypervisor subsystem directed to the primary controller device and identifying a crash dump logical storage subsystem in the logical storage device, it transmits a respective second crash dump command to each of a subset of the physical storage devices that provide the crash dump logical storage subsystem via a respective controller device that couple the software RAID subsystem to that physical storage device, confirms completion of the respective second crash dump commands, and transmits a crash dump confirmation to the hypervisor subsystem.

Abstract: Techniques are provided for creating secure IO (input/output) user connections between IO users and storage volumes. One method comprises establishing an IO user connection between a processor-based IO user and at least a portion of a storage volume on a storage array; obtaining IO user context information associated with the IO user connection, wherein the IO user context information comprises one or more keys for signature verification; and transmitting one or more IO operations over the IO user connection, wherein a signature associated with a given IO operation is evaluated to verify that the signature is a valid signature of one or more of the processor-based IO user and the storage array. The obtained IO user context information may further comprise an identifier of a signature generation function that generates the signature associated with the given IO operation and a connection identity string identifying the IO user connection.

Abstract: An object storage system, a migration control device, and a migration control method are provided. The migration control method includes observing a plurality of total target input/output (I/O) throughputs, inferring a plurality of reference I/O throughputs by using a first neural network, observing a plurality of target I/O throughputs with respect to an i-th storage device, determining a target object to be migrated and a target storage device, in which the target object will be stored, by using a second neural network, and generating a command instructing to migrate the target object to the target storage device.

Abstract: Systems, apparatus and methods are provided for determining an optimal performance profile and a predicted temperature. A method may include receiving a command from a host. The command may contain a logical block address (LBA) for data stored in a data storage system, a length for a data size associated with the command, and a timestamp associated with the command. The method may further include obtaining LBA information, the timestamp, the data size from the command, providing the LBA information, the timestamp, the data size, along with temperature readings, and a performance profile as inputs to a machine learning model, determining an optimal performance profile and a predicted temperature using the machine learning model and configuring a storage controller with settings of the optimal performance profile.

Abstract: A method for erasing data stored from memory of a network device comprises erasing stored data from the memory of the network device and requesting data from the memory of the network device after completion of the data erasure procedure or accessing the memory of the network device after completion of the data erasure procedure. The method further comprises determining the outcome of the data erasure procedure based at least in part on: the results of a comparison between a response received from the network device and an expected response which indicates a successful erasure of the memory of the network device; or a comparison between any contents of the memory of the network device after completion of the data erasure procedure and expected contents of the memory after the data erasure procedure which are indicative of a successful erasure of the memory of the network device.

Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. Based on embodiments of the disclosed technology, the memory system may suspend a target operation, which is a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. Accordingly, the memory system is capable of preventing a problem in that the end time of a program operation or an erase operation is excessively delayed, and controlling the number of times a program operation or an erase operation is suspended.

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

Abstract: A technique of managing the rate of I/O (Input/Output) request processing includes a token-bucket arrangement having first, second, and third token buckets. The first token bucket is provided with sufficient tokens to accommodate an expected baseline level of I/O requests, whereas the second token bucket is provided with sufficient tokens to accommodate an expected excess level of I/O requests during bursts. The third token bucket is provided with tokens at predefined intervals and limits a total amount of bursting available during those intervals.

Abstract: A system includes a logic that generates a reduced-precision primary data object and an associated residual data object for each of a plurality of uncompressed data objects. The logic classifies the at least some of the generated residual data objects for removal based on data integrity rules and determines that removal of others of the generated residual data objects violates the data integrity rules. The logic removes the at least some of the generated residual data objects classified for removal and applies a corresponding adjustment to at least one of the generated residual data objects.

Abstract: Disclosed are a method and a system for data uploading, which belongs to the technical field of blockchain. The method comprises: receiving a block upload request sent by a slave server of a target node; determining whether block data corresponding to the block upload request has been uploaded to a block data storage system; if the block data corresponding to the block upload request is not uploaded to the block data storage system, acquiring the block data if the block data corresponding to the block upload request is not uploaded to the block data storage system, and uploading the block data to a storage space of the block data storage system; and sending an uploading success instruction to the slave server if the uploading is successful, so as to instruct the slave server to delete the block data stored on a light-weight peer in the target node.

Abstract: A memory system includes a plurality of memory cells each storing a first bit and a second bit and a control circuit. The control circuit is reads out first data, first partial data, and second partial data, each corresponding to the first bit, from the plurality of memory cells, read out second data, third partial data, and fourth partial data, each corresponding to the second bit, from the plurality of memory cells, generate first compressed data based on an OR operation of the first partial data and the third partial data, generate second compressed data based on an OR operation of the second partial data and the fourth partial data, and transmit the first data, the second data, the first compressed data, and the second compressed data to an external memory controller.

Abstract: Disclosed is an operation method of a storage device which includes setting a first threshold value for a first host and a second threshold value for a second host under control of a hypervisor, sequentially fetching host commands from the first and second hosts, storing the fetched host commands in an internal command queue, stopping fetching a host command from the first host when the number of first host commands fetched from the first host from among the host commands stored in the internal command queue reaches the first threshold value, and stopping fetching a host command from the second host when the number of second host commands fetched from the second host from among the host commands stored in the internal command queue reaches the second threshold value.

Abstract: A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

Abstract: A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and having a set of memory ports. The memory system includes a first processor port, a second processor port, and one or more DIMM interface ports to be coupled to respective processors for providing access to the set of memory modules. In another embodiment, an artificial intelligence (AI) computing system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and an arithmetic function block performing multiply and accumulate functionalities using data stored in the memory modules. The set of memory modules are accessed to perform read, write and erase memory operations in a rotating manner in each computing cycle.

Abstract: The disclosure provides an approach for secure offloaded data transfer. Embodiments include receiving, by a security component on a client device, from a storage system connected to the client device, a token associated with a data read request corresponding to a source file on the storage system. Embodiments include determining, by the security component, that the source file is trusted. Embodiments include generating, by the security component, an entry in a trusted token cache based on determining that the source file is trusted, wherein the entry comprises the token. Embodiments include receiving, by the security component, a write request corresponding to a destination file on the storage system, wherein the write request comprises the token or a different token. Embodiments include determining, by the security component, based on the trusted token cache, whether to perform one or more operations related to the write request.

Abstract: A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.

Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

Abstract: A memory system includes a first memory, a second memory, and a controller. The controller is configured to store address mapping information in the first memory, store, in the second memory, a mapping update data that is generated each time data writing to the first memory is performed, and upon an amount of mapping update data that have not been transmitted to the host reaching a threshold, transmit the address mapping information in the first memory and the mapping update data in the second memory to the host and cause the host to store updated address mapping information in a third memory in the host. The controller is configured to perform address mapping using the address mapping information in the first memory and the mapping update data in the second memory when connection with the host is lost.

Abstract: System and method for de-centralized handling of high risk actions across coordinated systems. A monitoring system is used as an action advisor for performing the high risk actions at nodes across coordinated systems. The monitoring system advises performing the actions based on one or more monitoring signals corresponding to the coordinated systems. The process for performing the high risk actions is de-centralized. A metadata substrate system acts as a message broker between the monitoring system and coordinated systems.

Abstract: Aspects of a storage device for providing superior sustained sequential write (SSW) performance are disclosed. A controller on the storage device allocates buffer space in the host memory buffers (HMBs) on the host device for storage of relocation data, i.e., data to be folded or compacted. The controller or a hardware element therein can therefore allocate local SRAM (including TRAM) for use in accommodating incoming host writes. The increased SRAM allocation of relocation data without an attendant increase in cost or size to the storage device enables the storage device to perform operations in parallel and substantially increase SSW performance metrics.

Abstract: Logical address slices and corresponding metadata pages of mapping information can be partitioned into sets. Each node can be assigned exclusive ownership of one of the sets. In at least one embodiment, for a read I/O which is received at a first node and directed to a logical address LA1 that is owned by a second node, the first node can request that the second owning node perform resolution processing for LA1. The second node can own both LA1 and corresponding metadata pages included in mapping information used to map LA1 to a corresponding physical location PA1 including content C1 stored at LA1. The second node can perform resolution processing for LA1 using the metadata pages corresponding to LA1 to either read and return C1 to the first node, or obtain and return PA1 to the first node where the first node can then read C1 directly using PA1.

Abstract: A request can be provided, from a front-end of a memory sub-system, to a processing device of the memory sub-system and deleting the request from a buffer of the front-end of the memory sub-system. Responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer and responsive to deleting the requests from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system. Responsive to deleting the request from the buffer and providing the request to the processing device, determining whether to provide a response to a host, wherein the response includes an indication of the quantity of requests in the buffer and of outstanding requests in a back-end of the memory sub-system, based on a comparison of the second quantity of outstanding requests to a threshold.

Abstract: An electronic device includes an external device configured to determine a first performance index on the basis of at least one of a power level and a temperature signal, to put the first performance index into a command, and to output the command. The electronic device also includes a storage component including a plurality of memory dies. The electronic device further includes a memory controller configured to provide the temperature signal to the external device at a set transmission period, and to control the storage component to process the command by simultaneously operating the number of memory dies corresponding to the first performance index as the command is received.

Abstract: Memory systems and methods of operating the memory systems are disclosed. A memory system including a plurality of data storage zones may comprise a memory device including a plurality of zones for storing data, and a memory controller configured to control the memory device in performing a write operation in the memory device. The memory controller is configured to, upon performing a write operation corresponding to a write request received from a host, update a logical write pointer and a physical write pointer associated with a zone that is targeted to perform the write operation corresponding to the write request received from the host, and upon performing a write operation corresponding an internal write command internally issued by the memory controller, update a physical write pointer associated with the zone that is targeted to perform the write operation corresponding to an internal write command issued by the memory controller.

Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

Abstract: A method for improving message storage efficiency of a network chip, a device, and a storage medium are provided. The method comprises: configuring a data memory, dividing the data memory into N small RAMs, and managing respective RAMs by means of a link list; in a case where a write data request is received on any input interface, parsing and acquiring a channel number corresponding to the input interface, accessing a channel write state memory according to the channel number to acquire channel write state information, in a case of determining, according to the channel write state information, that at least one RAM is null, writing data into the data memory; and in a case where a read-out scheduling request is received on any channel, recombining data according to memory information in a link list memory and reading the recombined data out.

Abstract: Methods, systems, and devices for techniques to season memory cells are described. A memory device may receive a command to season the memory device from a device configured to season the memory device or from a host device. Based on receiving the command, the memory device may identify a quantity of cycles to season the memory device based on receiving the command. In one case, the memory device may identify the quantity of cycles based on the command including an indication of the quantity of cycles used to season the memory device. In another case, the memory device may identify the quantity of cycles based on the command including one or more parameters associated with operating the memory device. In either case, the memory device may execute the quantity of cycles and indicate a completion of seasoning the memory device based on executing the quantity of cycles.

Abstract: According to one embodiment, in a semiconductor device, a first chip is electrically connected to a terminal to which a signal from a host is input. The first chip is electrically connected to a second chip and to a third chip in parallel with the second chip. The first chip includes a first buffer memory and a second buffer memory. The first buffer memory corresponds to the second chip. The second buffer memory corresponds to the third chip. The second chip includes a third buffer memory. The third chip includes a fourth buffer memory. A capacity of the first buffer memory is equal to or larger than a capacity of the third buffer memory. A capacity of the second buffer memory is equal to or larger than a capacity of the fourth buffer memory.

Abstract: According to one embodiment, a controller manages a first set of blocks and a second set of blocks. The controller allocates a second block included in the second set of blocks to a first block included in the first set of blocks. In response to receiving one or more write command specifying the first block, the controller writes data associated with the one or more received write commands to the second block in units of a second minimum write size. When the first block is filled with data that has been written to the first block and unwritten region remains in the second block, the controller deallocates the second block from the first block, and allocates the deallocated second block to a write destination block other than the first block.

Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

Abstract: Various embodiments provide an electronic device and method for determining the lifespan and failure of a nonvolatile memory storage device. The electronic device and the method according to various embodiments may be configured to determine whether the storage device has failed in response to a connection with the storage device, output a guidance message for replacing the storage device when the storage device fails, confirm whether the storage device has a function of autonomously identifying its state when the storage device is normal, check the lifespan of the storage device based on state information received from the storage device when the storage device has the function, estimate the lifespan of the storage device when the storage device does not have the function, and output the guidance message for replacing the storage device based on the lifespan.