Control Technique Patents (Class 711/154)
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Patent number: 11928041Abstract: Embodiments of a system for determining a data gravity index score and implementing pervasive data center architecture is disclosed. In some embodiments, the system can calculate a data gravity index score based on the amount of data stored in a given location, an amount of data in motion in the given location, a bandwidth index associated with the given location, and a latency index associated with the given location. Based on data gravity index scores, in some embodiments, the system can localize traffic to improve network performance, improve security operations, and generate software-defined-network overlay.Type: GrantFiled: March 17, 2023Date of Patent: March 12, 2024Assignee: Digital Realty Trust, Inc.Inventors: Dave Dennis McCrory, Anthony Bennett Bishop
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Patent number: 11921628Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignees: SK hynix Inc., Korea Advanced Institute of Science and TechnologyInventors: Junhyeok Jang, Seungkwan Kang, Dongsuk Oh, Myoungsoo Jung
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Patent number: 11922200Abstract: A virtual network comprising virtual machines executing at a computing environment remote from the virtualized computing service provider is implemented. A control plane management functions is configured to provide and implement the virtual machines of the virtual network and executed at the virtualized computing service provider. Data plane management functions are configured to manage data traffic to and from the virtual machines of the virtual network and executed at the remote computing environment. A secure network connection between the virtualized computing service provider and the remote computing environment is established. The control plane management functions cause instantiation of the virtual machines of the virtual network at the remote computing environment. Using the control plane management functions executing at the virtualized computing service provider, operation of the virtual machines of the virtual network is managed.Type: GrantFiled: April 20, 2020Date of Patent: March 5, 2024Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Deepak Bansal, Qi Zhang
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Patent number: 11922037Abstract: A storage device includes a plurality of nonvolatile memories, each including a plurality of memory blocks and a controller configured to control the plurality of nonvolatile memories, in which the controller is configured to buffer data chunks received along with write commands from a host, is configured to determine a size of continuous data based on a start logical address and a chunk size of the data chunks, is configured to determine a striping number indicating a number of nonvolatile memory which is for distributing and storing the data chunks in sub-page units based on the size of continuous data, and is configured to provide the data chunks to one or more nonvolatile memories selected from among the plurality of nonvolatile memories based on the determined striping number and the one or more selected nonvolatile memories are configured to perform a programming operation on the data chunks in parallel.Type: GrantFiled: July 18, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hyungkyun Byun, Seongcheol Hong
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Patent number: 11922029Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.Type: GrantFiled: July 12, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Roy Chowdhury, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Ugo Russo
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Patent number: 11922013Abstract: A method for contention reduced update of one or more storage system parameters, the method may include (i) concurrently monitoring the one or more storage system parameters (SSPs) by compute entities (CEs); wherein the concurrently monitoring comprises updating, by the CEs, local counters allocated to different SSPs; (ii) updating, by the CEs, sets of shared counter fields with values of the local counters, wherein different sets are allocated to different SSPs; wherein an updating of a set of a shared counter fields by an CE comprises selecting a shared counter field of the set by the CE; and (iii) calculating values of the different SSPs, wherein a calculating of a value of a SSP is based on at least one value of at least one shared counter field of a set that is allocated to the SSP.Type: GrantFiled: April 14, 2022Date of Patent: March 5, 2024Assignee: VAST DATA LTD.Inventors: Amir Miron, Avi Goren
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Patent number: 11915741Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.Type: GrantFiled: February 3, 2023Date of Patent: February 27, 2024Inventor: Richard C. Murphy
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Patent number: 11914890Abstract: A memory sub-system to, in response to a power up, executing a first loading process to load a sequence of a set of trim values into one or more registers of the memory sub-system. In response to a request to execute a memory access operation, interrupting the first loading process. A second loading process including loading a portion of the set of trim values corresponding to the request is executed. The memory access operation is executed using the portion of the set of trim values loaded into the one or more registers during the second loading process. Following execution of the memory access operation, the first loading process is resumed to load one or more unloaded trim values of the sequence of trim values.Type: GrantFiled: February 13, 2023Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Steven Michael Kientz, Vamsi Pavan Rayaprolu
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Patent number: 11914472Abstract: An information handling system includes a memory module, a memory controller coupled to the memory controller by a memory bus, and an expansion memory device coupled to the memory controller by a data communication interface. The memory controller receives user data, calculates error correction code (ECC) data for the user data, determines metadata related to the user data, writes the user data and the ECC data to the memory module via the memory bus, and stores the metadata to the expansion memory device with a transaction on the data communication interface.Type: GrantFiled: July 13, 2022Date of Patent: February 27, 2024Assignee: Dell Products L.P.Inventors: Kevin Matthew Cross, Jordan Chin
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Patent number: 11914875Abstract: An apparatus comprises a processing device configured to identify storage workloads to be run on a storage system, and to determine a mix of input/output (TO) patterns associated with the identified storage workloads, the mix of IO patterns comprising a first set of IO patterns characterizing types of IO operations performed by a first storage workload and at least a second set of IO patterns characterizing types of IO operations performed by a second storage workload. The processing device is also configured to calculate an affinity metric for the mix of IO patterns, the calculated affinity metric characterizing a difference between (i) performance metrics for the mix of IO patterns running concurrently and (ii) the first and second sets of IO patterns running individually. The processing device is further configured to allocate the identified storage workloads to storage devices of the storage system based on the calculated affinity metric.Type: GrantFiled: July 8, 2022Date of Patent: February 27, 2024Assignee: Dell Products L.P.Inventors: Chi Chen, Hailan Dong, Huijuan Fan
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Patent number: 11908253Abstract: A computing system with a data store including storage priorities each associated with a different predefined event type. The storage priority indicating a likelihood detection of the predefined event type by an autonomous vehicle causes the autonomous vehicle to store sensor system output from a sensor system in the autonomous vehicle. The computing system can receive a data storage request indicating a request for the autonomous vehicle to store sensor system output for a specific predefined event type. The computing system can further update the storage priorities. Updating the storage priorities includes updates a storage priority associated with the specific predefined event type based on a parameter of specific predefined event type. The computing yet further can transmit the updated storage priorities to the autonomous vehicle which causes the autonomous vehicle to change the amount of sensory system output stored by the autonomous vehicle.Type: GrantFiled: December 12, 2018Date of Patent: February 20, 2024Assignee: GM CRUISE HOLDINGS LLCInventors: Audrey Lawrence, Sam McCabe
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Patent number: 11893278Abstract: A memory controller includes a first buffer configured to receive a first memory request from a host and store the first memory request, a request scheduler configured to determine an order in which the first memory request is transferred to a command generator, a request generator configured to generate one or more second memory requests based on a generation parameter of the first memory request, in response to an address of the first memory request corresponding to a processing in memory (PIM) memory, the command generator configured to generate a first command corresponding to the first memory request and one or more second commands corresponding to the one or more second memory requests, and store the generated first command and the one or more second commands in a second buffer, and a command scheduler configured to schedule the first command and the one or more second commands.Type: GrantFiled: August 23, 2021Date of Patent: February 6, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seungwoo Seo, Seungwon Lee
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Patent number: 11886749Abstract: Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.Type: GrantFiled: December 27, 2022Date of Patent: January 30, 2024Inventors: Federica Cresci, Nicola Del Gatto, Massimiliano Turconi, Massimiliano Patriarca
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Patent number: 11886737Abstract: A memory device can include a plurality of memory cells for storing data, a memory interface configured to store and retrieve data at the plurality of memory cells, a logic unit comprising digital circuitry configured to perform mathematic and logic operations, and a control circuitry configured to control operation of the memory device.Type: GrantFiled: November 30, 2021Date of Patent: January 30, 2024Assignee: Infineon Technologies AGInventor: Prakash Balasubramanian
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Patent number: 11880591Abstract: Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.Type: GrantFiled: November 17, 2022Date of Patent: January 23, 2024Inventor: M. Ataul Karim
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Patent number: 11880601Abstract: A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.Type: GrantFiled: October 28, 2021Date of Patent: January 23, 2024Assignee: SK HYNIX INC.Inventors: Jae Hyeong Jeong, Dae Sung Kim, Sung Ho Ahn
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Patent number: 11875056Abstract: A controller is provided. The controller includes a write queue configured to store commands for operating a memory device that are generated based on requests received from a host, zone identifications of the commands each indicating a memory region in the memory device to store data corresponding to a command, and write pointers of the commands each indicating an order that the requests are output from the host; and a queue controller configured to receive the commands, the zone identifications, and the write pointers from the write queue, store the commands in buffers allocated the zone identifications based on the write pointers, respectively, and based on an occurrence of an event that a number of commands stored in a buffer among the buffers reaches a preset number set in the buffer, output commands stored in the buffer.Type: GrantFiled: June 30, 2021Date of Patent: January 16, 2024Assignee: SK HYNIX INC.Inventor: Jong Tack Jung
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Patent number: 11875061Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.Type: GrantFiled: April 22, 2022Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventors: Daniel J. Hubbard, Roy Leonard
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Patent number: 11868661Abstract: An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses. The counters are configured to count activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; For example, in response to an activation command applied to a row address having first sub-addresses, counts stored in a portion of the counters corresponding to the first sub-addresses are increased for the count of the activation command. For each respective segment, counts stored in counters for sub-addresses in the respective segment are used to determine whether at least one of the sub-addresses has seen more activation commands than a threshold. An alert is generated for risk mitigation operations in response to each segment having at least one sub-address that has seen more activation commands than the threshold.Type: GrantFiled: May 17, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventor: Kai Wang
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Patent number: 11868283Abstract: The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.Type: GrantFiled: July 17, 2020Date of Patent: January 9, 2024Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Valeria Bertacco, Abraham Addisie
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Patent number: 11863202Abstract: Disclosed are devices, systems and methods for polar coding and decoding for correcting deletion and insertion errors caused by a communication channel. One exemplary method for error correction includes receiving a portion of a block of polar-coded symbols that includes d?2 insertion or deletion symbol errors, the block comprising N symbols, the received portion of the block comprising M symbols; estimating, based on one or more recursive calculations in a successive cancellation decoder (SCD), a location or a value corresponding to each of the d errors; and decoding, based on estimated locations or values, the portion of the block of polar-coded symbols to generate an estimate of information bits that correspond to the block of polar-coded symbols, wherein the SCD comprises at least log2(N)+1 layers, each comprising up to d2N processing nodes arranged as N groups, each of the N groups comprising up to d2 processing nodes.Type: GrantFiled: July 22, 2021Date of Patent: January 2, 2024Assignee: The Regents of the University of CaliforniaInventors: Kuangda Tian, Arman Fazeli Chaghooshi, Alexander Vardy
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Patent number: 11861207Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.Type: GrantFiled: December 27, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Chandra M. Guda, Suresh Rajgopal
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Patent number: 11853606Abstract: The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.Type: GrantFiled: October 1, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Paolo Amato
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Patent number: 11853223Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.Type: GrantFiled: November 17, 2021Date of Patent: December 26, 2023Assignee: Google LLCInventors: Vinod Chamarty, Joao Dias
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Patent number: 11847345Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.Type: GrantFiled: June 28, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sanjeev Kumar Jain, Cormac Michael O'Connell
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Patent number: 11847051Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.Type: GrantFiled: July 11, 2022Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Vamsi Pavan Rayaprolu, Karl D. Schuh, Jiangang Wu, Gil Golov
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Patent number: 11847326Abstract: A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storage operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.Type: GrantFiled: April 27, 2022Date of Patent: December 19, 2023Assignee: Dell Products L.P.Inventors: Girish Desai, Frederick K. H. Lee
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Patent number: 11847323Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: June 7, 2022Date of Patent: December 19, 2023Assignee: Westem Digital Technologies, Inc.Inventors: Amir Segev, Shay Benisty
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Patent number: 11842048Abstract: An apparatus includes a processor, a memory communicatively coupled to the processor, an acceleration framework circuit communicatively coupled to the memory and the processor, and a device driver. The device driver is configured to receive a request for data manipulation by a software defined storage (SDS) application. The device driver is configured to determine whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit. The device driver is configured to, based upon the determination of whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit, selectively cause the request to be executed by the acceleration framework circuit or the SDS application through execution on the processor.Type: GrantFiled: October 20, 2021Date of Patent: December 12, 2023Assignee: SOFTIRON LIMITEDInventors: Lionel Corbet, Phillip Edward Straw, Steve Hardwick, Harry Richardson
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Patent number: 11842078Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.Type: GrantFiled: January 31, 2022Date of Patent: December 12, 2023Assignee: Micron Technology, Inc.Inventors: Andrea Giovanni Xotta, Guido Luciano Rizzo, Umberto Siciliani, Tommaso Vali, Luca De Santis, Walter Di Francesco
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Patent number: 11836355Abstract: A method may include, in an operating system of an information handling system: responsive to a determination that a storage resource of the information handling system is experiencing a predictor of a failure of the storage resource, issuing a command to the storage resource to reload firmware code of the storage resource; responsive to the storage resource reloading the firmware code and reset of the storage resource following reloading of the firmware code, determining whether the predictor persists; and responsive to determining whether the predictor persists, performing a responsive action.Type: GrantFiled: November 21, 2021Date of Patent: December 5, 2023Assignee: Dell Products L.P.Inventors: Donald Mace, Xiaoye Jiang, Arieh Don
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Patent number: 11836356Abstract: An information handling system may include at least one processor; a network interface; and a physical storage resource including a flash translation layer (FTL) operable to provide a mapping between logical storage addresses and physical storage addresses. The information handling system may be configured to: receive a request for a snapshot; for used portions of the physical storage resource, change a metadata identifier from a used status to a snapshot status; prevent deletion of those portions associated with the snapshot status; and transmit, via the network interface, information associated with the portions that are associated with the snapshot status.Type: GrantFiled: January 14, 2022Date of Patent: December 5, 2023Assignee: Dell Products L.P.Inventors: Zhang Flag, Zheng Zhang, Zhuo Zhang, YungChin Fang
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Patent number: 11836364Abstract: A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.Type: GrantFiled: December 12, 2022Date of Patent: December 5, 2023Assignee: Oracle International CorporationInventors: Tao Mao, Yanfei Fan
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Patent number: 11829651Abstract: Methods, computer program products, computer systems, and the like for efficient metadata management are disclosed, which can include determining whether a change in a status of data has occurred. In response to a determination that the change has occurred, such methods, computer program products, and computer systems can include determining whether a move condition has been met, and, in response to a determination that the move condition has been met, moving the metadata from the first storage unit to a second storage unit.Type: GrantFiled: January 23, 2023Date of Patent: November 28, 2023Assignee: VERITAS TECHNOLOGIES LLCInventors: Jialun Liu, Xianbo Zhang, Weibao Wu
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Patent number: 11830541Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.Type: GrantFiled: January 6, 2022Date of Patent: November 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daero Kim, Kyunghoi Koo, Sujeong Kim, Juyoung Kim, Sanghune Park, Jiyeon Park, Jihun Oh, Kyoungwon Lee
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Patent number: 11829621Abstract: Disclosed herein are system, method, and computer program product aspects for managing a storage system. In an aspect, a host device may generate a configuration corresponding to a file and transmit the configuration to a memory device, such as 3D NAND memory. The configuration instructs the memory device to refrain from transmitting a logic-to-physical (L2P) dirty entry notification to the host device. The L2P dirty entry notification corresponds to the file. The host device may also generate a second configuration corresponding to the file and transmit the second configuration to the memory device. The second configuration instructs the memory device to resume transmitting the L2P dirty entry notification corresponding to the file to the host device.Type: GrantFiled: May 4, 2021Date of Patent: November 28, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Kaiyao Cao, Yaping Zhang, Xiuli Sun
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Patent number: 11822663Abstract: Systems and methods for verifying firmware before it is loaded to a memory device are presented herein. An amount of available memory remaining in a memory device after firmware is written to the memory device is determined, and padding data having a size equal to the determined amount of remaining available memory is generated and appended to the firmware (e.g., the firmware is padded with the padding data). In this way, there is no room for malicious code or a malicious version of the firmware in the memory device. A processing device may determine a verification value of the padded firmware and store the verification value. The verification value may be a cryptographic hash of the padded firmware or a cryptographic signature of the padded firmware. The padded firmware is then written to the memory device. The firmware may be read from the memory device and verified using the verification value.Type: GrantFiled: November 30, 2020Date of Patent: November 21, 2023Assignee: Red Hat, Inc.Inventors: Michael Tsirkin, Amnon Ilan
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Patent number: 11822804Abstract: The present disclosure is related to methods, systems, and machine-readable media for managing extent sharing between snapshots using mapping addresses. A first mapping address can be assigned to a first extent responsive to a request to write the first extent. A second mapping address can be assigned to a second extent responsive to a request to write the second extent. A snapshot can be created. A snapshot mapping address, that is monotonically increased from the second mapping address, can be assigned to the snapshot. A third mapping address, that is monotonically increased from the second mapping address, can be assigned to a third extent of the snapshot responsive to a request to write the third extent.Type: GrantFiled: October 4, 2021Date of Patent: November 21, 2023Assignee: VMware, Inc.Inventors: Wenguang Wang, Enning Xiang, Pranay Singh, Subhradyuti Sarkar
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Patent number: 11817169Abstract: A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.Type: GrantFiled: November 22, 2021Date of Patent: November 14, 2023Assignee: SK hynix Inc.Inventors: Munseon Jang, Hoiju Chung, Jang Ryul Kim
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Patent number: 11816336Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.Type: GrantFiled: December 19, 2022Date of Patent: November 14, 2023Assignee: HITACHI, LTD.Inventors: Naoya Okada, Takashi Nagao, Kentaro Shimada, Ryosuke Tatsumi, Sadahiro Sugimoto
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Patent number: 11809314Abstract: A method and apparatus for performing access control of a memory device with aid of multi-stage garbage collection (GC) management are provided. The method includes: during a first GC stage, sending a first simple read command to the NV memory in order to try reading first valid data from a first source block, sending the first valid data into an internal buffer of the NV memory, for being programed into a first destination block, sending a second simple read command to the NV memory in order to try reading second valid data from the first source block, and in response to reading the second valid data from the first source block being unsuccessful, preventing retrying reading the second valid data from the first source block; completing at least one host-triggered operation; and during a second GC stage, retrying reading the second valid data from the first source block.Type: GrantFiled: November 21, 2021Date of Patent: November 7, 2023Assignee: Silicon Motion, Inc.Inventor: Tsung-Chieh Yang
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Patent number: 11803479Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.Type: GrantFiled: November 17, 2021Date of Patent: October 31, 2023Assignee: Google LLCInventors: Vinod Chamarty, Joao Dias
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Patent number: 11797224Abstract: Solid State Drive devices with hardware accelerators and methods for apportioning storage resources with tokens in the SSD are disclosed. SSDs typically comprise an array of non-volatile memory devices and a controller which manages access to the memory devices. The controller may also comprise one or more accelerators to either improve the performance of the SSD itself or to offload specialized computation workloads of a host-computing device. Different accelerators may be dynamically assigned portions of the non-volatile memory array according to the type of data being accessed and/or the throughput required. Provision is also made for the data to be accessed directly by the accelerators bypassing the controller. The accelerators may also share data bus bandwidth and resources with each other or the storage device controller. To minimize conflicts and improve the storage device performance, a system of tokens for both cache memory and bus bandwidth is used to dynamically assign these resources.Type: GrantFiled: February 15, 2022Date of Patent: October 24, 2023Assignee: Western Digital Technologies, Inc.Inventor: Ramanathan Muthiah
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Patent number: 11797183Abstract: Systems and methods are disclosed for providing utilization of device resources based on host assisted grouping of applications. In certain embodiments, a data storage device includes a non-volatile memory, a volatile memory, and a controller configured to: receive application group information associated with applications from a host, wherein the application group information indicates corresponding application groups for the applications on the host; receive a plurality of write requests associated with a plurality of applications from the host, wherein the plurality of applications is included in the same application group; write data for each write request of the plurality of write requests in parallel across a plurality of channels associated with a plurality of dies in the non-volatile memory such that the data for the plurality of write requests share a parity buffer; and generate parity data for the data for the plurality of write requests.Type: GrantFiled: June 27, 2022Date of Patent: October 24, 2023Assignee: Western Digital Technologies, Inc.Inventors: Dinesh Kumar Agarwal, Amit Sharma
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Patent number: 11789656Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.Type: GrantFiled: October 5, 2021Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventor: Hiroshi Maejima
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Patent number: 11782841Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.Type: GrantFiled: March 2, 2022Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Sanjay Subbarao, James Fitzpatrick
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Patent number: 11785084Abstract: Methods and systems for a networked storage system is provided. One method includes transforming by a processor, performance parameters associated with storage volumes of a storage system for representing each storage volume as a data point in a parametric space; generating by the processor, a plurality of bins in the parametric space using the transformed performance parameters; adjusting by the processor, bin boundaries for the plurality of bins for defining a plurality of service levels for the storage system based on the performance parameters; and using the defined plurality of service levels for operating the storage system.Type: GrantFiled: November 16, 2018Date of Patent: October 10, 2023Assignee: NETAPP, INC.Inventors: Jayanta Basak, Ameet Deulgaonkar, Siddhartha Nandi
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Patent number: 11782606Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.Type: GrantFiled: April 27, 2022Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Wei Wang, Jiangli Zhu, Ying Yu Tai
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Patent number: 11775172Abstract: Provided is a genome data compression method of compressing FASTQ-formatted genome data, the method including: storing, by a first core that is one of the M cores, fixed header data in the first line of the first piece of sequence data in a compression result storage; and allocating, by the first core, N (N is a natural number of 2 or greater) pieces of the sequence data to each of the other M-1 (M is a natural number of 4 or greater) cores (hereinafter, referred to as “the remaining cores”), and performing compression by each of the remaining cores to compress N*(M-1) pieces of the sequence data together in parallel processing, and storing a compression result in the compression result storage, wherein the compression performed by each of the remaining cores is performed, including: primary compression in which for the N pieces of the sequence data, a process of the following stages for each piece of the sequence data is repeated: a stage in which a fixed header in the first line is removed; a stage in whichType: GrantFiled: May 5, 2022Date of Patent: October 3, 2023Assignee: CELLGENTEK CORP.Inventors: Hoi Yul Kim, Dong Woo Kim, Sung Ryul Oh, Young-Joon Kim, Jin-Young Lee
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Patent number: 11768783Abstract: A server system is provided that includes one or more compute nodes that include at least one processor and a host memory device. The server system further includes a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device is configured to virtualize hardware resources of the plurality of SSD devices. The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node.Type: GrantFiled: May 23, 2022Date of Patent: September 26, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Vadim Makhervaks, Aaron William Ogus, Jason David Adrian