Control Technique Patents (Class 711/154)
  • Patent number: 12260123
    Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: March 25, 2025
    Assignee: Silicon Motion, Inc.
    Inventor: Fahao Li
  • Patent number: 12260085
    Abstract: A write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. The write pattern of the host device is based on a number of I/O commands received from the host device and on a number of available memory blocks in the data storage device. If the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional I/O commands are received, the garbage collection process is initiated. An amount of valid data that is transferred from one memory location to another memory location during the garbage collection process is also dynamically determined. Thus, a garbage collection process may be tailored to a specific host device.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 25, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Anamika Choudhary, Disha Sharma
  • Patent number: 12254198
    Abstract: According to one embodiment, a memory system includes a non-volatile memory including a plurality of physical blocks and a controller. The controller is configured to allocate the plurality of physical blocks to a plurality of first block sets each including physical blocks among the plurality of physical blocks, generate a plurality of groups obtained by grouping the plurality of first block sets by the number of defective physical blocks included in each of the plurality of first block sets, and select a plurality of the first block sets from at least two groups of the plurality of groups to generate a second block set from the plurality of selected first block sets.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 18, 2025
    Assignee: Kioxia Corporation
    Inventor: Tetsuya Yasuda
  • Patent number: 12253990
    Abstract: A method, apparatus, and computer program product for tier-specific data compression, comprising comparing costs associated with a plurality of storage configurations for storing data based on one or more usage characteristics of data, wherein each storage configuration of the plurality of storage configurations corresponds to a particular storage tier of a plurality of storage tiers and a particular compression algorithm of a plurality of compression algorithms and based on the comparison of the costs, storing the data using a storage configuration of the plurality of storage configurations.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: March 18, 2025
    Assignee: PURE STORAGE, INC.
    Inventors: Richard V. Tran, Xiyan Liu, Abhinav Chakravarty, Joern Engel
  • Patent number: 12253940
    Abstract: A data storage device and method for host-determined proactive block clearance are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a command from a host that specifies a parameter of an upcoming burst mode; and in response to receiving the command, proactively perform a garbage collection operation according to the parameter to create available storage space in the memory to store data from the host during the upcoming burst mode. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: March 18, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ronak Jain, Rohit Prasad, Ramanathan Muthiah
  • Patent number: 12254219
    Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 18, 2025
    Assignee: SILICON MOTION, INC.
    Inventors: Hsu-Ping Ou, Kuang-Ting Tai
  • Patent number: 12254217
    Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Johnathan Alsop, Shaizeen Dilawarhusen Aga
  • Patent number: 12253942
    Abstract: In certain aspects, the memory controller includes a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a controller processor configured to control a memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by replacing original logical addresses of logical block address (LBA) segments of the file with new continuous logical addresses of a merged LBA segment of the file, and changing an original mapping relation between the original logical addresses of the LBA segment of the file and physical addresses of the file, to a new mapping relation between the new continuous logical addresses of the merged LBA segment of the file and the physical addresses of the file.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: March 18, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Mo Cheng
  • Patent number: 12253952
    Abstract: Various embodiments include systems, methods, and non-transitory computer-readable media for managing data using persistent storage. Consistent with these embodiments, a method includes receiving a write request that includes a value and a key; processing the write request, the processing of the write request including generating a message that includes the value; transmitting the message to an external system for storage of the value; generating an index based on a mapping of the key to an offset; and storing the value and the index in a local persistent storage.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: March 18, 2025
    Assignee: Twilio Inc.
    Inventors: Christopher O'Hara, Achille Roussel
  • Patent number: 12248408
    Abstract: When having detected that key data set to an accelerator by command information is not key data permitted to use, a monitor unit issues, to a storage control unit, a suspension request for suspending processing related to writing of data, a compute unit having received an instruction from an application program reads data from the storage device, encrypts read data using the accelerator, and issues, to the storage control unit, an instruction to write encrypted data to the storage device, and when having received the suspension request, the storage control unit suspends processing related to writing of data to the storage device.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: March 11, 2025
    Assignee: HITACHI VANTARA, LTD.
    Inventors: Tatsuya Hirai, Hideo Saito
  • Patent number: 12248676
    Abstract: A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: March 11, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Michael Ionin, Alexander Bazarsky, Itay Busnach, Noga Deshe, Judah Gamliel Hahn
  • Patent number: 12248386
    Abstract: Systems and techniques for application profiling to resize and reconfigure compute instances are generally described. In some examples, a first application executing in a user space of a first compute instance may be determined. A Berkeley Packet Filter (BPF) process may be executed in the user space of the first compute instance. The BPF process monitors resource consumption of a first resource of the first compute instance. First consumption data for the first resource may be determined. The first consumption data may be associated with a first process of the first application over a first period of time. The first consumption data may be evaluated using first criteria. A configuration of a second compute instance may be determined based on evaluation of the first consumption data using the first criteria. The second compute instance may be deployed according to the configuration.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: March 11, 2025
    Assignee: Red Hat, Inc.
    Inventors: Andrea Cosentino, Paolo Antinori
  • Patent number: 12248704
    Abstract: A data storage device comprising a non-volatile storage medium configured to store data, a data port configured to receive and transmit data between a host computer system and the data storage device and a controller. The controller is configured to receive, via the data port, a first command data structure comprising a status reporting activation and receive, via the data port, a second command data structure. In response to receiving the second command data structure, the controller is configured to, determine a response information associated with the second command data structure, and in response to the status reporting activation, determine a status information, and transmit, via the data port, a response data structure comprising the response information and the status information.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 11, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Eyal Hamo, Sagi Taragan, Voltaire Essa
  • Patent number: 12242737
    Abstract: A data storage device and method for accident-mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises single-level cell (SLC) memory and multi-level cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter accident mode; and in response to receiving the command from the vehicle to enter accident mode, relocate vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.
    Type: Grant
    Filed: February 7, 2024
    Date of Patent: March 4, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Nisiel Cohen, Orel Kahlon, Roi Jazcilevich, Aki Bleyer
  • Patent number: 12242386
    Abstract: Various devices, such as storage devices or systems are configured to efficiently process and update logical mappings within control table sets. Control table sets are often groupings of logical mapping corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these mappings must be updated within the control table set. Received changes to these mappings are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: March 4, 2025
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Leeladhar Agarwal, Lawrence Vazhapully Jacob
  • Patent number: 12242345
    Abstract: Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANS). In some examples, a GAN-based decoding reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: March 4, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ariel Navon, Shay Benisty, Alexander Bazarsky, Daniel Joseph Linnen, William Bernard Boyle
  • Patent number: 12243591
    Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 4, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xiang Yang, Jiacen Guo, Takayuki Inoue
  • Patent number: 12244603
    Abstract: Provided are a method, a system, and a computer program product in which metadata associated with encrypted data is maintained in a cloud computing environment, where the metadata indicates whether reading of information in the encrypted data is restricted geographically. A controller provides a decryption code to a cloud server located in a geographical location. The decryption code is for decrypting the encrypted data. The controller provides the decryption code, based on a determination as to whether the metadata indicates whether the reading of information in the encrypted data is restricted geographically.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 4, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Micah Robison
  • Patent number: 12242726
    Abstract: Methods, systems, and devices for capability messaging for memory operations across banks with multiple page access are described. Techniques are described for a memory system to use a same bank for first and second access operations of data associated with an access command. The data corresponding to the second access operation may be communicated after the data corresponding to the first access operation on the same data channels. Techniques are further described for including one or more additional access commands with the access command that use other banks. Techniques are further described for interleaving data sets communicated as a result of the access commands and for abutting data sets based on parameters obtained by the memory device. Techniques are further described for the generation and performance of internal access commands in accordance with a data transfer type indicated by a host system.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: March 4, 2025
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet V. Ayyapureddi
  • Patent number: 12242381
    Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: March 4, 2025
    Assignee: NeuroBlade Ltd.
    Inventors: Elad Sity, Eliad Hillel
  • Patent number: 12242761
    Abstract: A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: March 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jesuk Yeon, Seontaek Kim, Young-Ho Park, Eun Ju Choi, Yonghwa Lee
  • Patent number: 12237032
    Abstract: A system for improving radiation tolerance of memory senses an amount of radiation exposure and, based on the sensed amount of radiation exposure, determines whether to perform one or more techniques for mitigating the effects of the radiation exposure. As an example, the system may perform a data refresh operation by re-writing data that has been corrupted by radiation, or the system may adjust the reference voltage used to read memory cells. In another example, the system may perform a fault repair operation by re-programming cells that have erroneously transitioned from a program state to an erase state. The system may selectively perform different radiation-mitigation techniques in a tiered approach based on the sensed amount of radiation in order to limit the adverse effects of the more invasive techniques.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: February 25, 2025
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventors: Biswajit Ray, Aleksandar Milenkovic
  • Patent number: 12236100
    Abstract: The present disclosure is directed to an operating method of a memory controller, a memory controller, a memory system, and an electronic device. Herein, the operating method can include determining a backup region to be used in an idle state from a memory array, when detecting that remaining capacity of a currently used backup region for storing redundancy parity data in the memory array is less than a required capacity of redundancy parity data to be written, determining the quantity of all backup regions for storing redundancy parity data including the backup region to be used in the memory array, deciding whether the quantity is larger than a preset threshold, and erasing backup regions having stored redundancy parity data in the memory array when the quantity is larger than the preset threshold.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: February 25, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jin Cai, Xianwu Luo
  • Patent number: 12229448
    Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: February 18, 2025
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 12229446
    Abstract: One or more aspects of the present disclosure relate to performant destaging of write pending (WP) data to disk. In embodiments, an input/output (IO) workload is received at a storage array. Additionally, the IO workload can include an IO request with a random write request. Further, a write destage context for write-pending (WP) data corresponding to the random write request can be generated by a data services engine of the storage array. In addition, using the write destage context, a disk adapter (DA), at a backend of the storage array, is enabled to destage write-pending (WP) data without reading from a target write location of the random write request on a storage device on the storage array.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 18, 2025
    Assignee: Dell Products L.P.
    Inventors: Rong Yu, Lixin Pang, Jiahui Wang, Mohammed Asher
  • Patent number: 12229673
    Abstract: Systems, apparatuses and methods may provide for technology that prefetches compressed data and a sparsity bitmap from a memory to store the compressed data in a decode buffer, where the compressed data is associated with a plurality of tensors, wherein the compressed data is in a compressed format. The technology aligns the compressed data with the sparsity bitmap to generate decoded data, and provides the decoded data to a plurality of processing elements.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Deepak Mathaikutty, Arnab Raha, Raymond Sung, Debabrata Mohapatra, Cormac Brick
  • Patent number: 12229018
    Abstract: One example method includes receiving, by a first computing entity from a second computing entity, a request for data, providing, by the first computing entity, a compliance API (Application Program Interface) to the second computing entity, receiving, by the first computing entity from the second computing entity, location information and/or data compliance information, by way of the compliance API, consulting, by the first computing entity, a mapping, and determining, based on information in the mapping and the location information and/or data compliance information, whether or not the data is permitted to be transmitted by the first computing entity to the second computing entity, and either transmitting the data to the second computing entity, or not transmitting the data to the second computing entity, based on data tags, the information in the mapping and the location information and/or data compliance information.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 18, 2025
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael Roche, Michal Drozd, Scott Quesnelle
  • Patent number: 12223170
    Abstract: One or more aspects of the present disclosure relate to relate to analyzing and mitigation storage array latency. In embodiments, an input/output (IO) workload is received by a storage array. Additionally, a latency corresponding to processing one or more IO requests of the IO workload is determined. For example, a factor corresponding to a significant portion of the latency is identified. Further, a remediation action is performed based on the factor identified.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: February 11, 2025
    Assignee: Dell Products L.P.
    Inventors: David Moloney, Eileen Kelleher, Colm O'Leary
  • Patent number: 12222897
    Abstract: Embodiments of this application are applicable to the field of terminal technologies, and provide a file storage location determining method and apparatus, and a terminal. The method includes: A first terminal determines a plurality of candidate paths corresponding to a target file. Each candidate path points to one file storage location. The first terminal obtains file information of the target file. The first terminal determines, based on the file information and the plurality of candidate paths, a file storage location pointed to by a first candidate path in the plurality of candidate paths as a storage location of the target file. A matching degree of the first candidate path is a highest matching degree in matching degrees of the plurality of candidate paths. According to the foregoing method, accuracy of determining the file storage location is improved.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: February 11, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lianbo Zou, Wei Zhang, Puliang Luo
  • Patent number: 12223208
    Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Daniel J. Hubbard, Roy Leonard
  • Patent number: 12222904
    Abstract: A method of synchronously executing input/output operations (IOs) for a plurality of applications using a storage device with a file system includes the steps of: receiving a first write IO including an instruction to write first data at a first address of the file system; determining that, within a first range of the file system comprising the first address, there are no pending unmap IOs for deallocating storage space of the storage device from files of the plurality of applications; after determining that there are no pending unmap IOs within the first range, locking the first range to prevent incoming unmap IOs from deallocating storage space within the first range from the files of the plurality of applications; after locking the first range, writing the first data to the storage device at the first address; and after writing the first data, unlocking the first range.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: February 11, 2025
    Assignee: VMware LLC
    Inventors: Mahesh Hiregoudar, Prasanna Aithal, Prasad Rao Jangam, Srinivasa Shantharam, Rohan Pasalkar, Srikanth Mahabalarao
  • Patent number: 12222697
    Abstract: A differential logger stores, into a log storage from a device memory, a differential log being a log of a device value that has changed at each execution of a control program. A collective logger collectively stores, at a set time, collection target device values into the log storage as reference data to be used to collect the differential log. A split logger acquires as split logs, after the set time, logs of the device values multiple times, and stores the split logs into the reference data storage. The differential logger overwrites data in the log storage with the differential log after new reference data is stored into the log storage.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 11, 2025
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Naoya Okada, Takashi Okamoto
  • Patent number: 12216530
    Abstract: A system, method, and computer-readable medium for performing a data center monitoring and management operation, The data center monitoring and management operation includes receiving data center data for a data center, the data center data comprising data center memory associated data; receiving data center asset data for a plurality of data center assets, the data center asset data comprising data center asset memory associated data; providing the data center memory associated data and the data center asset memory associated data to a memory failure prediction model; and, training the memory failure prediction model using the data center memory associated data and the data center asset memory associated data.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: February 4, 2025
    Assignee: Dell Products L.P.
    Inventor: Deepak NagarajeGowda
  • Patent number: 12219101
    Abstract: An image processing system capable of managing image data using a plurality of boxes, comprises a microphone that obtains a sound, an obtaining unit that obtains a user identifier based on voice information of a user obtained via the microphone, a specifying unit that specifies one box among the plurality of boxes based on specification information including at least the user identifier, and an informing unit that informs the user of information related to the specified one box.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: February 4, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shintaro Okamura
  • Patent number: 12216941
    Abstract: A memory system includes a memory area. A controller controls data. A first connector inputs the data and/or outputs the data, and is removable from the host. A first holding part is electrically disconnected from the memory area and the first connector and including a first port, and holds identification information used to authenticate an authority to initialize the memory area. The first port outputs the identification information to the host when receiving, from the host, an initialization command that instructs initialization of at least the part of the memory area. The controller includes a second port and an authentication part. The second port receives the initialization command from the host and receives the identification information via the first port. The authentication part executes initialization of at least the part of the memory area based on the initialization command and the identification information received at the second port.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: February 4, 2025
    Assignee: Kioxia Corporation
    Inventor: Shintaro Haba
  • Patent number: 12217803
    Abstract: A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Abdelhakim S. Alhussien, James Fitzpatrick, Patrick Robert Khayat, Sivagnanam Parthasarathy
  • Patent number: 12210753
    Abstract: Systems, apparatus and methods are provided for determining an optimal performance profile and a predicted temperature. A method may include receiving a command from a host. The command may contain a logical block address (LBA) for data stored in a data storage system, a length for a data size associated with the command, and a timestamp associated with the command. The method may further include obtaining LBA information, the timestamp, the data size from the command, providing the LBA information, the timestamp, the data size, along with temperature readings, and a performance profile as inputs to a machine learning model, determining an optimal performance profile and a predicted temperature using the machine learning model and configuring a storage controller with settings of the optimal performance profile.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 28, 2025
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Lin Chen
  • Patent number: 12210745
    Abstract: Techniques are provided for creating secure IO (input/output) user connections between IO users and storage volumes. One method comprises establishing an IO user connection between a processor-based IO user and at least a portion of a storage volume on a storage array; obtaining IO user context information associated with the IO user connection, wherein the IO user context information comprises one or more keys for signature verification; and transmitting one or more IO operations over the IO user connection, wherein a signature associated with a given IO operation is evaluated to verify that the signature is a valid signature of one or more of the processor-based IO user and the storage array. The obtained IO user context information may further comprise an identifier of a signature generation function that generates the signature associated with the given IO operation and a connection identity string identifying the IO user connection.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 28, 2025
    Assignee: Dell Products L.P.
    Inventors: Shoham Levy, Michal Sara Davidson
  • Patent number: 12210776
    Abstract: A direct-attached storage device software RAID crash dump system includes a chassis housing a software RAID subsystem coupled to physical storage devices, controller devices, and a hypervisor subsystem. The software RAID subsystem presents a primary controller device to the hypervisor subsystem as being connected to a logical storage device provided by the physical storage devices. When the software RAID subsystem receives a first crash dump command from the hypervisor subsystem directed to the primary controller device and identifying a crash dump logical storage subsystem in the logical storage device, it transmits a respective second crash dump command to each of a subset of the physical storage devices that provide the crash dump logical storage subsystem via a respective controller device that couple the software RAID subsystem to that physical storage device, confirms completion of the respective second crash dump commands, and transmits a crash dump confirmation to the hypervisor subsystem.
    Type: Grant
    Filed: July 29, 2023
    Date of Patent: January 28, 2025
    Assignee: Dell Products L.P.
    Inventors: Nikhith Ganigarakoppal Kantharaju, Abhijit Shashikant Mirajkar, Ajay Sukumaran Nair Syamala Bai
  • Patent number: 12210760
    Abstract: An object storage system, a migration control device, and a migration control method are provided. The migration control method includes observing a plurality of total target input/output (I/O) throughputs, inferring a plurality of reference I/O throughputs by using a first neural network, observing a plurality of target I/O throughputs with respect to an i-th storage device, determining a target object to be migrated and a target storage device, in which the target object will be stored, by using a second neural network, and generating a command instructing to migrate the target object to the target storage device.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: January 28, 2025
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Honguk Woo, Seunghwan Jeong, Jooyoung Park, Youngseok Lee
  • Patent number: 12197763
    Abstract: A method for erasing data stored from memory of a network device comprises erasing stored data from the memory of the network device and requesting data from the memory of the network device after completion of the data erasure procedure or accessing the memory of the network device after completion of the data erasure procedure. The method further comprises determining the outcome of the data erasure procedure based at least in part on: the results of a comparison between a response received from the network device and an expected response which indicates a successful erasure of the memory of the network device; or a comparison between any contents of the memory of the network device after completion of the data erasure procedure and expected contents of the memory after the data erasure procedure which are indicative of a successful erasure of the memory of the network device.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: January 14, 2025
    Assignee: BLANCCO TECHNOLOGY GROUP IP OY
    Inventors: Mitesh Shah, Markku Valtonen, Dhia Ben Haddej, Chandrashekhar Kakade, Akash Nehere, Prasad Bidkar, Pratibha Pathekar
  • Patent number: 12197753
    Abstract: Disclosed are a method and a system for data uploading, which belongs to the technical field of blockchain. The method comprises: receiving a block upload request sent by a slave server of a target node; determining whether block data corresponding to the block upload request has been uploaded to a block data storage system; if the block data corresponding to the block upload request is not uploaded to the block data storage system, acquiring the block data if the block data corresponding to the block upload request is not uploaded to the block data storage system, and uploading the block data to a storage space of the block data storage system; and sending an uploading success instruction to the slave server if the uploading is successful, so as to instruct the slave server to delete the block data stored on a light-weight peer in the target node.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 14, 2025
    Assignee: JINGDONG TECHNOLOGY INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Long Cao, Chao Ma, Haibo Sun, Yi Wang, Ming Zhao
  • Patent number: 12197770
    Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. Based on embodiments of the disclosed technology, the memory system may suspend a target operation, which is a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. Accordingly, the memory system is capable of preventing a problem in that the end time of a program operation or an erase operation is excessively delayed, and controlling the number of times a program operation or an erase operation is suspended.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: January 14, 2025
    Assignee: SK HYNIX INC.
    Inventors: Seung Gu Ji, Hyung Min Lee
  • Patent number: 12198779
    Abstract: A memory system includes a plurality of memory cells each storing a first bit and a second bit and a control circuit. The control circuit is reads out first data, first partial data, and second partial data, each corresponding to the first bit, from the plurality of memory cells, read out second data, third partial data, and fourth partial data, each corresponding to the second bit, from the plurality of memory cells, generate first compressed data based on an OR operation of the first partial data and the third partial data, generate second compressed data based on an OR operation of the second partial data and the fourth partial data, and transmit the first data, the second data, the first compressed data, and the second compressed data to an external memory controller.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: January 14, 2025
    Assignee: Kioxia Corporation
    Inventor: Mitsuaki Honma
  • Patent number: 12197776
    Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: January 14, 2025
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Michal Wysoczanski, Kapil Karkra, Piotr Wysocki, Anand S. Ramalingam
  • Patent number: 12197784
    Abstract: Disclosed is an operation method of a storage device which includes setting a first threshold value for a first host and a second threshold value for a second host under control of a hypervisor, sequentially fetching host commands from the first and second hosts, storing the fetched host commands in an internal command queue, stopping fetching a host command from the first host when the number of first host commands fetched from the first host from among the host commands stored in the internal command queue reaches the first threshold value, and stopping fetching a host command from the second host when the number of second host commands fetched from the second host from among the host commands stored in the internal command queue reaches the second threshold value.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunseok Kang, Soo-Gon Kim, Jaesub Kim, Yangwoo Roh, Jeongbeom Seo
  • Patent number: 12197736
    Abstract: A technique of managing the rate of I/O (Input/Output) request processing includes a token-bucket arrangement having first, second, and third token buckets. The first token bucket is provided with sufficient tokens to accommodate an expected baseline level of I/O requests, whereas the second token bucket is provided with sufficient tokens to accommodate an expected excess level of I/O requests during bursts. The third token bucket is provided with tokens at predefined intervals and limits a total amount of bursting available during those intervals.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: January 14, 2025
    Assignee: Dell Products L.P.
    Inventors: Vitaly Zharkov, Omer Dayan, Eldad Zinger
  • Patent number: 12197788
    Abstract: A system includes a logic that generates a reduced-precision primary data object and an associated residual data object for each of a plurality of uncompressed data objects. The logic classifies the at least some of the generated residual data objects for removal based on data integrity rules and determines that removal of others of the generated residual data objects violates the data integrity rules. The logic removes the at least some of the generated residual data objects classified for removal and applies a corresponding adjustment to at least one of the generated residual data objects.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: January 14, 2025
    Assignee: Chicago Mercantile Exchange Inc.
    Inventor: Carl Erik Thornberg
  • Patent number: 12189750
    Abstract: The disclosure provides an approach for secure offloaded data transfer. Embodiments include receiving, by a security component on a client device, from a storage system connected to the client device, a token associated with a data read request corresponding to a source file on the storage system. Embodiments include determining, by the security component, that the source file is trusted. Embodiments include generating, by the security component, an entry in a trusted token cache based on determining that the source file is trusted, wherein the entry comprises the token. Embodiments include receiving, by the security component, a write request corresponding to a destination file on the storage system, wherein the write request comprises the token or a different token. Embodiments include determining, by the security component, based on the trusted token cache, whether to perform one or more operations related to the write request.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: January 7, 2025
    Assignee: VMware LLC
    Inventors: Amit Anandram Luniya, Sujay Shrikant Godbole
  • Patent number: 12189522
    Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: January 7, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Justin Bates, Ryan Hrinya, Fulvio Rori, Chiara Cerafogli, Carmine Miccoli