Interleaving Patents (Class 711/157)
  • Patent number: 11221950
    Abstract: A storage system and method for interleaving data for enhanced quality of service are provided. In one embodiment, a storage system is presented comprising a memory and a controller. The controller is configured to determine a skip length for interleaving data received from a host; interleave the data according to the determined skip length; store the interleaved data in the memory; and update a logical-to-physical address table to reflect the interleaved data. Other embodiments are provided.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11137936
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: October 5, 2021
    Assignee: Google LLC
    Inventors: Amin Farmahini, Benjamin Steel Gelb, Gurushankar Rajamani, Sukalpa Biswas
  • Patent number: 11055102
    Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 6, 2021
    Assignee: Apple Inc.
    Inventors: Aditya Kesiraju, Brett S. Feero, Nikhil Gupta
  • Patent number: 11048509
    Abstract: Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device includes a vector processor comprising multiple processing elements (PEs) communicatively coupled via a corresponding plurality of channels to a vector register file comprising a plurality of memory banks. The vector processor provides a direct memory access (DMA) controller that is configured to receive a plurality of vectors that each comprise a plurality of vector elements representing operands for processing a loop iteration. The DMA controller arranges the vectors in the vector register file such that, for each group of vectors to be accessed in parallel, vector elements for each vector are stored consecutively, but corresponding vector elements of consecutive vectors are stored in different memory banks of the vector register file.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 29, 2021
    Inventors: Hadi Parandeh Afshar, Amrit Panda, Eric Rotenberg, Gregory Michael Wright
  • Patent number: 11036642
    Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Dimitrios Ziakas, Mark A. Schmisseur, Kshitij A. Doshi, Kimberly A. Malone
  • Patent number: 11023249
    Abstract: The present invention relates to a method of reading images using redundant copies and recovery mechanisms to produce valid images, including: reading an OS boot table from a default location in at least one flash memory to at least one DDR SDRAM of a printed circuit board, using at least one processor connected to at least one FPGA; wherein the boot table describes where to find an OS image and a RAM filesystem image in the flash memory; reading a RAM filesystem image from the flash memory into the DDR SDRAM; and validating the boot table and the RAM filesystem image by checking them for corruption using header information and cyclic redundancy check methods; wherein when at least one of the OS image or the RAM filesystem image is corrupt, a valid image can be compiled using valid sections of each of the OS image or the RAM filesystem image.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 1, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventor: Jennifer A. S. Corekin
  • Patent number: 11010316
    Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Won Park, Je-Min Ryu, Sang-Hoon Shin, Jae-Hoon Jung
  • Patent number: 10996949
    Abstract: A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventor: Jan Van Lunteren
  • Patent number: 10977188
    Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 13, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
  • Patent number: 10970202
    Abstract: Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more unprocessed write requests, a target storage device type from the first type of storage device and the second type of storage device; issuing a first group of write requests to the first type of storage device, the first group of write requests addressed to one or more locations selected in dependence upon an expected address translation to be performed by the first type of storage device; and issuing a second group of write requests to the second type of storage device, the second group of write requests addressed to one or more locations selected in dependence upon a layout of memory in the second type of storage device.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: April 6, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Peter Kirkpatrick, John Colgrove, Neil Vachharajani
  • Patent number: 10969966
    Abstract: Embodiments of the present disclosure relate to method and device for data read/write. The method comprises: in response to receiving a first read/write request for a first target area, determining whether there is a second read/write request under execution in conflict with the first read/write request, a second target area for the second read/write request at least partially overlapping with the first target area, and at least one of the first read/write request and the second read/write request being a write request; and in response to determining there being the second read/write request in conflict, suspending the first read/write request while maintaining a sub-area of the first target area in an unlocked state, the sub-area not overlapping with the second target area.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Bean Bin Zhao, Wilson Guoyu Hu, Jun Wu, Shuo Lv, Qiaosheng Zhou, Lester Ming Zhang
  • Patent number: 10943183
    Abstract: An electronic device includes a memory device storing data and a system-on-a-chip using the memory device as a working memory. The system-on-a-chip performs software training on a second memory area of the memory device by loading a training code to a first memory area of the memory device, and executing the loaded training code.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gyu-Hwan Cha
  • Patent number: 10908906
    Abstract: An apparatus and method for a tensor permutation engine. The TPE may include a read address generation unit (AGU) to generate a plurality of read addresses for the plurality of tensor data elements in a first storage and a write AGU to generate a plurality of write addresses for the plurality of tensor data elements in the first storage. The TPE may include a shuffle register bank comprising a register to read tensor data elements from the plurality of read addresses generated by the read AGU, a first register bank to receive the tensor data elements, and a shift register to receive a lowest tensor data element from each bank in the first register bank, each tensor data element in the shift register to be written to a write address from the plurality of write addresses generated by the write AGU.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Berkin Akin
  • Patent number: 10840948
    Abstract: A method, system, and apparatus for interleaving data including creating a buffer, writing input data, and reading output data out of the buffer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Acacia Communications, Inc.
    Inventor: Pierre Humblet
  • Patent number: 10817493
    Abstract: Generally discussed herein are systems, devices, and methods for data interpolation. A system for data interpolation can include first circuitry to split a set of data into four disjoint subsets including first, second, third, and fourth subsets and load each of the disjoints subsets into respective first, second, third, and fourth memory portions, second circuitry to retrieve, simultaneously, data from each of the first, second, third, and fourth memory portions, and interpolation circuitry to perform, based on the retrieved data, data interpolation.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 27, 2020
    Assignee: Raytheon Company
    Inventor: James R. Sackett
  • Patent number: 10740004
    Abstract: A computer program product is provided for efficiently managing storage in a multi-tiered storage system. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to receive a command from an application, where the command is directed to at least one object. The program instructions are further executable by the processor to cause the processor to determine storage for the at least one object in a multi-tiered storage system based on the command, and store the at least one object in accordance with the determined storage.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert B. Basham, Joseph W. Dain, Evangelos S. Eleftheriou, Dean Hildebrand, Stan Li, Edward H. W. Lin, Harold J. Roberson, II, Slavisa Sarafijanovic, Thomas D. Weigold
  • Patent number: 10725698
    Abstract: Provided is a controller which issues a first write command for writing all data of a burst access operation on a memory and a second write command for writing data of a burst access operation on a memory per byte. The controller includes a holding unit configured to hold a plurality of commands requesting access to the memory and a selection unit configured to select, in a case where the holding unit holds the second write command and a command that causes a first time penalty longer than a second time penalty needed between the first write command that is issued first and the second write command that is issued next, the second write command prior to the command.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Wataru Ochiai
  • Patent number: 10691632
    Abstract: A computer architecture that connects a plurality of compute engines and memory banks using one or more permutated ring networks to provide a scalable, high-bandwidth, low-latency point-to-point multi-chip communications solution.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 23, 2020
    Assignee: DeGIRUM Corporation
    Inventor: Kit S. Tam
  • Patent number: 10658064
    Abstract: A test method for a memory device which includes performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit, performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region, performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit, and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeong-Jun Lee
  • Patent number: 10642734
    Abstract: Systems, apparatuses, and methods for managing a non-power of two memory configuration are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem with a non-power of two number of active memory channels. The control unit reduces a ratio of the number of active memory channels over the total number of physical memory channels to a ratio of a first number to a second number. If a first subset of physical address bits of a received memory request are greater than or equal to the first number, the control unit calculates a third number which is equal to a second subset of physical address bits modulo the first number and the control unit uses a concatenation of the third number and a third subset of physical address bits to select a memory channel for issuing the received memory request.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 5, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Pazhani Pillai
  • Patent number: 10642733
    Abstract: A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 5, 2020
    Assignee: LIGHTBITS LABS LTD.
    Inventor: Ofer Hayut
  • Patent number: 10613864
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 10558368
    Abstract: This technology relates to a memory system in which a plurality of memory devices operates in an interleaving manner and an operating method of the memory system. The memory system may include a plurality of memory devices, a host controller suitable for generating a plurality of internal read commands by splitting an external read command applied from a host in a minimum read size, and a memory controller suitable for checking information about internal read commands which belong to the plurality of internal read commands and which are sequentially late in a section in which a read operation is performed on the plurality of memory devices based on check values of information about internal read commands which belong to the plurality of internal read commands and which are sequentially ahead.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae-Hong Kim, Soong-Sun Shin
  • Patent number: 10554221
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10540277
    Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: January 21, 2020
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
  • Patent number: 10503637
    Abstract: A system on chip which is connected with a plurality of memory chips includes first and second processors, a first access window, a first linear remapper, and a memory controller. The first and second processors are configured to provide an address for using the plurality of memory chips. The first access window sets an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips. The first linear remapper remaps an address received from the first processor. The memory controller performs a partial linear access operation with respect to the plurality of memory chips, based on an area set by the first access window and an address remapped by the first linear remapper.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dongsik Cho
  • Patent number: 10481823
    Abstract: A data storage system includes first and second storage devices accessed via first and second hardware channels, respectively. A storage controller receives a first access request requesting access to first data and a second access request requesting access to second data, where both the first data and the second data are accessed via the first hardware channel. In response to detecting receipt of the first and second access requests within a same service window defining a range of temporal proximity, the storage controller records an association of identifiers of the first data and second data requested by the first and second access requests, respectively. The storage controller thereafter migrates the second data accessed by the second access request from the first storage device to the second storage device based on the recorded association, such that the first and second data are available for access via different hardware channels.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell, Yijie Zhang, Samuel K. Ingram
  • Patent number: 10461778
    Abstract: An apparatus and method for interleaving and puncturing are provided. The apparatus includes: an interleaver formed of a plurality of columns and rows, configured to perform interleaving by writing bits input to the interleaver in the plurality of columns and reading the bits from each row of the plurality of columns in which the bits are written; and a puncturer configured to puncture a predetermined number of bits among the bits read from the interleaver.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 29, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Hong-sil Jeong, Sang-hyo Kim, Kyung-joong Kim, Se-ho Myung, Jong-hwan Kim, Dae-hyun Ryu, Min Jang
  • Patent number: 10360147
    Abstract: Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Timothy P. Finkbeiner
  • Patent number: 10275350
    Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: Dell Products, LP
    Inventor: Stuart Allen Berke
  • Patent number: 10169395
    Abstract: One or more processors initiate generation of an identifier based on the definitions of both a primary range and a secondary range. One or more processors obtain a unique sequence value from a unique sequence range of known maximum number of values. One or more processors calculate an offset value based on, at least in part, the primary range and the secondary range. One or more processors add the offset value to the unique sequence value to generate an identifier value.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sean K. Dunne, Martin A. Flint, Liam S. Harpur, Peter McGrath
  • Patent number: 10158702
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 18, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shahar, Hillel Chapman, Gilad Shainer, Adi Menachem, Ofer Hayut
  • Patent number: 10102157
    Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Jeffrey R. Wilcox, Noam Yosef
  • Patent number: 10063257
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10056920
    Abstract: A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 21, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yiming Chen, Anantha Raman Krishnan
  • Patent number: 9927977
    Abstract: A method includes generating a plurality of segment allocation tables (SATs) for pluralities of sets of encoded data slices. For a first SAT, the method further includes dispersed storage error encoding the first SAT to produce a first set of encoded SAT slices. The method further includes generating a first source name for the first plurality of sets of encoded data slices and the first SAT based on an object identifier associated with the data object. The method further includes generating, based on the first source name, a first plurality of sets of slices names for the first plurality of sets of encoded data slices and the first set of encoded SAT slices. The method further includes outputting, based on the first plurality of sets of slices names, the first plurality of sets of encoded data slices and the first set of encoded SAT slices to storage units.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 9823984
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for remapping of memory in memory control architectures. A processing device includes a processing core and a platform controller hub (PCH) coupled to the processing core. The PCH is to receive an indication of a failure associated with a first memory region of a plurality of memory regions residing in a memory. The PCH is also to interrupt an operating system to prompt for a reboot. Upon the reboot, the PCH is to remap a memory address range associated with the first memory region to a second memory region of the plurality of regions.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventor: Leong Hock Sim
  • Patent number: 9811417
    Abstract: According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Abe
  • Patent number: 9811460
    Abstract: Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2n channels, where n is a natural number greater than 0, allocating a first channel of the 2n channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Hong Jeon, Hyeok-Man Kwon, Nak-Hee Seong
  • Patent number: 9769476
    Abstract: A digital receiver includes a pre-de-interleaver processing block for receiving a receive signal including reception data units quantized using a quantization rule. The digital receiver additionally includes a controllable compressor for compressing the data units into a compressed representation, a controllable time-de-interleaver being configured for applying a varying interleaving size in data units, and a controller for controlling the controllable processor or the controllable time-de-interleaver. The controller is configured for controlling the compressor or the time-de-interleaver so that a higher interleaving size such as a higher interleaving time or a higher number of data units per second is applied, when a compression in a lower number of bits is active.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 19, 2017
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Marco Breiling, Holger Stadali, Amaia Anorga Gomez
  • Patent number: 9761273
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword, and second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword that is written to the storage medium.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 12, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 9754674
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Patent number: 9720825
    Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Dell Products, LP
    Inventor: Stuart Allen Berke
  • Patent number: 9696908
    Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Balluchi, Graziano Mirichigni
  • Patent number: 9690510
    Abstract: Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang Ting Chen, Ching-Wei Wu
  • Patent number: 9612648
    Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dexter Chun, Yanru Li, Alex Tu, Haw-Jing Lo
  • Patent number: 9606869
    Abstract: A method includes dividing a data file into a plurality of data regions. For each data region, the method includes determining a segmentation approach; determining a dispersed storage error encoding function; segmenting the data region into a plurality of data segments in accordance with the segmentation approach; and dispersed storage error encoding the plurality of data segments to produce a plurality of sets of encoded data slices in accordance with the dispersed storage error encoding function. The method includes creating a segment allocation table (SAT) for the data file and dispersed storage error encoding the segment allocation table to produce a set of encoded SAT slices. The method includes outputting the set of encoded SAT slices with at least one of the pluralities of sets of encoded data slices for storage in storage units of the DSN.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 9582420
    Abstract: Mapping an address for memory access in a memory system into a combination address that includes a memory bank identifier and a memory bank internal address. The address is partitioned into a first portion, and a second portion. The memory bank identifier is determined by performing a look-up operation in a look-up matrix, in which a look-up matrix row is determined by the value of the first portion, and a look-up matrix column is determined by the value of a binary number with two or more bits formed by applying a parity function to two or more respective sub-portions of the second portion. The memory bank internal address is derived based on the second portion of the address.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventor: Jan Van Lunteren
  • Patent number: 9575906
    Abstract: Embodiments of systems and methods disclosed herein may isolate the working set of a process such that the data of the working set is inaccessible to other processes, even after the original process terminates. More specifically, in certain embodiments, the working set of an executing process may be stored in cache and for any of those cache lines that are written to while in secure mode those cache lines may be associated with a secure descriptor for the currently executing process. The secure descriptor may uniquely specify those cache lines as belonging to the executing secure process such that access to those cache lines can be restricted to only that process.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: February 21, 2017
    Assignee: Rubicon Labs, Inc.
    Inventor: William V. Oxford
  • Patent number: 9552175
    Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system is configured to receive a command from a host memory controller of a host system and store the command in a command buffer entry. The system determines that the command is complete using a buffer check logic and provides the command to a command buffer. The command buffer comprises a first field that specifies an entry point of the command within the command buffer entry.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 24, 2017
    Assignee: DIABLO TECHNOLOGIES INC.
    Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone