Interleaving Patents (Class 711/157)
  • Patent number: 10360147
    Abstract: Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Timothy P. Finkbeiner
  • Patent number: 10275350
    Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: Dell Products, LP
    Inventor: Stuart Allen Berke
  • Patent number: 10169395
    Abstract: One or more processors initiate generation of an identifier based on the definitions of both a primary range and a secondary range. One or more processors obtain a unique sequence value from a unique sequence range of known maximum number of values. One or more processors calculate an offset value based on, at least in part, the primary range and the secondary range. One or more processors add the offset value to the unique sequence value to generate an identifier value.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sean K. Dunne, Martin A. Flint, Liam S. Harpur, Peter McGrath
  • Patent number: 10158702
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 18, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shahar, Hillel Chapman, Gilad Shainer, Adi Menachem, Ofer Hayut
  • Patent number: 10102157
    Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Jeffrey R. Wilcox, Noam Yosef
  • Patent number: 10063257
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10056920
    Abstract: A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 21, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yiming Chen, Anantha Raman Krishnan
  • Patent number: 9927977
    Abstract: A method includes generating a plurality of segment allocation tables (SATs) for pluralities of sets of encoded data slices. For a first SAT, the method further includes dispersed storage error encoding the first SAT to produce a first set of encoded SAT slices. The method further includes generating a first source name for the first plurality of sets of encoded data slices and the first SAT based on an object identifier associated with the data object. The method further includes generating, based on the first source name, a first plurality of sets of slices names for the first plurality of sets of encoded data slices and the first set of encoded SAT slices. The method further includes outputting, based on the first plurality of sets of slices names, the first plurality of sets of encoded data slices and the first set of encoded SAT slices to storage units.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 9823984
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for remapping of memory in memory control architectures. A processing device includes a processing core and a platform controller hub (PCH) coupled to the processing core. The PCH is to receive an indication of a failure associated with a first memory region of a plurality of memory regions residing in a memory. The PCH is also to interrupt an operating system to prompt for a reboot. Upon the reboot, the PCH is to remap a memory address range associated with the first memory region to a second memory region of the plurality of regions.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventor: Leong Hock Sim
  • Patent number: 9811417
    Abstract: According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Abe
  • Patent number: 9811460
    Abstract: Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2n channels, where n is a natural number greater than 0, allocating a first channel of the 2n channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Hong Jeon, Hyeok-Man Kwon, Nak-Hee Seong
  • Patent number: 9769476
    Abstract: A digital receiver includes a pre-de-interleaver processing block for receiving a receive signal including reception data units quantized using a quantization rule. The digital receiver additionally includes a controllable compressor for compressing the data units into a compressed representation, a controllable time-de-interleaver being configured for applying a varying interleaving size in data units, and a controller for controlling the controllable processor or the controllable time-de-interleaver. The controller is configured for controlling the compressor or the time-de-interleaver so that a higher interleaving size such as a higher interleaving time or a higher number of data units per second is applied, when a compression in a lower number of bits is active.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 19, 2017
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Marco Breiling, Holger Stadali, Amaia Anorga Gomez
  • Patent number: 9761273
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword, and second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword that is written to the storage medium.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 12, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 9754674
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Patent number: 9720825
    Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Dell Products, LP
    Inventor: Stuart Allen Berke
  • Patent number: 9696908
    Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Balluchi, Graziano Mirichigni
  • Patent number: 9690510
    Abstract: Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang Ting Chen, Ching-Wei Wu
  • Patent number: 9612648
    Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dexter Chun, Yanru Li, Alex Tu, Haw-Jing Lo
  • Patent number: 9606869
    Abstract: A method includes dividing a data file into a plurality of data regions. For each data region, the method includes determining a segmentation approach; determining a dispersed storage error encoding function; segmenting the data region into a plurality of data segments in accordance with the segmentation approach; and dispersed storage error encoding the plurality of data segments to produce a plurality of sets of encoded data slices in accordance with the dispersed storage error encoding function. The method includes creating a segment allocation table (SAT) for the data file and dispersed storage error encoding the segment allocation table to produce a set of encoded SAT slices. The method includes outputting the set of encoded SAT slices with at least one of the pluralities of sets of encoded data slices for storage in storage units of the DSN.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 9582420
    Abstract: Mapping an address for memory access in a memory system into a combination address that includes a memory bank identifier and a memory bank internal address. The address is partitioned into a first portion, and a second portion. The memory bank identifier is determined by performing a look-up operation in a look-up matrix, in which a look-up matrix row is determined by the value of the first portion, and a look-up matrix column is determined by the value of a binary number with two or more bits formed by applying a parity function to two or more respective sub-portions of the second portion. The memory bank internal address is derived based on the second portion of the address.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventor: Jan Van Lunteren
  • Patent number: 9575906
    Abstract: Embodiments of systems and methods disclosed herein may isolate the working set of a process such that the data of the working set is inaccessible to other processes, even after the original process terminates. More specifically, in certain embodiments, the working set of an executing process may be stored in cache and for any of those cache lines that are written to while in secure mode those cache lines may be associated with a secure descriptor for the currently executing process. The secure descriptor may uniquely specify those cache lines as belonging to the executing secure process such that access to those cache lines can be restricted to only that process.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: February 21, 2017
    Assignee: Rubicon Labs, Inc.
    Inventor: William V. Oxford
  • Patent number: 9552175
    Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system is configured to receive a command from a host memory controller of a host system and store the command in a command buffer entry. The system determines that the command is complete using a buffer check logic and provides the command to a command buffer. The command buffer comprises a first field that specifies an entry point of the command within the command buffer entry.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 24, 2017
    Assignee: DIABLO TECHNOLOGIES INC.
    Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone
  • Patent number: 9547444
    Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: January 17, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xueshi Yang, Chi Kong Lee
  • Patent number: 9502125
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Patent number: 9477562
    Abstract: A line of data is read from a line of memory. Intended data is specified by a random location and a random size within the line of memory. The line of data is moved into temporary storage. The line of data and a zero are multiplexed using a control signal to output a line of adjusted data which is automatically aligned to an initial point in an XOR buffer. A starting index of the intended data within the line of adjusted data corresponds to the initial point within an XOR buffer. An XOR operation is performed on the line of adjusted data and a line of data read from the XOR buffer to obtain a modified line of XOR data. The modified line of XOR data is written back to the XOR buffer at the same buffer locations as the line of data read from the XOR buffer.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 25, 2016
    Assignee: Microsemi Storage Solutions (US), Inc.
    Inventors: Mohammad Nikuie, Ihab Jaser
  • Patent number: 9477617
    Abstract: A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: October 25, 2016
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Qamrul Hasan, Stephan Rosner, Roger Dwain Isaac
  • Patent number: 9465735
    Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Bohuslav Rychlik, Feng Wang, Anwar Rohillah, Simon Booth
  • Patent number: 9411592
    Abstract: Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Mark J. Charney, Jesus Corbal, Milind B. Girkar, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Brett L. Toll
  • Patent number: 9378125
    Abstract: Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 28, 2016
    Assignee: Foundation of Soongsil University-Industry Cooperation
    Inventor: Chan-Ho Lee
  • Patent number: 9355127
    Abstract: Database queries are optimized through the functionality of decomposition data skew in an asymmetric massively parallel processing database system. A table having data skew is restructured by (1) storing original data values of a distribution key in a special switch column added to the table, (2) replacing the original data values of the distribution key with modified data values such as randomly generated data values, and (3) partitioning the rows across the nodes of the asymmetric massively parallel processing database system based on the distribution key. The original data values that are stored and replaced may only comprise a subset of the original data values that cause data skew in the table. Data skew is reduced, which improves performance, yet the original data values remain available, which reduces the impact on collocated joins.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lukasz Gaza, Artur M. Gruszecki, Tomasz Kazalski, Grzegorz S. Milka, Konrad Krzysztof Skibski, Tomasz Stradomski, Natalya A. Yanayt
  • Patent number: 9344490
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: May 17, 2016
    Assignee: Mellanox Technologies Ltd.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinobitz, Pavel Shamis, Gilad Shainer
  • Patent number: 9335951
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Pil Son, Chul Woo Park, Hak Soo Yu, Hong Sun Hwang
  • Patent number: 9330009
    Abstract: A method and system for use in managing data storage is disclosed. Data storage in a data storage system is managed. The data storage system comprises a first data storage tier and a second data storage tier configured such that the performance characteristics associated with one of the data storage tiers is superior to the other data storage tier. I/O activity is determined in connection with a data group stored on one of the first and second data storage tiers. It is determined whether to migrate the data group stored on the one of the first and second data storage tiers to the other data storage tier based on the performance characteristics associated with the other data storage tier and the determined I/O activity. The data group is migrated to the other data storage tier in response to determining to migrate the data group to the other data storage tier.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 3, 2016
    Assignee: EMC Corporation
    Inventors: Dean D. Throop, Dennis T. Duprey, Miles de Forest, Michael D. Haynes
  • Patent number: 9268744
    Abstract: A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: February 23, 2016
    Assignee: Institute of Automation, Chinese Academy of Sciences
    Inventors: Shaolin Xie, Donglin Wang, Jie Hao, Tao Wang, Leizu Yin
  • Patent number: 9189240
    Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer
  • Patent number: 9159274
    Abstract: A system and a method for updating an electronic paper display are disclosed. A memory includes a waveform table and a transition matrix including multiple pixels, each representing a pixel of the electronic paper display. A page transition display system is coupled to the memory and identifies waveforms from the waveform table associated with multiple transition matrix pixels by processing multiple transition matrix pixels in parallel. For example, the page transition display system loads multiple transition matrix pixels into a register and accesses the waveform table using the contents of the register. Using the identified waveforms, the page transition display system generates control signals used to modify the electronic paper device.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: October 13, 2015
    Assignee: Ricoh Co., Ltd.
    Inventors: Bradley J. Rhodes, Guotong Feng, Edward L. Schwartz
  • Patent number: 9146738
    Abstract: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: September 29, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Dale Morris
  • Patent number: 9141626
    Abstract: A volume system that presents a volume having an extent of logical addresses to a file system. A volume exposure system exposes the volume to the file system in a manner that the volume has multiple tiers, each offering storage of different traits. This is performed using multiple heterogenic underlying storage systems, each having different storage system-specific traits. Each underlying storage system may be hardware, software, or a combination thereof that permits each storage system to expose storage having the particular storage system-specific traits to the file system. The volume system supports each tier by mapping logical addresses of the tier to portions of underling storage systems that are consistent with the tier traits.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 22, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shiv Rajpal, Karan Mehra, Andrew Herron, Shi Cong
  • Patent number: 9116904
    Abstract: A file system that operates on an underlying volume that has multiple tiers, each tier including a particular trait set. Upon creating or otherwise identifying a file system namespace (such as a directory or file) that is in a volume or that is to be included within the volume, a storage trait set to be applied corresponding to the file system namespace is identified. Then, the storage trait set is compared against the trait sets for the multiple tiers to identify a tier into which to store the file system namespace. The file system namespace is then caused to be stored within the identified tier. Thus, the file system is provided with a volume that has multiple tiers (each having different trait sets) to choose from in storing files.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 25, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Neal Robert Christiansen, Daniel Chan, Rajsekhar Das, Juan-Lee Pang, Malcolm James Smith, Andrew Herron
  • Patent number: 9104526
    Abstract: A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: August 11, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Sun Jeon, Ho Jin Lee, Joon Hyuk Cha, Shi Hwa Lee, Young Su Moon, Hyun Sang Park
  • Patent number: 9100673
    Abstract: A digital broadcasting transmission and/or reception system having an improved reception performance and a signal-processing method thereof. A digital broadcasting transmitter comprises a TRS encoder for to TRS-encode a MPEG-2 transmission stream having null data for inserting a Known data and a TRS parity at predetermined positions, randomizer to input and randomize data stream from the TRS encoder, a null packet exchanger to replace the null data for inserting the Known data to the known data, and an encoder for encoding a data streams to which the Known data is inserted. Accordingly, the present invention detects the known data from a signal received from a reception side and uses the detected known data for synchronization and equalization and further uses the TRS parity for correcting error of the received signal, so that the digital broadcasting reception performance can be improved at poor multipath channels.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 4, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-deok Chang, Joon-soo Kim, Sung-woo Park
  • Patent number: 9092327
    Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Subrato K. De, Richard A. Stewart, Gheorghe Calin Cascaval, Dexter T. Chun
  • Patent number: 9086954
    Abstract: A data storing method for a memory storage apparatus having a flash memory module is provided. The method includes detecting the operating temperature of the memory storage device through a thermal sensor and determining whether the operating temperature of the memory storage device is larger than a predetermined temperature. The methods further includes using a first data storing mode to access the flash memory module if the operating temperature of the memory storage device is not larger than the predetermined temperature; and using a second data storing mode to access the flash memory module if the operating temperature of the memory storage apparatus is larger than the predetermined temperature, wherein the first data storing mode is different from the second data storing mode. Accordingly, the method can effectively ensure the accuracy of the data stored into the flash memory module.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 21, 2015
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9076516
    Abstract: Provided is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Junghoon Park
  • Patent number: 9063850
    Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: June 23, 2015
    Assignee: Memory Technologies LLC
    Inventors: Jani Hyvonen, Kimmo J. Mylly, Jussi Hakkinen, Yevgen Gyl
  • Patent number: 9058894
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 16, 2015
    Assignee: INTEL CORPORATION
    Inventors: Jim Kardach, Nikos Kaburlasos
  • Patent number: 9032167
    Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating writing, in a sequential order, portions of the file data to a first buffer and a second buffer. The disclosure also provides for writing from a first buffer and a second buffer to a first track until the first track is filled.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 12, 2015
    Assignee: Comcast Cable Communications, LLC
    Inventor: Niraj K. Sharma
  • Publication number: 20150121019
    Abstract: A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: ARM LIMITED
    Inventors: Ganesh Suryanarayan DASIKA, Rune HOLM, Stephen John HILL
  • Publication number: 20150106577
    Abstract: One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: LSI CORPORATION
    Inventors: Kannan Rajamani, Ramon Sanchez, Kevin R. Kinney
  • Patent number: 9009409
    Abstract: A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a cache region of the memory cache based on an identification that the object has no potential for storage in a shared memory cache and a determination that the cache region is associated with a storage policy that specifies that objects to be stored in the cache region are to be stored in a local memory cache and that a garbage collector is not to remove objects stored in the cache region from the local memory cache.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: April 14, 2015
    Assignee: SAP SE
    Inventors: Galin Galchev, Frank Kilian, Oliver Luik, Dirk Marwinski, Petio G. Petev