Interleaving Patents (Class 711/157)
  • Patent number: 10840948
    Abstract: A method, system, and apparatus for interleaving data including creating a buffer, writing input data, and reading output data out of the buffer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Acacia Communications, Inc.
    Inventor: Pierre Humblet
  • Patent number: 10817493
    Abstract: Generally discussed herein are systems, devices, and methods for data interpolation. A system for data interpolation can include first circuitry to split a set of data into four disjoint subsets including first, second, third, and fourth subsets and load each of the disjoints subsets into respective first, second, third, and fourth memory portions, second circuitry to retrieve, simultaneously, data from each of the first, second, third, and fourth memory portions, and interpolation circuitry to perform, based on the retrieved data, data interpolation.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 27, 2020
    Assignee: Raytheon Company
    Inventor: James R. Sackett
  • Patent number: 10740004
    Abstract: A computer program product is provided for efficiently managing storage in a multi-tiered storage system. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to receive a command from an application, where the command is directed to at least one object. The program instructions are further executable by the processor to cause the processor to determine storage for the at least one object in a multi-tiered storage system based on the command, and store the at least one object in accordance with the determined storage.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert B. Basham, Joseph W. Dain, Evangelos S. Eleftheriou, Dean Hildebrand, Stan Li, Edward H. W. Lin, Harold J. Roberson, II, Slavisa Sarafijanovic, Thomas D. Weigold
  • Patent number: 10725698
    Abstract: Provided is a controller which issues a first write command for writing all data of a burst access operation on a memory and a second write command for writing data of a burst access operation on a memory per byte. The controller includes a holding unit configured to hold a plurality of commands requesting access to the memory and a selection unit configured to select, in a case where the holding unit holds the second write command and a command that causes a first time penalty longer than a second time penalty needed between the first write command that is issued first and the second write command that is issued next, the second write command prior to the command.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Wataru Ochiai
  • Patent number: 10691632
    Abstract: A computer architecture that connects a plurality of compute engines and memory banks using one or more permutated ring networks to provide a scalable, high-bandwidth, low-latency point-to-point multi-chip communications solution.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 23, 2020
    Assignee: DeGIRUM Corporation
    Inventor: Kit S. Tam
  • Patent number: 10658064
    Abstract: A test method for a memory device which includes performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit, performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region, performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit, and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeong-Jun Lee
  • Patent number: 10642734
    Abstract: Systems, apparatuses, and methods for managing a non-power of two memory configuration are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem with a non-power of two number of active memory channels. The control unit reduces a ratio of the number of active memory channels over the total number of physical memory channels to a ratio of a first number to a second number. If a first subset of physical address bits of a received memory request are greater than or equal to the first number, the control unit calculates a third number which is equal to a second subset of physical address bits modulo the first number and the control unit uses a concatenation of the third number and a third subset of physical address bits to select a memory channel for issuing the received memory request.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 5, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Pazhani Pillai
  • Patent number: 10642733
    Abstract: A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 5, 2020
    Assignee: LIGHTBITS LABS LTD.
    Inventor: Ofer Hayut
  • Patent number: 10613864
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 10558368
    Abstract: This technology relates to a memory system in which a plurality of memory devices operates in an interleaving manner and an operating method of the memory system. The memory system may include a plurality of memory devices, a host controller suitable for generating a plurality of internal read commands by splitting an external read command applied from a host in a minimum read size, and a memory controller suitable for checking information about internal read commands which belong to the plurality of internal read commands and which are sequentially late in a section in which a read operation is performed on the plurality of memory devices based on check values of information about internal read commands which belong to the plurality of internal read commands and which are sequentially ahead.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae-Hong Kim, Soong-Sun Shin
  • Patent number: 10554221
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10540277
    Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: January 21, 2020
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
  • Patent number: 10503637
    Abstract: A system on chip which is connected with a plurality of memory chips includes first and second processors, a first access window, a first linear remapper, and a memory controller. The first and second processors are configured to provide an address for using the plurality of memory chips. The first access window sets an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips. The first linear remapper remaps an address received from the first processor. The memory controller performs a partial linear access operation with respect to the plurality of memory chips, based on an area set by the first access window and an address remapped by the first linear remapper.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dongsik Cho
  • Patent number: 10481823
    Abstract: A data storage system includes first and second storage devices accessed via first and second hardware channels, respectively. A storage controller receives a first access request requesting access to first data and a second access request requesting access to second data, where both the first data and the second data are accessed via the first hardware channel. In response to detecting receipt of the first and second access requests within a same service window defining a range of temporal proximity, the storage controller records an association of identifiers of the first data and second data requested by the first and second access requests, respectively. The storage controller thereafter migrates the second data accessed by the second access request from the first storage device to the second storage device based on the recorded association, such that the first and second data are available for access via different hardware channels.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sergio Reyes, Brian C. Twichell, Yijie Zhang, Samuel K. Ingram
  • Patent number: 10461778
    Abstract: An apparatus and method for interleaving and puncturing are provided. The apparatus includes: an interleaver formed of a plurality of columns and rows, configured to perform interleaving by writing bits input to the interleaver in the plurality of columns and reading the bits from each row of the plurality of columns in which the bits are written; and a puncturer configured to puncture a predetermined number of bits among the bits read from the interleaver.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 29, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Hong-sil Jeong, Sang-hyo Kim, Kyung-joong Kim, Se-ho Myung, Jong-hwan Kim, Dae-hyun Ryu, Min Jang
  • Patent number: 10360147
    Abstract: Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Timothy P. Finkbeiner
  • Patent number: 10275350
    Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: Dell Products, LP
    Inventor: Stuart Allen Berke
  • Patent number: 10169395
    Abstract: One or more processors initiate generation of an identifier based on the definitions of both a primary range and a secondary range. One or more processors obtain a unique sequence value from a unique sequence range of known maximum number of values. One or more processors calculate an offset value based on, at least in part, the primary range and the secondary range. One or more processors add the offset value to the unique sequence value to generate an identifier value.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sean K. Dunne, Martin A. Flint, Liam S. Harpur, Peter McGrath
  • Patent number: 10158702
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 18, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shahar, Hillel Chapman, Gilad Shainer, Adi Menachem, Ofer Hayut
  • Patent number: 10102157
    Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Jeffrey R. Wilcox, Noam Yosef
  • Patent number: 10063257
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 10056920
    Abstract: A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 21, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yiming Chen, Anantha Raman Krishnan
  • Patent number: 9927977
    Abstract: A method includes generating a plurality of segment allocation tables (SATs) for pluralities of sets of encoded data slices. For a first SAT, the method further includes dispersed storage error encoding the first SAT to produce a first set of encoded SAT slices. The method further includes generating a first source name for the first plurality of sets of encoded data slices and the first SAT based on an object identifier associated with the data object. The method further includes generating, based on the first source name, a first plurality of sets of slices names for the first plurality of sets of encoded data slices and the first set of encoded SAT slices. The method further includes outputting, based on the first plurality of sets of slices names, the first plurality of sets of encoded data slices and the first set of encoded SAT slices to storage units.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 9823984
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for remapping of memory in memory control architectures. A processing device includes a processing core and a platform controller hub (PCH) coupled to the processing core. The PCH is to receive an indication of a failure associated with a first memory region of a plurality of memory regions residing in a memory. The PCH is also to interrupt an operating system to prompt for a reboot. Upon the reboot, the PCH is to remap a memory address range associated with the first memory region to a second memory region of the plurality of regions.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventor: Leong Hock Sim
  • Patent number: 9811417
    Abstract: According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Abe
  • Patent number: 9811460
    Abstract: Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2n channels, where n is a natural number greater than 0, allocating a first channel of the 2n channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Hong Jeon, Hyeok-Man Kwon, Nak-Hee Seong
  • Patent number: 9769476
    Abstract: A digital receiver includes a pre-de-interleaver processing block for receiving a receive signal including reception data units quantized using a quantization rule. The digital receiver additionally includes a controllable compressor for compressing the data units into a compressed representation, a controllable time-de-interleaver being configured for applying a varying interleaving size in data units, and a controller for controlling the controllable processor or the controllable time-de-interleaver. The controller is configured for controlling the compressor or the time-de-interleaver so that a higher interleaving size such as a higher interleaving time or a higher number of data units per second is applied, when a compression in a lower number of bits is active.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 19, 2017
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Marco Breiling, Holger Stadali, Amaia Anorga Gomez
  • Patent number: 9761273
    Abstract: A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword, and second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword that is written to the storage medium.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 12, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Yiming Chen
  • Patent number: 9754674
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Patent number: 9720825
    Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Dell Products, LP
    Inventor: Stuart Allen Berke
  • Patent number: 9696908
    Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Balluchi, Graziano Mirichigni
  • Patent number: 9690510
    Abstract: Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang Ting Chen, Ching-Wei Wu
  • Patent number: 9612648
    Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dexter Chun, Yanru Li, Alex Tu, Haw-Jing Lo
  • Patent number: 9606869
    Abstract: A method includes dividing a data file into a plurality of data regions. For each data region, the method includes determining a segmentation approach; determining a dispersed storage error encoding function; segmenting the data region into a plurality of data segments in accordance with the segmentation approach; and dispersed storage error encoding the plurality of data segments to produce a plurality of sets of encoded data slices in accordance with the dispersed storage error encoding function. The method includes creating a segment allocation table (SAT) for the data file and dispersed storage error encoding the segment allocation table to produce a set of encoded SAT slices. The method includes outputting the set of encoded SAT slices with at least one of the pluralities of sets of encoded data slices for storage in storage units of the DSN.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilya Volvovski, Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Patent number: 9582420
    Abstract: Mapping an address for memory access in a memory system into a combination address that includes a memory bank identifier and a memory bank internal address. The address is partitioned into a first portion, and a second portion. The memory bank identifier is determined by performing a look-up operation in a look-up matrix, in which a look-up matrix row is determined by the value of the first portion, and a look-up matrix column is determined by the value of a binary number with two or more bits formed by applying a parity function to two or more respective sub-portions of the second portion. The memory bank internal address is derived based on the second portion of the address.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventor: Jan Van Lunteren
  • Patent number: 9575906
    Abstract: Embodiments of systems and methods disclosed herein may isolate the working set of a process such that the data of the working set is inaccessible to other processes, even after the original process terminates. More specifically, in certain embodiments, the working set of an executing process may be stored in cache and for any of those cache lines that are written to while in secure mode those cache lines may be associated with a secure descriptor for the currently executing process. The secure descriptor may uniquely specify those cache lines as belonging to the executing secure process such that access to those cache lines can be restricted to only that process.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: February 21, 2017
    Assignee: Rubicon Labs, Inc.
    Inventor: William V. Oxford
  • Patent number: 9552175
    Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system is configured to receive a command from a host memory controller of a host system and store the command in a command buffer entry. The system determines that the command is complete using a buffer check logic and provides the command to a command buffer. The command buffer comprises a first field that specifies an entry point of the command within the command buffer entry.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 24, 2017
    Assignee: DIABLO TECHNOLOGIES INC.
    Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone
  • Patent number: 9547444
    Abstract: Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: January 17, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xueshi Yang, Chi Kong Lee
  • Patent number: 9502125
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Patent number: 9477562
    Abstract: A line of data is read from a line of memory. Intended data is specified by a random location and a random size within the line of memory. The line of data is moved into temporary storage. The line of data and a zero are multiplexed using a control signal to output a line of adjusted data which is automatically aligned to an initial point in an XOR buffer. A starting index of the intended data within the line of adjusted data corresponds to the initial point within an XOR buffer. An XOR operation is performed on the line of adjusted data and a line of data read from the XOR buffer to obtain a modified line of XOR data. The modified line of XOR data is written back to the XOR buffer at the same buffer locations as the line of data read from the XOR buffer.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 25, 2016
    Assignee: Microsemi Storage Solutions (US), Inc.
    Inventors: Mohammad Nikuie, Ihab Jaser
  • Patent number: 9477617
    Abstract: A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: October 25, 2016
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Qamrul Hasan, Stephan Rosner, Roger Dwain Isaac
  • Patent number: 9465735
    Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Bohuslav Rychlik, Feng Wang, Anwar Rohillah, Simon Booth
  • Patent number: 9411592
    Abstract: Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Mark J. Charney, Jesus Corbal, Milind B. Girkar, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Brett L. Toll
  • Patent number: 9378125
    Abstract: Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 28, 2016
    Assignee: Foundation of Soongsil University-Industry Cooperation
    Inventor: Chan-Ho Lee
  • Patent number: 9355127
    Abstract: Database queries are optimized through the functionality of decomposition data skew in an asymmetric massively parallel processing database system. A table having data skew is restructured by (1) storing original data values of a distribution key in a special switch column added to the table, (2) replacing the original data values of the distribution key with modified data values such as randomly generated data values, and (3) partitioning the rows across the nodes of the asymmetric massively parallel processing database system based on the distribution key. The original data values that are stored and replaced may only comprise a subset of the original data values that cause data skew in the table. Data skew is reduced, which improves performance, yet the original data values remain available, which reduces the impact on collocated joins.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lukasz Gaza, Artur M. Gruszecki, Tomasz Kazalski, Grzegorz S. Milka, Konrad Krzysztof Skibski, Tomasz Stradomski, Natalya A. Yanayt
  • Patent number: 9344490
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: May 17, 2016
    Assignee: Mellanox Technologies Ltd.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinobitz, Pavel Shamis, Gilad Shainer
  • Patent number: 9335951
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Pil Son, Chul Woo Park, Hak Soo Yu, Hong Sun Hwang
  • Patent number: 9330009
    Abstract: A method and system for use in managing data storage is disclosed. Data storage in a data storage system is managed. The data storage system comprises a first data storage tier and a second data storage tier configured such that the performance characteristics associated with one of the data storage tiers is superior to the other data storage tier. I/O activity is determined in connection with a data group stored on one of the first and second data storage tiers. It is determined whether to migrate the data group stored on the one of the first and second data storage tiers to the other data storage tier based on the performance characteristics associated with the other data storage tier and the determined I/O activity. The data group is migrated to the other data storage tier in response to determining to migrate the data group to the other data storage tier.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 3, 2016
    Assignee: EMC Corporation
    Inventors: Dean D. Throop, Dennis T. Duprey, Miles de Forest, Michael D. Haynes
  • Patent number: 9268744
    Abstract: A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: February 23, 2016
    Assignee: Institute of Automation, Chinese Academy of Sciences
    Inventors: Shaolin Xie, Donglin Wang, Jie Hao, Tao Wang, Leizu Yin
  • Patent number: 9189240
    Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Lutz Naethke, Axel Borkowski, Bert Bretschneider, Kyriakos A. Stavrou, Rainer Theuer