Interleaving Patents (Class 711/157)
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Patent number: 7779215Abstract: A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.Type: GrantFiled: March 4, 2005Date of Patent: August 17, 2010Assignee: VIA Technologies Inc.Inventors: Ming-Shi Liou, Bowei Hsieh, Jiin Lai
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Patent number: 7778812Abstract: Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands to be generated in a different sequence from the sequence of generated write commands, having different sizes than the sizes of the write commands, and that maximize the amount of data read (verified) and minimize the amount of unnecessary reads (re-verification).Type: GrantFiled: January 7, 2005Date of Patent: August 17, 2010Assignee: Micron Technology, Inc.Inventor: Robert Hoffman, Jr.
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Publication number: 20100199025Abstract: A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit.Type: ApplicationFiled: September 14, 2009Publication date: August 5, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Nanjou, Tetsuya Murakami
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Patent number: 7769973Abstract: A method for deinterleaving a sequence of interleaved data stored in a set of memory locations from a first order to a second order in-place of a memory with linear time. Two data items are withdrawn from the center of the sequence, creating a hole therein. Destination positions for said withdrawn data items are determined. It is determined whether the destination positions contain any data items. If so, the data items of said destination positions are replaced with the withdrawn data items, and second destination positions are determined for the data items withdrawn from the first destination positions. Otherwise, the first data items are inserted at the destination positions directly. If a data item is inserted at the hole of the sequence before the sequence is properly deinterleaved, an incorrect positioned data item is determined and repositioned. The repositioning sequence is repeated until all data items are correctly positioned.Type: GrantFiled: September 29, 2004Date of Patent: August 3, 2010Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventor: Mats Svensson
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Publication number: 20100180089Abstract: A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.Type: ApplicationFiled: January 14, 2009Publication date: July 15, 2010Applicant: International Business Machines CorporationInventors: Diana Garza Flemming, Ghadir Robert Gholami, Octavian Florin Herescu, William A. Maron, Mysore Sathyanarayana Srinivas
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Patent number: 7757054Abstract: The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a microprocessor, a serial storage device, a first buffer, a second buffer, a memory control unit, and a multiplexer. The memory control system and the method to read data from memory according to the invention utilize the characteristics that the microprocessor reads data from continuous addresses of a serial memory during most of the time. By reading in advance and temporarily storing the data that the microprocessor requests to read, increasing the reading memory speed can be achieved.Type: GrantFiled: December 13, 2007Date of Patent: July 13, 2010Assignee: Etron Technology, Inc.Inventors: Chien-Chou Chen, Chi-Chang Lu
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Patent number: 7752379Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.Type: GrantFiled: January 6, 2009Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Ryan Abel Heckendorf, Tolga Ozguner
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Publication number: 20100165503Abstract: Disclosed are information recording/reading methods. The information recording method includes forming file data and metadata regarding the file data into recording information; dividing a predetermined recording medium into a plurality of zones when a recording mode is set; and recording file data and metadata, which are to be additionally recorded, in different zones.Type: ApplicationFiled: August 14, 2009Publication date: July 1, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Won-jong Choi, Du-il Kim, Ki-seok Chang
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Patent number: 7746944Abstract: An electronic transmitter device has a puncturing device with two data outputs and/or an interleaver with two data inputs. An electronic receiver device has a de-interleaver with two data outputs and/or a depuncturing device with two data inputs.Type: GrantFiled: January 8, 2003Date of Patent: June 29, 2010Assignee: Infineon Technologies AGInventors: Martin Bacher, Stefano Marsili
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Publication number: 20100156917Abstract: A method for managing a frame memory includes: determining a frame memory structure with reference to memory configuration information and image processing information; configuring a frame memory such that a plurality of image signals are stored in each page according to the frame memory structure; and computing a signal storage address by combining image acquiring information by bits, and accessing a frame memory map to write or read an image signal by pages.Type: ApplicationFiled: October 15, 2009Publication date: June 24, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hoo Sung LEE, Kyoung Seon Shin, Ig Kyun Kim, Suk Ho Lee, Sang Heon Lee, Seong Mo Park, Nak Woong Eum
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Publication number: 20100146229Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.Type: ApplicationFiled: December 4, 2008Publication date: June 10, 2010Applicant: LSI CorporationInventors: Shaohua Yang, Changyou Xu, Weijun Tan, Ching-Fu Wu, Yuan Xing Lee
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Publication number: 20100131810Abstract: Systems and methods for implementing a stride value for memory are provided. One embodiment relates to a system that includes a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. A memory test device is configured to perform a memory test that accesses a portion of the plurality of memory storage units in a sequence according to a programmable stride value. The memory test device performs the memory test by writing test data to each of the memory storage units in the portion of the plurality of memory storage units and reading the test data from each of the memory storage units in the portion of the plurality of memory storage units.Type: ApplicationFiled: January 27, 2010Publication date: May 27, 2010Inventors: LARRY J. THAYER, Andrew C. Walton, Mike H. Cogdill
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Patent number: 7725641Abstract: A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.Type: GrantFiled: June 1, 2007Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Gi-Ho Park, Shin-Dug Kim, Jung-Wook Park, Jun-Kyu Park, Sung-Bae Park
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Patent number: 7721066Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.Type: GrantFiled: June 5, 2007Date of Patent: May 18, 2010Assignee: Apple Inc.Inventors: Tse-yu Yeh, Daniel C. Murray, Po-Yung Chang, Anup S. Mehta
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Publication number: 20100115214Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.Type: ApplicationFiled: July 24, 2009Publication date: May 6, 2010Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Hong Beom PYEON
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Publication number: 20100106922Abstract: A first communication device estimates upstream channel conditions for an upstream channel and determines an upstream memory requirement for a first buffer at a second communication device and a first buffer at the first communication device based on the upstream channel conditions. A downstream memory requirement is received from the second communication device for a second buffer at the first communication device and a second buffer at the second communication device based on downstream channel conditions estimated at the second communication device for a downstream channel. The first communication device determines whether the sum of the upstream and downstream memory requirements exceeds an available amount of memory for implementing the first and second buffers at the first communication device and revises at least one of the memory requirements if the sum of the upstream and downstream memory requirements is different than the available amount of memory.Type: ApplicationFiled: December 31, 2009Publication date: April 29, 2010Applicant: LANTIQ DEUTSCHLAND GMBHInventor: Umashankar Thyagarajan
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Patent number: 7707370Abstract: An information processing device is provided with a plurality of memory channels, and performs interleave control on a unit memory connected to a memory channel. Furthermore, the information processing device has a circuit for performing the interleave control such that an interleave number on access to the unit memory connected to the memory channel can be constantly a multiplier of 2.Type: GrantFiled: December 20, 2006Date of Patent: April 27, 2010Assignee: NEC CorporationInventor: Norihiko Inoue
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Patent number: 7702860Abstract: A memory access apparatus for accessing a first memory and a second memory, includes: an address outputting unit configured to output a read address to at least one of the first and the second memories; an access request outputting unit configured to output a read request to at least one of the first and the second memories; a data information outputting unit configured to output an information on the data size, and an information on the address, of the read data; and a read data outputting unit configured to generate the read data to be output, from the data output from at least one of the first and the second memories in response to the read address and the read request.Type: GrantFiled: August 1, 2007Date of Patent: April 20, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Iwao Honda
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Patent number: 7694193Abstract: Systems and methods for implementing a stride value for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a plurality of memory storage units according to a predetermined interleave. The plurality of memory storage units can be defined by a memory range of consecutive addresses. The system also comprises a memory test device configured to access a portion of the plurality of memory storage units in a sequence that repeats according to a programmable stride value.Type: GrantFiled: March 13, 2007Date of Patent: April 6, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Larry J. Thayer, Andrew C. Walton, Mike H. Cogdill
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INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE RECORDING MEDIUM
Publication number: 20100083379Abstract: An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event.Type: ApplicationFiled: March 26, 2009Publication date: April 1, 2010Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTERInventors: Satoshi Katsunuma, Masahiro Goshima, Hidetsugu Irie, Ryota Shioya, Shuichi Sakai -
Publication number: 20100082917Abstract: A solid state storage system includes a memory area configured to include a plurality of chips, and a micro controller unit (MCU) configured to perform a control operation, such that continuous logical block addresses are allocated using a multi-plane method or an interleaving method to different chips, and a read/write operation is performed in the logical block address unit in response to a read/write command.Type: ApplicationFiled: December 29, 2008Publication date: April 1, 2010Inventors: Wun-Mo YANG, Jeong-Soon KWAK
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Patent number: 7689779Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.Type: GrantFiled: August 14, 2006Date of Patent: March 30, 2010Assignee: Micronas GmbHInventors: Matthias Vierthaler, Carsten Noeske
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Patent number: 7681023Abstract: A method according to the invention ensures optimal memory configuration in a computer: A determination is made whether performance can be improved by rearranging the DIMMs that are installed in the computer. If so, then a user of the computer is notified that the DIMMs can be rearranged to improve performance.Type: GrantFiled: April 30, 2004Date of Patent: March 16, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert J. Volentine, Mark A. Piwonka, Patrick L. Gibbons
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Patent number: 7676640Abstract: An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control code for the flash memory system (flash card) are stored in the flash memory device during a programming procedure. The flash controller transfers the boot code and control code to a volatile main memory (e.g., random access memory or RAM) at start up or reset making a RAM-based memory system. Boot code and control code are selectively overwritten during a code updating operation. A single flash controller thus supports multiple brands and types of flash memory to eliminate stocking issues.Type: GrantFiled: September 28, 2007Date of Patent: March 9, 2010Assignee: Super Talent Electronics, Inc.Inventors: David Q. Chow, Charles C. Lee, Frank I-Kang Yu, Edward W. Lee, Ming-Shiang Shen
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Publication number: 20100049908Abstract: In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.Type: ApplicationFiled: October 30, 2009Publication date: February 25, 2010Inventors: Carlos J. Gonzalez, Mark Sompel, Kevin M. Conley
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Patent number: 7669014Abstract: A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port memory blocks form a storage array for storing at least one input matrix and outputting the at least one input matrix in transposed form. A data input is provided to receive a plurality data words on each cycle and a data output is provided to output a plurality of data words on each cycle. A read address logic is provided to generate read addresses such that one cell of each dual port memory block can be read out on each cycle. A write address logic is provided to generate write addresses such that one cell k of each dual port memory block can be written on each cycle. In each cycle, one storage cell of each dual port memory block is addressed by the read address logic. The data words stored in the addressed storage cells are read out from one dual port memory block and outputted through the data output.Type: GrantFiled: July 23, 2007Date of Patent: February 23, 2010Assignee: Nokia CorporationInventor: Jarno Mikael Tuominen
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Patent number: 7664922Abstract: When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 sequentially transfers data to be recorded to a memory controller 160 that records data in memory having a plurality of banks. A selector 174 selects any DMAC 170 from among a plurality of DMACs, irrespective of priority sequence of transfer service for the DMAC. A transmitter 176 transmits, to a control-side transfer unit 114, data requested to be transferred by the selected DMAC 170. The selector 174 selects consecutively the DMAC 170 so that the transfer service for the same DMAC is consecutively executed, and determines the number of consecutive selections so that a transfer across the banks of the DMAC 170 occurs by a plurality of the transfer services.Type: GrantFiled: May 11, 2006Date of Patent: February 16, 2010Assignee: Sony Computer Entertainment Inc.Inventors: Katsushi Ohtsuka, Nobuo Sasaki
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Publication number: 20100030980Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.Type: ApplicationFiled: December 25, 2007Publication date: February 4, 2010Applicant: PANASONIC CORPORATIONInventors: Takashi Yamada, Daisuke Imoto, Koji Asai, Nobuyuki Ichiguchi, Tetsuji Mochida
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Publication number: 20100023711Abstract: According to one embodiment, memory is allocated between an interleaver buffer and a de-interleaver buffer in a communication device based on downstream and upstream memory requirements. The upstream de-interleaver memory requirement is determined based on upstream channel conditions obtained for a communication channel used by the communication device. The memory is allocated between the interleaver and de-interleaver buffers based on the downstream and upstream memory requirements. The downstream interleaver memory requirement may be determined based on one or more predetermined downstream configuration parameters. Alternatively, the downstream interleaver memory requirement may also be determined based on the upstream channel conditions by estimating the downstream capacity of the communication channel based on the upstream channel conditions and determining an interleaver buffer size that satisfies one or more predetermined downstream configuration parameters and the downstream capacity estimate.Type: ApplicationFiled: July 28, 2008Publication date: January 28, 2010Applicant: INFINEON TECHNOLOGIES AGInventor: Umashankar Thyagarajan
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Patent number: 7650474Abstract: Method and system for dividing a data segment of unknown length into first and second halves, for example, for interleaving the first and second halves. Units of the data segment are written into first and second register files. With respect to the first register file, responsive to determining that the last unit of the data segment has been written into the first register file, units of the data segment in the first register file that are not units of the first half of the data segment are removed, wherein the first register file stores the first half of the data segment.Type: GrantFiled: December 19, 2006Date of Patent: January 19, 2010Assignee: LSI CorporationInventors: Jackson Lloyd Ellis, Ori Ron Liav
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Publication number: 20100011176Abstract: A method and system are provided for executing a binary bulk input/output (IO) operation on a first virtual disk and a second virtual using interleaving. The performance improvement due to the method is expected to increase as more information about the configuration of the virtual disks and their implementation are taken into account. Aspects of a binary bulk IO operation, which distinguish it from a unary bulk IO operation, are collection of information regarding both virtual disks and consideration of performance factors on both virtual disks, individually and jointly. Performance factors considered may include contention among tasks implementing the parallel process, load on the storage system(s) from other processes, performance characteristics of components of the storage system(s), and the virtualization relationships (e.g., mirroring, striping, and concatenation) among physical and virtual storage devices within the virtual configuration.Type: ApplicationFiled: July 11, 2008Publication date: January 14, 2010Inventor: Todd R. Burkey
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Publication number: 20100002792Abstract: A data transmission system respectively encodes successive bits representing information to be transmitted. An interleaver receives the bits from the encoder and interleaves the bits. The interleaver includes a memory and a memory read write controller configured to write the bits to the memory in accordance with a diagonal write pattern and to read the bits from the memory in a diagonal read pattern. A symbol mapper receives the interleaved bits and maps the encoded interleaved bits into symbols using a transmission format.Type: ApplicationFiled: January 16, 2008Publication date: January 7, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventor: Seyed-Alireza Seyedi-Esfahani
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Patent number: 7644340Abstract: A circuit is provided for performing interleaving and deinterleaving functions in a digital communication system. The circuit includes a single-port memory that reads first data units from a first interleaved sequence of address locations to generate a first data stream and that writes second data units from a second data stream to the address locations. A first address generator module communicates with the single-port memory and generates a first interleaved sequence of addresses that correspond to the address locations and correspond to one of an interleaving function and deinterleaving function between the first data stream and the second data stream.Type: GrantFiled: February 24, 2006Date of Patent: January 5, 2010Assignee: Marvell International Ltd.Inventor: Peter Tze-Hwa Liu
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Patent number: 7644120Abstract: A method and process control data server system architecture are disclosed for providing process data to a variety of client applications via a plurality of differing data sharing standards. The system architecture incorporates a ready platform for subsequently added client application data exchange protocols. In an exemplary embodiment, a set of standard interface definitions between client application data exchange protocol-specific plugins and a data access server engine supports incorporating new client application data exchange protocols by means of plugins designed to interface with the data access server engine according to the standard interface definitions.Type: GrantFiled: September 14, 2001Date of Patent: January 5, 2010Assignee: Invensys Systems, Inc.Inventors: Ivan A. Todorov, Louis D. Ross, Michael Hadrich, Rainer Hessmer
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Patent number: 7640479Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.Type: GrantFiled: March 3, 2008Date of Patent: December 29, 2009Assignee: LSI CorporationInventor: Qiang Shen
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Patent number: 7640413Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.Type: GrantFiled: March 20, 2007Date of Patent: December 29, 2009Assignee: Micron Technology, Inc.Inventor: Simon J. Lovett
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Patent number: 7636817Abstract: Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure. Memory is divided into blocks having sequential addresses based on the number of simultaneous memory access specified, e.g. base addresses at A, A+B, A+2B, A+3B. Individual slave side arbiters are assigned to each block of memory. Addresses for memory accesses associated with master components or master ports are modified to allow simultaneous access to multiple memory locations.Type: GrantFiled: April 18, 2006Date of Patent: December 22, 2009Assignee: Altera CorporationInventor: Jeffrey Orion Pritchard
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Publication number: 20090300299Abstract: Methods and apparatus provide for a Dynamic Interleaver to modify the interleaving distribution spanning physical memory modules. Specifically, dynamic interleaving provides the ability to increase the number of interleaved physical memory modules when a current interleaved group of memory locations is experiencing heavy use. By increasing the number of interleaved memory locations, a system can make optimal use of memory by allowing more parallel accesses to physical memory during the period of heavy utilization. However, if the current interleaved group of memory locations experience low use, the Dynamic Interleaver can choose to interleave across fewer physical memory modules and apply power management techniques to those memory locations that are no longer being accessed. Prior to “re-interleaving” interleaved memory locations, the Dynamic Interleaver migrates data out of the current interleaved memory locations.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Eric C. Saxe, Sherry Q. Moore, Darrin P. Johnson
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Publication number: 20090300300Abstract: Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the ISDB-T receiver that performs both time and frequency de-interleaving of the interleaved data and a buffer address calculation module for generating buffer address in the buffer. The system performs memory sharing of the time and frequency de-interleaver for ISDB-T receivers and reduces the memory size required for performing de-interleaving in an ISDB-T receiver and combines the frequency and time de-interleaver buffers into one RAM thereby reducing the memory size.Type: ApplicationFiled: June 2, 2008Publication date: December 3, 2009Applicant: Newport Media, Inc.Inventor: Philip Treigherman
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Patent number: 7627712Abstract: A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and represents a second block from a second plane of the multi-plane solid state memory device.Type: GrantFiled: March 22, 2005Date of Patent: December 1, 2009Assignee: Sigmatel, Inc.Inventors: Richard Sanders, Josef Zeevi
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Patent number: 7620784Abstract: Described is a high speed nonvolatile memory device and technology that includes a controller coupled via interfaces to sets of nonvolatile storage, such as separate flash memory chips or separate regions of a single chip. The controller includes logic that processes write requests of arbitrary size, by interleaving writes among the interfaces, including by parallel writing among the interfaces. For example, the data may be received via direct memory access (DMA) transfers. The controller maintains information to allow the interleaved data to be reassembled into its correct relative locations when read back, such as by DMA. The high speed nonvolatile memory device thus provides a hardware device and software solution that allows a personal computer to rapidly boot or resume from a reduced power state such as hibernation. The high speed nonvolatile memory device also may be used for other data storage purposes, such as caching and file storage.Type: GrantFiled: June 9, 2006Date of Patent: November 17, 2009Assignee: Microsoft CorporationInventor: Ruston Panabaker
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Patent number: 7620710Abstract: Systems and methods for allocating transmission resources within a computer network are provided. In some embodiments of the invention, communication links may be assigned based on predefined preferences or system configuration to facilitate the transfer of data from one point in the network to another. In other embodiments, system operation may be monitored and communication paths be assigned dynamically based on this information to improve system operation and provide improved failover response, load balancing and to promote robust data access via alternative routes.Type: GrantFiled: December 19, 2005Date of Patent: November 17, 2009Assignee: CommVault Systems, Inc.Inventors: Rajiv Kottomtharayil, Ho-Chi Chen, Manoj Vijayan Retnamma
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Patent number: 7617367Abstract: A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.Type: GrantFiled: June 27, 2006Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: John E. Campbell, Kevin C. Gower
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Patent number: 7613866Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.Type: GrantFiled: August 10, 2004Date of Patent: November 3, 2009Assignee: Thomson LicensingInventors: Tim Niggemeier, Thomas Brune
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Patent number: 7610457Abstract: An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are sequentially calculated according to a predetermined process, and reading data stored at read address values of the memory which are sequentially calculated according to a predetermined process, wherein the memory has N data banks, each data bank has M storage spaces, and there are D interleaving target data having data numbers A, and the storing data operation includes storing the data at storage spaces of the data banks, the storage spaces corresponding to integer values and the data banks corresponding to remainders obtained by dividing the data numbers A by results of dividing a total number of data D by the number of storage spaces M.Type: GrantFiled: July 13, 2006Date of Patent: October 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Jeong-sang Lee
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Publication number: 20090265513Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: ApplicationFiled: June 25, 2009Publication date: October 22, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Dong-Ryul RYU
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Patent number: 7603512Abstract: A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a master device. The scheduler reorders the requests from the master device based on priorities assigned to the master device or provides information about following requests. The refresh control unit determines a refresh timing of the dynamic memory based on the existence of the following requests and an idle state of banks constituting the dynamic memory. Accordingly, the dynamic memory refresh controller may maximize a refresh trigger interval by changing the management order of the requests from the master device based on the priority of the response latency.Type: GrantFiled: February 20, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Yoon-Bum Seo
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Patent number: 7602512Abstract: Secrecy of printed matter is raised and charges for a storing area are more accurately charged. According to the invention, a printing apparatus is instructed so as to store print data corresponding to a print request into one of a plurality of storing areas. The print data is transmitted to the printing apparatus. The user is notified of authentication information corresponding to the print data stored in one of the plurality of storing areas.Type: GrantFiled: March 18, 2003Date of Patent: October 13, 2009Assignee: Canon Kabushiki KaishaInventor: Kazutaka Matsueda
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Publication number: 20090248998Abstract: A storage system includes: N pieces of storages that stores electronic information, N being an integral number that is two or more; and a controller that obtains electronic information to be written, wherein the controller, in a case where the electronic information to be written is a first kind of electronic information, divides the electronic information to be written into N pieces, and independently writes the divided electronic information into each of the N pieces of storage, and the controller, in the electronic information to be written is a second kind of electronic information, redundantly writes the electronic information to be written into each of the N pieces of storage.Type: ApplicationFiled: August 26, 2008Publication date: October 1, 2009Applicant: FUJI XEROX CO., LTDInventors: Jun SATO, Shohei Ikenoue, Kentaro Fukami, Akiyoshi Osugi
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Publication number: 20090248997Abstract: A de-interleaver for receiving data blocks including data units in an interleaved order, each data unit having a de-interleaved location within the data block, placing the data units in a memory buffer, and outputting the data units in a de-interleaved order from the memory buffer, the de-interleaver including an output unit configured to output a data unit from a location in the memory buffer of a next data unit in de-interleaved order, thereby to provide the data block in de-interleaved order, and an input unit configured with the output unit to input an incoming data unit, the incoming data unit being in the interleaved order, into the location in the memory buffer vacated by the next, in de-interleaved order, data unit being output. Related apparatus and methods are also described.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicant: Horizon Semiconductors Ltd.Inventor: Moshe Ben-Ari