Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: A method for second interleaving is disclosed. The method comprises: generating an interleaving address preset in an interleaving matrix for each input data, and writing the data into the interleaving matrix according to the interleaving address; initializing the interleaving address and reading out the data from the interleaving matrix according to the interleaving address; judging whether the reading operation on a column of data in the interleaving matrix is completed or not, if completed, then calculating the interleaving address of the next column in the interleaving matrix according to inter-column replacement rules; otherwise, obtaining the interleaving address by adding its own value to the column spacing; judging whether the reading operations on all data are completed or not, if completed, then the second interleaving ending; otherwise, returning to the step of reading out the data from the interleaving matrix according to the interleaving address, and repeating the above operation.

Abstract: A method and apparatus for rate matching is described. During operation of a transmitter, multiple data streams are received and individually interleaved with a permutation of a same length K?. A permutation (?p0) of a second stream is the same as a permutation (?sys) of a first stream and a permutation (?p1) of a third stream is different from the permutation of the first stream. Each element of ?p1 is derived from the corresponding element of ?sys. The plurality of interleaved streams are multiplexed to form a circular buffer. Finally, data is transmitted from the circular buffer.

Abstract: A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port.

Abstract: A redundant controller storage virtualization subsystem performing host-side IO rerouting and dynamic logical media unit reassignment. In one embodiment, the assignment of logical media unit owner can be dynamically reassigned to the receiving storage virtualization controller which was originally not the logical media unit owner such that the receiving storage virtualization controller becomes new logical media unit owner to execute the IO request. In another embodiment, the dynamic logical media unit reassignment can be performed according to the operating condition(s) of the storage virtualization system so as to improve the performance of the storage virtualization system. In a further embodiment, the controller storage virtualization subsystem can perform host-side IO rerouting when the timing for performing dynamic logical media unit reassignment is not reached.

Abstract: According to one embodiment, a memory system includes a first memory chip includes a first temporary memory and a first block, a second memory chip includes a second temporary memory and a second block, and a memory controller that controls writing of logical pages to the first and second memory chips. The memory controller forms a second unit having the same page number as the first unit by the first temporary memory and the lowermost physical page in the first block, forms a third unit having the same page number as the first unit by the second temporary memory and the lowermost physical page in the second block, and writes the logical pages by an interleave operation in order of the second unit, the third unit, the first unit in the first block, and the first unit in the second block.

Abstract: A method and system for operating a computer system are disclosed. In at least some embodiments, the present invention relates to a method of operating a computer system that includes operating a first cell of the system in accordance with a first memory access configuration, and migrating a first attribute of a first core of the first cell to a second cell of the system. The method additionally includes configuring a portion of the first cell so that the first cell is capable of operating in accordance with a second memory access configuration, and migrating at least one of the first attribute and a second attribute from the second cell back to the first core of the first cell, whereby subsequently the first cell operates in the second mode of operation. In at least some embodiments, the first and second configurations are direct and agent access memory configurations, or vice-versa.

Abstract: A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is obviated. Each evaluation cycle performed by the reduced complexity PSV generator is modified by each primitive root of the desired discrete power series. For each PSV generated, a corresponding address is calculated to indicate the correct placement of the PSV generated.

Abstract: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Abstract: A method for writing an audio/video information stream to an optical disc, and for reading the information from disc. The information stream includes alternative video parts which are recorded in an interleaved manner; an interleaved unit includes angle blocks, each angle block including one portion of each of the alternative video stream parts. For each video portion, entry points are defined. A user is allowed to change from one video stream to another video stream at any moment during the playback of a video portion; the change will be effected at the first entry point after the user command. Thus, it is not necessary to wait until the video portion has been completely played back; thus, it is possible to define large angle block lengths, so that during normal play the jump frequency is reduced.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock.

Abstract: A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the nonvolatile memory devices, and interleaving units are formed by memory cell regions having different programming times.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: A set of data is allocated into a plurality of data chunks, wherein the plurality of data chunks is thinly provisioned and erasure coded. A plurality of storage devices is divided into a first and a second set of storage devices, wherein the first set of storage devices is powered up and the second set of storage devices is powered down. The data chunks are distributed on the first set of storage devices to equally load each of the first set of storage devices. A storage device from the second set of storage devices is powered up to reassign the storage device from the second set of storage devices to the first set of storage devices. Data chunks are migrated to a reassigned storage device until the data chunks are evenly distributed on the first set of storage devices and the reassigned storage device.

Abstract: A data processing system includes a storage system and caching storage controllers coupled to the storage system and to a storage network. The storage controllers operate in an active-active fashion to provide access to volumes of the storage system from any of the storage controllers in response to storage commands from the storage network. The storage controllers employ a distributed cache protocol in which (a) each volume is divided into successive chunks of contiguous blocks, and (b) either chunk ownership may be dynamically transferred among the storage controllers in response to the storage commands, or storage commands sent to a non-owning controller may be forwarded to the owning controller.

Abstract: Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a fraction of the address fragments generated, which potentially will exceed a maximum allowable value, is compared to the maximum allowable value. If the compared address fragment exceeds the maximum allowable value it is discarded. If the compared address fragment does not exceed the maximum allowable value it is accepted.

Abstract: Provided are a multi-channel flash memory system capable of increasing the overall bandwidth by using a plurality of flash memory chips, and a programming method performed in the flash memory system. The flash memory system includes: a plurality of channel units each including at least two flash memory chips, a control unit which controls the flash memory chips, and a buffer unit which stores external data; and a host interface unit which transmits data separated according to the number of the channel units and transmitted by a host to the buffer units of the channel units, wherein the control unit records the data stored in the buffer unit into the at least two flash memory chips.

Abstract: A method and apparatus for turbo encoding with a contention-free interleaver is provided herein. During operation an input block of size K? is received. The original input block and the interleaved input block are encoded to obtain a codeword block, wherein the original input block is interleaved using an interleaver of size K? and a permutation ?(i)=(f1×i+f2×i2)mod K?, where 0?i?K??1 is the sequential index of the symbol positions after interleaving, ?(i) is the symbol index before interleaving corresponding to position i, K? is the interleaver size in symbols, and f1 and f2 are the factors defining the interleaver. The values of K?, f1, f2 are taken from at least one row of a table. The codeword block is transmitted through the channel.

Abstract: Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.

Abstract: According to one embodiment, an interleave control device of a memory system includes a memory divided into sections, and a data bus used, in common, for data transfers for the sections, the device comprises a detector and a start module. The detector is configured to detect a transfer of data of a predetermined size during a transfer of data on the data bus to be written to a certain section of the memory or data read from the section. The start module is configured to start a transfer of interleave control data in place of the data to be written or the read data when the detector detects the transfer of the data of the predetermined size.

Abstract: A method and device for copying-back data in a multi-chip flash memory device having first and second memory chips. The method may include reading first source data from a first source region of one of the memory chips; programming the first source data into a target region included in one of the memory chips and reading second source data from second source region of the other memory chip different from the memory chip including the target region. Reading the second source data may be carried out while programming the first source data.

Abstract: Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operating mode. Examples of operating modes may include (1) reading or writing to flash memory when connected to an external power source, (2) reading from flash memory when powered by portable power source (e.g., battery), and (3) writing to flash memory when powered by a portable power source.

Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Abstract: Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page.

Abstract: The present invention provides a data interleaving method for a storage device and a related storage device. The storage device comprises a plurality of non-volatile memory units, a buffer, and a processing unit. The method comprises: transmitting a plurality of first data required to be written to the plurality of non-volatile memory units to the buffer one by one; and respectively performing a plurality of interleaving operations to transmit the plurality of first data received by the buffer in sequence to the plurality of non-volatile memory units, respectively. The data interleaving method and the related storage device of the present invention only has to use one buffer, and thus the data interleaving method and the related storage device of the present invention can reduce requirement of buffer memory.

Abstract: A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.

Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.

Abstract: A storage apparatus includes one or more memory units each having a plurality of memory blocks to store a file having data corresponding to a plurality of clusters, and a controller to store the file in the memory units such that such that the data of at least two sequential addresses of the clusters are stored in the memory blocks of different memory units.

Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

Abstract: A data storing system including: a non-volatile memory configured to have a plurality of memory blocks each capable of independently operating and allow random access to each of addresses; a controller configured to control writing of data to the non-volatile memory; and an executing unit configured to execute a predetermined application, wherein the executing unit decides the number of interleaves indicating the number of memory blocks operated in parallel among the plurality of memory blocks, and the executing unit notifies the controller of the decided number of interleaves.

Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element

Abstract: High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.

Abstract: One exemplary memory control method of a memory device includes: determining at least a physical row partition including a plurality of physical rows selected from the memory device; and for each physical row partition, mapping interleaved virtual rows to the selected physical rows. Each physical row partition is a portion of the memory device. Bank addresses of adjacent virtual rows are different. Another exemplary memory control method of a memory device includes: assigning an indicator to each physical row partition in the memory device for indicating if the corresponding physical row partition is to be refreshed; and controlling a partial refresh operation of the memory device according to the indicator of each physical row partition. Each physical row partition is a portion of the memory device.

Abstract: A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode.

Abstract: A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.

Abstract: Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set of storage units has been coupled to the controller. The plurality of extents are distributed among all storage units included in the first set of storage units and the second set of storage units.

Abstract: A method for arbitrating between a plurality of access requests issued in relation to a resource by a plurality of requestors, wherein each request can be one of at least two types, a first of the types having a higher latency associated with its performance than at least some of the other types, the method including the steps of: (a) receiving a plurality of the access requests; (the requests are not placed anywhere, they are simply received); (b) maintaining a current pointer that points to a current timeslot in a timeslot list, and at least one lookahead pointer that points to a future timeslot in the timeslot list; and (c) in the event an access request as arbitrated via the lookahead pointer is of the first type, initiating performance of the access request earlier than the position in the list suggests it would be performed should it be started when the current pointer reached the timeslot.

Abstract: A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the memory array at a second number of writes per unit time; and skewing expected wearout times of the memory devices by making the second number of writes per unit time less than the first number of writes per unit time. A method in another embodiment includes writing first data to a first memory device of a memory array; writing second data to a second memory device of the memory array; and skewing expected wearout times of the memory devices by making a number of available storage units cm the second memory device less than a number of available storage units on the first memory device.

Abstract: Provided is a system and method for de-interleaving a data stream stored in a buffer having a plurality of memory locations. Each location has a memory width of (W) bytes and the data stream is formed of a number of data words each including (N) number of data bytes, and (N) is a non-integer multiple of the width (W). The method includes storing the data words into respective memory locations and appending each of the stored data words with number (X) of dummy bytes, a sum of (N)+(X) being an integer multiple of the width (W). The appended dummy bytes are then stored in the respective memory locations.

Abstract: An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.

Abstract: Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.

Abstract: A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

Abstract: Methods and apparatus for interleaving data in a multitrack tape drive and for writing data on a multitrack tape in the tape drive. One method includes: partitioning the data into m(2n+k) data blocks, where each data block has a logical array of rows and columns of data bytes; error-correction coding a row and a column of the logical array to produce an encoded block; assigning the coded row to a respective location in a logical interleave array having L rows and 2n+k columns of locations; and writing a sequence of assigned coded rows simultaneously in respective data tracks on the multitrack tape. The coded row is assigned such that the minimum Euclidean distance on the multitrack tape between the coded rows is maximized. The apparatus includes units for performing the methods and the computer program product includes a program code means for causing a computer to perform the methods.

Abstract: A memory system includes multiple processors. The memory system includes first and second processors, a storage device and a controller. The storage device includes one or more banks which are respectively allocated to the first processor or the second processor. The controller controls the storage device to access a plurality of banks through an interleaving method when the plurality of banks are allocated to one processor. The memory system can improve performance and power efficiency.

Abstract: The present invention comprises an interleaver that uses a reduced interleaving table to generate interleaved output data blocks from input data blocks. By iteratively applying the reduced interleaving table to bits in the input data blocks, the interleaver generates output data blocks equivalent to those that would have been generated using a full-size interleaving table. According to one embodiment of the present invention, the interleaving circuit includes a grouping circuit, a permuting circuit, and a mapping circuit. The grouping circuit groups the bits of each data block into a plurality of sub-blocks, while the permuting circuit independently permutes the data bits in each sub-block using the reduced interleaving table to generate permuted sub-blocks. The mapping circuit maps the bits from each permuted sub-block to one or more output data blocks, where the bits in each output data block may comprise bits from different sub-blocks and/or different input data blocks.

Abstract: A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.

Abstract: Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operating mode. Examples of operating modes may include (1) reading or writing to flash memory when connected to an external power source, (2) reading from flash memory when powered by portable power source (e.g., battery), and (3) writing to flash memory when powered by a portable power source.

Abstract: A memory system that disperses memory addresses of strings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer. The memory is configured to store strings of data. The CPU is configured to direct the storing and retrieving of the strings of data from the memory at select memory addresses. The address randomizer is coupled between the CPU and the memory. Moreover, the address randomizer is configured to disburse the strings of data throughout locations of the memory by changing the select memory addresses directed by the CPU.

Abstract: A storage device is provided. The storage device includes a memory that includes interleaved fast and slow pages and a controller. In response to a command from a host of the storage device the controller stores fast-reading data in the memory. If the fast and slow pages alternate, the controller stores the fast-reading data in the first pages alternately with filler data in the low pages, and if contiguous pluralities of the fast and slow pages alternate, the controller stores the fast reading data in the contiguous pluralities of the fast pages alternately with the filler data in the contiguous pluralities of the slow pages.

Abstract: An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B?1) each addressing more than one and less than all of the memory banks. The interleaves are offset (S) from each adjacent other as to address all of the memory banks equally. An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.