Abstract: The adaptive sequential pattern memory search technique only examines the contents of a subset of the total number of memory locations in each search for information representative of a character string. The subset includes a plurality of storage locations and each examination is performed in one concurrent read operation. If the character string is not matched, the memory must be updated to store information representative of the unmatched string. This updating process selects one location from the subset for storing this representative information. Advantageously, an indicator of when each stored representative information last matched a character string is maintained and utilized in the selection process. In addition, to avoid operational errors associated with outputting invalid information from the "child" of a previously discarded "parent", an indication of the time each stored entry is created is utilized to remove such invalid information as it is detected in the updating process.

Abstract: A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number. The location in the cache of an item that includes a first key is determined by supplying the first key to a lockless-lookup engine which then provides a lookup output that is alternatively a lookup entry number or an indication that the item is not stored in the cache. The lookup entry number is alternatively a first or second entry number, wherein the first entry number points to a first entry in which the item is stored and the second entry number points to a second entry in which the item is not stored. If the lookup output is the lookup entry number, then it is verified that the lookup entry number is the first entry number.

Abstract: A plurality of data storage media which are constructed in a hierarchical structure of a plurality of levels having different access times and have different access information items are provided, a data storage medium into which data is to be stored is selected according to the access frequency of data, and data is stored according to the result of selection. At the time of data relocation between the data storage media of different hierarchies or between the data storage media of the same hierarchy, one of a plurality of relocation measures is selected according to the characteristics of the data storage media and the characteristic of data to be stored and then data is relocated according to the selected relocation measure.

Abstract: An expandable-set, tag, cache circuit for use with a data cache memory comprises a tag memory divided into a first set and a second set for storing, under a single address location, first and second tag fields representative of first and second data, respectively. The tag memory also stores first and second signals representative of which of the sets is the least recently used. A comparator is responsive to a tag field of an address representative of requested data as well as to a first tag field output from the tag memory for producing an output signal indicative of a match therebetween. A second comparator is responsive to the same tag field of the address and to a second tag field output from the tag memory for producing an output signal indicative of a match therebetween. A first logic gate is responsive to the first and second comparators for producing an output signal indicative of the availability of the requested data in the data cache memory.

Abstract: A cache memory system has an address register for storing a tag address and an index address of data to be accessed, a plurality of data memories for storing data corresponding to said index address, a plurality of tag memories corresponding to said data memories for storing tag addresses relating to said data stored in said data memories, and tag comparators corresponding to said tag memories for comparing a tag address stored in said tag memories with the tag address stored in the address register and for determining whether a cache hit has occurred or a cache miss has occurred. A reference frequency information register stores information indicating a tag memory which has resulted in a cache hit. An access control circuit selects one of the tag memories and one of the comparators corresponding to the selected tag memory based on the information from the reference frequency information register.

Abstract: A disk cache operation which was optimized so as to adapted to an operation form of the user and a disk array is executed. A cache mechanism is provided for each of two sets of controllers and can be made operative in either one of the reliability significance mode for storing the same data into each system, the performance significance mode for independently storing data every system, and the average mode of both of said modes. A cache process in which a disk array which operates in RAID0, RAID1, RAID3, or RAID5 is set to a target is efficiently executed. Effective data is prepared on a cache block so as to enable an access like RAID3 such that a parity can be calculated without needing to read the disk even in the operation of RAID5.

Abstract: A hierarchical memory system having a cache memory for storing a portion of data stored in a main memory. The cache memory is divided into hierarchically ordered primary and secondary cache memories. The primary cache memory being connected to a processor. The larger secondary cache memory being connected to the primary cache memory and to a bus connected to the main memory. When a cache miss-hit is made in the secondary cache memory, at the time of access by the processing unit, the secondary cache memory notifies the primary cache memory of an address of a replacement entry prior to seeking a data transfer. The primary cache memory, when it has an entry corresponding to the replacement entry, makes the corresponding entry the replacement entry.

Abstract: A multi-tier cache system and a method for implementing the multi-tier cache system is disclosed. The multi-tier cache system has a small cache in random access memory (RAM) that is managed in a Least Recent Used (LRU) fashion. The RAM cache is a subset of a much larger non-volatile cache on rotating magnetic media (e.g., a hard disk drive). The non-volatile cache is, in turn a subset of a local CD-ROM or of a CD-ROM or mass storage device controlled by a server system. In a preferred embodiment of the invention, a heuristic technique is employed to establish a RAM cache of optimum size within the system memory. Also in a preferred embodiment, the RAM cache is made up of multiple identically-sized sub-blocks. A small amount of RAM is utilized to maintain a table which implements a Least Recently Used (LRU) RAM cache purging scheme. A hashing mechanism is employed to search for the "bucket" within the RAM cache in which the requested data may be located.

Abstract: There is provided a disk array apparatus designed to realize high-speed recovery processing in occurrence of an error while preventing a reduction in total storage capacity due to the use of parity disks. A disk with a high access frequency is set in a group constituted by a small number of disks, whereas a disk with a low access frequency is set in a group constituted by a large number of disks. In a group constituted by a small number of disks, since the number of disks used for recovery is small, the disk access frequency in recovery processing becomes low, and high-speed recovery processing can be realized. In a group constituted by a large number of disks, since the ratio of the parity disk capacity to the total capacity is low, a reduction in disk capacity is small.

Abstract: A method and apparatus for replacing data in a list of buffers is provided. The list of buffers has a hot end and a cold end. The buffers at the hot end are maintained in a FIFO list and the buffers at the cold end are maintained in an LRU list. Requested data is located and, if the requested data is located in the LRU portion of the buffer list, the buffer containing the requested data is moved to the head of the FIFO list. If the data is located in a buffer in the FIFO portion of the buffer list, no rearrangement is required. If the requested data is not located in the buffer list, the data is stored into the buffer at the tail end of the LRU list, then the buffer is moved to the head of the FIFO list.

Abstract: A data processor (10) has a cache array (40) and a control unit (58) for storing a number of recently accessed data lines. If an execution unit requests a data line that is not stored in the memory cache (a miss) then the control unit will request the data from an external memory device and allocate a location in the cache array in which it will store the requested data when returned. In the depicted embodiment, the control unit first attempts to allocate an invalid one of N possible locations, where N is the set way associativity of the memory cache. If none of the ways is invalid, then the control unit uses a least recently used (LRU) algorithm to select the location. Therefore, the data cache may be non-blocking up to N times to the same set.

Abstract: A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15) If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).

Abstract: A computer system and associated method for executing a plurality of threads of execution with reduced memory space requirements. The computer system comprises a memory, an execution controller, and a data compressor. The execution controller controls execution of the threads such that the threads are executable and unexecutable at different times. The execution controller also stores uncompressed into available space in the run-time memory execution data of the threads when the execution data is generated. The data compressor compresses the uncompressed execution data of compressible ones of the threads that are unexecutable. As a result, space is made available in the run-time memory. The data compressor also decompresses in available space in the run-time memory the compressed execution data of decompressible ones of the threads so that the decompressible ones of the threads may be executed after becoming executable.

Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.

Abstract: A method and apparatus are provided for adaptive localization of frequently accessed, randomly addressed data in a direct access storage device (DASD) to achieve improved system access performance. At selected sampling intervals, a DASD storage controller analyzes data access patterns based on frequency of access, identifies a remapping algorithm to remap the logical groups to physical groups, and moves the physical groups according to the identified remapping algorithm. The data reordering on the DASD provides frequently accessed data in close proximity so that seek time is minimized. The adaptive data localization method periodically performed by the storage controller is transparent to the host file system. The reordering of the data on the DASD is performed during periods of low system data transfer activity.

Abstract: A cache management system and method monitors and controls the contents of cache memory. A time indication provider provides a time indication signal to a cache indexer, for maintaining a cache index which are stored in cache as well as an indication that a data element must be written to a longer term data storage device. A cache manager is responsible for placing data elements into and removing data elements from the cache memory. The cache manager is responsive to at least one data element stored in cache which must be written to a longer term data storage device, and to the associated time indication, for determining the amount of time that the data element has been stored in cache as well as the average period of time that elapses between a data element being inserted in cache and being removed from cache.

Abstract: A cache memory includes: a plurality of tag memory blocks, each of which stores multiple compare addresses; a first bus which sends a low order address to all of the tag memory blocks; a respective output from each tag memory block on which a compare address is read in response to the low order address; a second bus which carries a high order address; and, a comparator circuit which generates a miss signal when the compare address on the output from every tag memory block miscompares with the high order address. Each tag memory block further stores respective control bits with each compare address; and each tag memory block responds to the low order address by reading the compare address and the respective control bits, in parallel, on its respective output.

Abstract: An n-way set-associative cache (where n is an integer greater than 1), includes a replacement mechanism for selecting a cache line for replacement. Each cache line has an associated priority tag indicating a user-defined priority for that cache line The replacement mechanism comprises an apparatus for selecting a cache line with the lowest user-defined priority in a current set of cache lines, and apparatus (e.g. based on recency of usage) for choosing between cache lines of equal priority if there is more than one cache line with said lowest user-defined priority in the current set.

Abstract: According to the present invention, faulty lines of data of a set associative cache memory containing one or more faulty data bits which are not repairable through conventional repair means such as row/column redundancy, are not updated following a cache miss condition and thereby effectively bypassed. Replacement logic circuitry detects and controls the state of a replacement status bit associated with each line of data of the set associative cache memory to determine if the line of data in the cache should be updated or bypassed. Thus, when replacing a line of data, the replacement logic circuitry detects the address of a faulty line of data in a particular set and avoids updating that faulty line of data in favor of updating another line of data of another set.

Abstract: A method of caching I/O requests permits caching in the MVS environment independent of the access method protocol used to initiate an I/O request (e.g., QSAM, VSAM, Media Manager). In addition, objects can be user-prioritized for residence in the cache.