Entry Replacement Strategy Patents (Class 711/159)
  • Patent number: 11983606
    Abstract: Disclosed are a method and device for constructing a quantum circuit of a QRAM architecture, the QRAM architecture being configured for accessing data and being a binary tree structure, the method including: partitioning the binary tree structure into basic circuit structures, wherein a basic circuit structure comprises address bits and data bits of one subtree node and data bits of two child nodes in the lower layer of the one subtree node; determining qubits required for a basic quantum circuit to be constructed, according to qubits included in the basic circuit structure; determining an input and an output of the basic quantum circuit to be constructed, according to action relationships between the qubits required for the basic quantum circuit to be constructed; and constructing a basic quantum circuit corresponding to the basic circuit structure, according to the input and the output using the required qubits and quantum logic gates.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: May 14, 2024
    Assignee: Origin Quantum Computing Technology (Hefei) Co., Ltd.
    Inventors: Ye Li, Ningbo An, Menghan Dou
  • Patent number: 11983204
    Abstract: The mobile terminal-oriented complex condition geographic information query method, device and medium are disclosed, and the method includes: determining geographic information query condition semantics, and setting complex condition query contents according to condition semantic regulations; based on a preset query rule, analyzing conditions meeting the rule, and obtaining attribute information of target objects and attribute information of condition objects forming complex conditions; and according to the attribute information of the target objects and the attribute information of the condition objects, performing server calculation query and returning a geographic information query result. Based on collection, storage and classification of the geographic entity position information, the geographic entity position information of a specific type and space limitation is inquired, so that the function of simultaneously limiting the conditions of target objects by the mobile terminal is enriched.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: May 14, 2024
    Assignee: BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Shuai Zhao, Bo Cheng, Shengjie Li, Junliang Chen
  • Patent number: 11977489
    Abstract: Apparatuses, systems, and techniques for memory management are disclosed. In at least one embodiment, memory management is provided for a heterogenous system, for example, a system including a CPU and a GPU, in which redundant or unnecessary memory transfers are reduced.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA Corporation
    Inventors: Weixi Zhu, Guilherme Cox
  • Patent number: 11940919
    Abstract: System and techniques for recall pending cache line eviction are described herein. A queue that includes a deferred memory request is kept for a cache line. Metadata for the queue is stored in a cache line tag. When a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request ID. After the recall request is transmitted, the memory request ID is written to a second recall storage referenced by the message ID of the recall request. Upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message ID in the response to lookup the memory request ID from the second recall storage, then using the memory request ID to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony M. Brewer
  • Patent number: 11934695
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chandramani, Dinesh Agarwal, Sharath Shivakumar, Ruchir Sinha
  • Patent number: 11907725
    Abstract: A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: February 20, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Richard Osborne, Matthew Fyles
  • Patent number: 11907556
    Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
  • Patent number: 11893243
    Abstract: A storage system has a memory that is organized in wordlines. Each wordline has a number of strings. A controller in the storage system changes, in each of the wordlines, which of the strings is a last string programmed. Doing so can unmask a program disturb error when triple-level cells in the memory are used as pseudo-multi-level cells. By unmasking the program disturb error, the controller can detect and correct the error.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel J. Linnen, Prakash Subedi, Khanfer A. Kukkady, Mark Murin
  • Patent number: 11875045
    Abstract: A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jixing Chen, Weibing Shang
  • Patent number: 11868271
    Abstract: A method for accessing compressed computer memory residing in physical computer memory is disclosed. In the method, compressed memory blocks are represented as sectors, wherein all sectors contain a fixed number of compressed memory blocks, have a fixed logical size in the form of the fixed number of compressed memory blocks, and have varying physical sizes in the form of the total size of data stored in the respective compressed memory blocks.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 9, 2024
    Assignee: Zeropoint Technologies AB
    Inventors: Angelos Arelakis, Vasileios Spiliopoulos, Per Stenström
  • Patent number: 11853202
    Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventor: Hye Mi Kang
  • Patent number: 11841873
    Abstract: Data sources provide access to data. The data stored by the data source may be transformed before use by an application. Different data sources support different transformations. A data agent sidecar for the application accepts work orders from the application and submits work orders to data sources. A work order identifies a data source from which data is requested. The work order optionally includes one or more transformations to be applied to the data from the data source. The data agent sidecar determines, for the data source from which data is requested, which transformations can be performed by the data source and which transformations are not supported by the data source. The data transformations that can be performed by the data source are included in the work order to the data source. The remaining data transformations are performed by the data agent sidecar.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 12, 2023
    Assignee: SAP SE
    Inventors: Daniel Bos, Qing Liu, Tobias Maximilian Karpstein
  • Patent number: 11824932
    Abstract: An information management system according to certain aspects can implement application archiving. The system may archive one or more applications on computing devices to make more storage space available on these devices. The system can determine which applications on client computing device to archive based on various factors. Some examples of factors can include frequency of use, application type, amount of application data and/or storage, user and/or device location, etc. The data to be archived can include one or more executable file(s), metadata, actual data, etc. After an application is archived, the system can generate a placeholder for the application; a placeholder can include information for restoring the archived application.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: November 21, 2023
    Assignee: Commvault Systems, Inc.
    Inventors: Bhavyan Bharatkumar Mehta, Rajiv Kottomtharayil, Tirthankar Chatterjee, Jun H. Ahn
  • Patent number: 11809283
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for deleting backup data. The method includes determining a set of non-backup time periods for an object based on a set of backup time periods for the object. The method further includes selecting a subset of non-backup time periods from the set of non-backup time periods on the basis of a time length. The method further includes deleting backup data of the object in the subset of non-backup time periods. By the embodiments of the present disclosure, a suitable time period can be selected, and unnecessary backup data is effectively deleted from the selected time period, thus improving the success rate of deletion of backup data.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: November 7, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Zengjie Zhang, Jinru Yan, Yudai Wang, Kai Ji, Zheyi Zhu
  • Patent number: 11797525
    Abstract: Techniques for reconstructing or building metadata pages in storage nodes that have a delta-log based architecture. The techniques include walking “up” an ancestor chain of a metadata page, detecting the most recent delta update for a metadata entry of the metadata page, writing the most recent delta update to a location of the metadata entry in the metadata page, setting a bitmap entry corresponding to the location of the metadata entry in the metadata page, detecting a less recent delta update for the metadata entry of the metadata page, and, having previously set the bitmap entry corresponding to the location of the metadata entry in the metadata page, avoiding writing the less recent delta update to the location of the metadata entry in the metadata page. In this way, the need to save in memory the entire ancestor chain of the metadata page can be eliminated.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 24, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Ami Sabo
  • Patent number: 11797575
    Abstract: A request may be received to transform records in a data lake that match one or more query criteria. Data lake records that match the criteria may be retrieved. The retrieved records may include two data lake records associated with the same data lake record identifier. A transformed record may be generated based on time stamps associated with the retrieved records.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: October 24, 2023
    Assignee: Salesforce, Inc.
    Inventors: Shreedhar Sundaram, Mahalaxmi Sanathkumar, Aaron Zhang, Parin Kenia, Violet Gong, Priya Sethuraman, Zhidong Ke, Kevin Terusak
  • Patent number: 11790993
    Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: October 17, 2023
    Assignee: Kioxia Corporation
    Inventors: Riki Suzuki, Yoshihisa Kojima
  • Patent number: 11777790
    Abstract: The present invention relates to methods and apparatus for migrating and/or changing the allocation of network interface(s) or Internet Protocol address(es) of network interface(s) from one Pod, e.g., a failed Pod, to another Pod, e.g., a live Pod, in a Kubernetes system. An exemplary method of operating a Kubernetes system in accordance with an embodiment of the invention includes: establishing, by the Kubernetes system, a first service including a first Pod located on a first node and a second Pod located on a second node, allocating by the Kubernetes system an external network interface including an Internet Protocol address for use by the first Pod, the allocation of said external network interface for use by the first Pod being unknown to a first Kubelet managing the first node; and upon failure of the first Pod, changing allocation of the external network interface from the first Pod to the second Pod.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 3, 2023
    Assignee: Ribbon Communications Operating Company, Inc.
    Inventors: Tolga Asveren, Souvik Dey, Mark St. Pierre, Suyash Suhas Karmarkar
  • Patent number: 11768763
    Abstract: A system with storage memory and a processing device has a logical deletion to physical erasure time bound. The system dereferences data, responsive to a direction to delete the data. The system monitors physical blocks in storage memory for live data and the dereferenced data. The system cooperates garbage collection with monitoring the physical blocks, so that at least a physical block having the dereferenced data is garbage collected and erased within a logical deletion to physical erasure time bound.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 26, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Igor Ostrovsky, Constantine P. Sapuntzakis, Peter E. Kirkpatrick, John Colgrove
  • Patent number: 11763896
    Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seungjune Jeon, Zhenming Zhou, Zhenlei Shen
  • Patent number: 11762573
    Abstract: A method of preserving the contiguity of large pages of a workload during migration of the workload from a source host to a destination host includes the steps of: detecting at the destination host, receipt of a small page of zeros from the source host, wherein, at the source host, the small page is part of one of the large pages of the workload; and upon detecting the receipt of the small page of zeros, storing, at the destination host, all zeros in a small page that is part of one of the large pages of the workload.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: September 19, 2023
    Assignee: VMware, Inc.
    Inventors: Arunachalam Ramanathan, Yury Baskakov, Anurekh Saxena, Ying Yu, Rajesh Venkatasubramanian, Michael Robert Stunes
  • Patent number: 11740801
    Abstract: This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: August 29, 2023
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, Alan Chen, Robert Lercari
  • Patent number: 11734277
    Abstract: An approach is provided for optimizing a database buffer pool. Based on statistics about read and write operations in a range of pages, the range of pages is determined to be a candidate for a hot read range for which locks and latches are avoided in processing operations in the hot read range. Using an on-time trigger or pre-trigger process, the hot read range is created from the range of pages by marking start and end points in the range of pages. Write operation(s) are determined to be included in the hot read range by marking an object control block. The write operation(s) are added to a write pending list. The read operations in the hot read range are performed without a latch or lock. The write operation(s) are merged from the write pending list to the range of pages and the write operation(s) are performed.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Xiaobo Wang, Hong Mei Zhang, Sheng Yan Sun
  • Patent number: 11734113
    Abstract: A solid state disk access method includes: determining, in response to a read error, a first read voltage of the current data block according to a current data storage time interval to which a data storage time of the current data block belongs; performing reread error correction on the data in the current data block based on the first read voltage; determining, if reread error correction of the current data block fails, a second read voltage corresponding to the current data block according to the current data storage time interval and a preset data read rule that is determined based on the data storage time interval and the number of data reads; and performing reread error correction on the data in the current data block based on the second read voltage until the reread error correction of the current data block meets a preset reread error correction condition.
    Type: Grant
    Filed: February 20, 2021
    Date of Patent: August 22, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Wenhao Shao
  • Patent number: 11726963
    Abstract: A data storage system for use with a multi-threaded processing system receives concurrent requests to store data to a common data store, and efficiently and securely swaps an active data store for a new data store while avoiding conflicts arising from multiple threads attempting to swap a same data store and minimizing reliance on operations that re-attempt actions upon failure of an attempted action, thereby improving performance of the data storage system and also the multi-threaded processing system.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: August 15, 2023
    Assignee: Chicago Mercantile Exchange Inc.
    Inventor: Kyle D. Kavanagh
  • Patent number: 11714573
    Abstract: Techniques for storage optimization in a distributed object store are described. A storage optimization service of a provider network monitors changes to data objects in a distributed object store that are part of a data lake and are referenced by a table index. The storage optimization service determines whether particular storage optimizations involving the data objects would be beneficial, prioritizes the ordering of these optimizations with a focus on performing impactful optimizations first, while intelligently scheduling the optimizations to avoid overutilization of available resources.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: August 1, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Shashank Bhardwaj, Roman Gavrilov, Brian Scott Ross, Mehul A. Shah, Benjamin Sowell, Anthony A. Virtuoso, Linan Zheng
  • Patent number: 11693663
    Abstract: Methods and apparatus for managing circular queues are disclosed. A pointer designates an index position of a particular queue element and contains an additional pointer state, whereby two pointer values (split indexes) can designate the same index position. Front and rear pointers are respectively managed by dequeue and enqueue logic. The front pointer state and rear pointer state distinguish full and empty queue states when both pointers designate the same index position. Asynchronous dequeue and enqueue operations are supported, no lock is required, and no queue entry is wasted. Hardware and software embodiments for numerous applications are disclosed.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: July 4, 2023
    Assignee: UT-Battelle, LLC
    Inventors: Narasinga Rao Miniskar, Frank Y. Liu, Jeffrey S. Vetter
  • Patent number: 11687489
    Abstract: A method and system for identifying garbage data, an electronic device, and a storage medium. The method includes: uploading an object to a distributed object storage system; acquiring a head object identifier in an index storage pool of the distributed object storage system; querying a data storage pool for a target data group corresponding to the head object identifier; marking a tail object corresponding to a tail object identifier in the target data group as a target tail object; and marking tail objects in the data storage pool other than the target tail object as garbage data.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 27, 2023
    Assignee: INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.
    Inventors: Yu Zhao, Yonggang Hu
  • Patent number: 11675411
    Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe D'Eliseo, Xiangang Luo, Ting Luo, Jianmin Huang
  • Patent number: 11663136
    Abstract: A non-volatile memory device includes a volatile memory, a non-volatile memory, and a controller. The controller is configured to map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory. The controller is configured to perform a storage capacity recovery operation for a region of the non-volatile memory that is selected based at least partially on a number of mappings for the region likely to be stored in the volatile memory for the storage capacity recovery operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 30, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Hongmei Xie, Dhanunjaya Rao Gorrle, Aajna Karki
  • Patent number: 11656979
    Abstract: A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventors: Miseon Han, Hyung Jin Lim, Jongryool Kim, Myeong Joon Kang
  • Patent number: 11630766
    Abstract: A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 18, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Duck-Ho Bae
  • Patent number: 11630764
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. Garbage collection is performed with regard to the memory device on the basis of a first amount of time and a second amount of time, the first amount of time being a period of time between triggering of first garbage collection and triggering of second garbage collection, and the second amount of time being an amount of time necessary to perform the second garbage collection. A ratio of the first amount of time to the second amount of time is determined as a target ratio value, and the second amount of time is determined to be equal to or longer than a minimum garbage collection operation time. Accordingly, efficient garbage collection can be performed, and the optimal time to perform garbage collection can be determined with regard to a configured performance drop value.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 18, 2023
    Assignee: SK hynix Inc.
    Inventors: Min Jun Jang, Hyoung Pil Choi
  • Patent number: 11620085
    Abstract: A processing device, operatively coupled with a memory device, performs operations including receiving a write request from a host system at a first time, the write request identifying first data to be stored in a segment of the memory device, determining whether a pre-read voltage level of the write request satisfies a pre-read voltage level criterion pertaining to a write-to-write time interval for the segment, wherein the write-to-write time interval is defined by the first time and a second time corresponding to a last time at which the segment was written, and responsive to determining that the pre-read voltage level satisfies the pre-read voltage level criterion pertaining to the write-to-write time interval, performing a pre-read operation on the segment using the pre-read voltage level to determine second data currently stored in the segment.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 11620215
    Abstract: A method and a system for garbage collection on a system. The method includes initiating a garbage collection process on a system by a garbage collector. The garbage collector includes one or more garbage collector threads. The method also includes marking a plurality of referenced objects using the garbage collector threads and one or more application threads during a preemption point. The method includes replicating the referenced objects using the garbage collector threads and marking for replication any newly discovered referenced objects found by scanning the application thread stack from a low-water mark. The method also includes replicating the newly discovered referenced objects and overwriting any reference to the old memory location.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventor: Kelvin Don Nilsen
  • Patent number: 11604760
    Abstract: Provided are a computer program product, system, and method for dynamic determination of retention periods for digital content. Metadata is generated for instances of digital content including an access pattern of the digital content by a user of the computing device, attributes of the digital content, and a retention period during which the digital content stored is retained in the storage. A machine learning module is trained with input comprising the metadata for instances of the digital content to produce the retention period of the digital content. Input, comprising metadata determined from digital content, received after training the machine learning module, is provided to the machine learning module to produce an output retention period for the digital content received after the training. The output retention period is used to determine when to delete the digital received after the training content from the storage.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: March 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Partho Ghosh, Saraswathi Sailaja Perumalla, Divya Mantha, Sunita Rani Nayak
  • Patent number: 11582168
    Abstract: Snapshots of storage volumes and containers of a bundled application may be created and used to rollback or clone the bundled application. Clone snapshots of storage volumes may be gradually populated with data from prior snapshots to reduce loading on a primary snapshot. Components of cloned applications may communicate with one another using addresses of these components in the parent application. Containers of the bundled application may communicate with an open virtual switch (OVS) that implements flows to implement translation between clone and parent addresses. Containers may be modified to execute operation-specific entrypoint functions prior to invoking an entrypoint of an application instance loaded in the containers.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 14, 2023
    Assignee: Robin Systems, Inc.
    Inventors: Shravan Kumar Vallala, Ravi Kumar Alluboyina
  • Patent number: 11561787
    Abstract: A computer-implemented method that includes determining that a first version of an operating system (OS) is updated to a second version of the OS. The method further includes determining that an application does not support the second version of the OS. The method further includes associating the first version of the OS with the application as a base OS. The method further includes invoking the application on the base OS by generating an isolated instance running the base OS on a user device, where the user device simultaneously runs the second version of the OS.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sho Ayuba, Mayumi Goto, Timothy Waileong Koh, Nobuyuki Yoshifuji
  • Patent number: 11556275
    Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Colella, Antonino Pollio, Gianfranco Ferrante
  • Patent number: 11556262
    Abstract: Successful storing of extent operations into corresponding records of a transaction log results in acknowledgement of completion of the extent operations being indicated to one or more hosts. In response to determining that the extent operations are unrelated to each other, the extent operations are flushed in parallel from the transaction log to back-end non-volatile data storage. During the flushing, dependencies between the extent operations and other operations stored in the transaction log are maintained. Dependency chains are identified within the transaction log, and at least one tree data structure representing the dependencies between each of the extent operations and the other operations stored in the transaction log may be generated and traversed in order to select the correct operations stored in the transaction log to flush.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 17, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Socheavy Heng, William C. Davenport
  • Patent number: 11550711
    Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, Nadav Grosz, Qing Liang, David Aaron Palmer
  • Patent number: 11543984
    Abstract: A storage device includes a memory device and a memory controller. The memory device includes a first plane and a second plane, each including data blocks configured to store user data, one or more replacement blocks configured to replace one or more bad blocks, and system blocks configured to store system information. The memory controller is configured to replace, when a bad block is detected in the first plane after all the one or more replacement blocks in the first plane are used to replace previously detected bad blocks, the detected bad block with a target system block selected among the system blocks in the first plane.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Hoon Choi, Beom Ju Shin
  • Patent number: 11543988
    Abstract: A method of preserving the contiguity of large pages of a workload during migration of the workload from a source host to a destination host includes the steps of: detecting at the destination host, receipt of a small page of zeros from the source host, wherein, at the source host, the small page is part of one of the large pages of the workload; and upon detecting the receipt of the small page of zeros, storing, at the destination host, all zeros in a small page that is part of one of the large pages of the workload.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: January 3, 2023
    Assignee: VMware, Inc.
    Inventors: Arunachalam Ramanathan, Yury Baskakov, Anurekh Saxena, Ying Yu, Rajesh Venkatasubramanian, Michael Robert Stunes
  • Patent number: 11537560
    Abstract: A method for performing hash code calculations may include calculating, during a write operation for a data block, a hash code for an occupied portion of the data block, inserting, during the write operation, a marker into the data block, calculating, during a read operation for the data block, a hash code for the occupied portion of the data block, searching, during the read operation, for the marker in the data block, and terminating the hash code calculation in response to finding the marker. A system may include a first interface configured to receive data blocks, a second interface configured to transmit data blocks, and hash logic coupled between the first and second interfaces, wherein the hash logic is configured to calculate a hash code for the occupied portion of a data block received through the first interface, and insert a marker in an unoccupied portion of the data block.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 27, 2022
    Inventors: Jian Zhao, Hui-Juan Li, Rong Zheng
  • Patent number: 11526439
    Abstract: A storage device includes a nonvolatile memory including a plurality of first blocks having memory cells each configured to store one bit of data and a plurality of second blocks having memory cells each configured to multiple bits of data; and a controller configured to determine whether or not a number of use-completed second blocks, each of which has a first threshold number or less of valid pages, among use-completed second blocks of the plurality of second blocks, is equal to or larger than a second threshold number and to select, according to a determination result, a victim block on which garbage collection is to be performed among used-completed first blocks of the plurality of first blocks or the use-completed second blocks each having the first threshold number or less of valid pages.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Woo Kim, Jin Woong Kim, Hui Jae Yu
  • Patent number: 11507702
    Abstract: Embodiments relate to switching a neural processor circuit between non-secure and secure modes. A security controller of the neural processor circuit indicates that a transition from the non-secure mode to the secure mode is to occur. The security controller waits for a neural task manager of the neural processor circuit to clear out any existing non-secure tasks in queues. After the existing non-secure mode tasks are cleared, the security controller switches the neural processor circuit to the secure mode. While in the secure mode, secure tasks are added to one or more queues and executed, and data for processing in the neural processor circuit is received from a secure source. The neural processor circuit may to transition back to the non-secure mode when all secure mode tasks are completed.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 22, 2022
    Assignee: Apple Inc.
    Inventors: Liran Fishel, Zhimin Chen
  • Patent number: 11501838
    Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: November 15, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Seungjune Jeon, Zhenming Zhou, Zhenlei Shen
  • Patent number: 11500590
    Abstract: Techniques for data writing involve: determining an unavailable storage zone in multiple storage zones of a storage area, wherein each storage zone is used to store a zip header and compressed data corresponding to the zip header; acquiring a reference zip header for the unavailable storage zone, wherein the reference zip header includes metadata indicating a zone length of the unavailable storage zone; and generating consecutive write requests for the storage area based at least on target data to be written to the storage area and the reference zip header, so as to write the target data to available storage zones in the multiple storage zones. Accordingly, rewriting of data can be implemented by constructing large consecutive write requests, thus improving the write performance of the storage device.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Leihu Zhang, Chen Gong, Shuo Lv
  • Patent number: 11494276
    Abstract: Processing write requests from clients includes logging the associated data into logs corresponding to the data objects targeted by the write requests. The logs are persisted by combining log entries from each of the logs into one ore more fixed-size data blocks. The fixed-size data blocks are inserted into a data tree stored on a block-based storage device.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 8, 2022
    Assignee: VMWARE INC.
    Inventors: Wenguang Wang, Vamsi Gunturu, Eric Knauft
  • Patent number: 11487658
    Abstract: A memory system may include a plurality of dies; and a controller coupled to the plurality of dies through a plurality of data paths, the controller being suitable for transmitting first data received from a host and second data obtained through an internal operation in parallel through the plurality of data paths.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun