Entry Replacement Strategy Patents (Class 711/159)
  • Patent number: 11188229
    Abstract: In some examples, a system may include at least one class of storage that is configured for having freed storage space reclaimed to enable reuse of the freed storage space. For instance, the system may determine whether a volume corresponding to the at least one class of storage is used to store system data or user data. If the volume is used to store user data, then the system may determine whether any of the user data has been deleted from the volume. If data has been deleted from the volume, the system may determine whether an available capacity of the volume is less than a remaining capacity threshold before performing reclamation on the at least one storage device corresponding to the volume. Alternatively, if the volume is used to store system data, the system may perform reclamation based on an elapsed period of time since the last reclamation.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 30, 2021
    Assignee: HITACHI VANTARA LLC
    Inventors: Yury Kats, Sowmya Manjanatha
  • Patent number: 11182097
    Abstract: A computer-implemented method includes receiving a plurality of storage requests to store a plurality of objects in a dispersed storage network. The computer-implemented method further includes transforming each object in the plurality of objects into a set of error encoded slices. The computer-implemented method further includes dispersing each error encoded slice in each set of error encoded slices to a memory zone of a distinct storage unit. The computer-implemented method further includes co-locating two or more error encoded slices in a common memory zone of a storage unit based, at least in part, on an expiry time associated with the two or more encoded slices. The computer-implemented method further includes logically deleting the common memory zone of the storage unit after all error encoded slices stored in the common memory zone have expired.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Praveen Viraraghavan, Ethan Wozniak, Amit Lamba
  • Patent number: 11163679
    Abstract: Memory systems and components thereof execute an improved garbage collection (GC) strategy in the case of multiple sudden power offs (SPOs). Such a memory system comprises a memory device including single-level cell (SLC) memory blocks grouped into super blocks (SLC SBs) and multi-level cell (MLC) memory blocks grouped into SBs (MLC SBs); and a memory controller to execute a flash translation layer (FTL) to perform a garbage collection (GC) operation. The memory controller executes the GC operation after a sudden power off (SPO) by determining each MLC SB with user data opened before the SPO to be an unsafe super block (UB), copying data from pages in a select one of the UBs to pages in the SLC SBs, and copying data from the pages in the SLC SBs to pages in a select MLC SB not determined to be a UB.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Igor Novogran, Andrei Konan
  • Patent number: 11157483
    Abstract: Embodiments of the present disclosure provide methods, systems, apparatuses, and computer program products for digital content auditing in a group based communication repository, where the group based communication repository comprises a plurality of enterprise-based digital content objects organized among a plurality of group-based communication channels. In one embodiment, a computing entity or apparatus is configured to receive an enterprise audit request, where the enterprise audit request comprises an audit credential and digital content object retrieval parameters. The apparatus is further configured to determine if the audit credential satisfies an enterprise authentication protocol.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: October 26, 2021
    Assignee: Slack Technologies, LLC
    Inventors: Brenda Jin, Britton Jamison
  • Patent number: 11157365
    Abstract: A solution for processing a stripe in a storage device is provided. Where at least one stripe unit not requiring garbage collection from each stripe of at least two stripes in the storage device is determined, each of the at least two stripes comprises a stripe unit requiring garbage collection and a stripe unit not requiring garbage collection; parity data of data in the determined stripe units not requiring garbage collection is computed and stored into a first idle stripe unit, where the first idle stripe unit and the determined stripe units not requiring garbage collection are in a new stripe in the storage device.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 26, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Mingchang Wei, Suhong Wu, Guoyan Huang
  • Patent number: 11144451
    Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11106372
    Abstract: An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael G. Miller
  • Patent number: 11099982
    Abstract: Methods and systems for garbage collection are described. In some embodiments, Garbage collector threads may maximize local accesses and minimize remote access by copying Young objects and Old objects differently. When copying a Young object, a garbage collector thread may determine the lgroup of the pool that contains the object and copy the object to a pool of the same lgroup. The garbage collector thread may spread Old objects among lgroups by copying Old objects to pools of the same lgroup as the respective garbage collector thread. Additional methods and systems are disclosed.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 24, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Antonios Printezis, Igor Veresov, Paul Henry Hohensee, John Coomes
  • Patent number: 11086660
    Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 10, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Izzat El Hajj, Alexander Merritt, Gerd Zellweger, Dejan S Milojicic
  • Patent number: 11080097
    Abstract: Customers of a computing resource service provider may transmit requests to instantiate compute instances associated with a plurality of logical partitions. The compute instances may be executed by a server computer system associated with a particular logical partition of the plurality of logical partitions. For example, a compute service may determine a set of server computer systems that are capable of executing the compute instance based at least in part on placement information and/or a diversity constraint of the plurality of logical partitions.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: August 3, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Vikas Panghal, Alan Hadley Goodman, André Mostert, Stig Manning, Joshua Dawie Mentz, Gustav Karl Mauer, Marnus Freeman
  • Patent number: 11061815
    Abstract: A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Patent number: 11049585
    Abstract: Field configurable bad block repair for a memory array comprising a plurality of blocks utilizes a block repair information store for data identifying one or more bad blocks in the array. The block repair information store includes nonvolatile memory writable at least once. Block repair circuitry on the device is configurable to redirect commands to access bad blocks identified in the bad block repair information store to reserved blocks in the memory array. A controller is responsive to a command to write bad block repair information, such as an identifier of a bad block in the plurality of blocks to the block repair information store in the field, and to reconfigure the block repair circuitry in the field using the updated information.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chun-Hsiung Hung
  • Patent number: 11036629
    Abstract: In accordance with an embodiment of the present disclosure, a method of a controller for controlling a nonvolatile memory device including a plurality of data storage regions may include: determining, in response to a first copy event of receiving from a host a command instructing copy of data from a first logical address into a second logical address, whether a second copy event of copying the data from a first data storage region having a first physical address mapped to the first logical address into a data storage region having another physical address will occur; and in response to determining that the second copy event will not occur, changing a logical address mapped to the first physical address from the first logical address to the second logical address and invalidating the first logical address.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Patent number: 11030094
    Abstract: A memory system includes a nonvolatile memory device including a plurality of dies, each die including a plurality of planes, each plane including a plurality of blocks, each block including a plurality of pages, and further includes a plurality of page buffers, each page buffer for caching data in a unit of a page to be inputted to, and outputted from, each of the blocks; and a controller suitable for managing a plurality of super blocks according to a condition, each super block including N blocks capable of being read in parallel among the blocks, generating predicted required times for the super blocks, respectively, each of the predicted required times representing a time needed to extract valid data from the corresponding super block, and selecting a victim block for garbage collection from among the blocks based on the predicted required times.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Yeong-Sik Yi, Jin-Woong Kim
  • Patent number: 11016883
    Abstract: A method of manual memory management is described which comprises enabling one or more threads to access an object created in a manual heap by storing a reference to the object in thread-local state and subsequently deleting the stored reference after accessing the object. In response to abandonment of the object, an identifier for the object and a current value of either a local counter of a thread or a global counter are stored in a delete queue and all threads are prevented from storing any further references to the object in thread-local state. Deallocation of the object only occurs when all references to the object stored in thread-local state for any threads have been deleted and a current value of the local counter for the thread or the global counter has incremented to a value that is at least a pre-defined amount more than the stored value, wherein the global counter is updated using one or more local counters.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: May 25, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Matthew John Parkinson, Manuel Silverio da Silva Costa, Dimitrios Vytiniotis, Kapil Vaswani
  • Patent number: 10977172
    Abstract: Techniques are disclosed relating to virtual memory page reclamation policies. In some embodiments, an operating system of a computing device implements, during a first operating mode, a first page reclamation policy for pages corresponding to user processes and non-user processes. The computing device may then enter a second operating mode upon detecting some indication of user inactivity. The operating system may then implement, during the second operating mode, a second page reclamation policy for pages corresponding to user processes and non-user processes, where the second page reclamation policy prioritizes, relative to the first page reclamation policy, eviction of pages corresponding to non-user processes.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: April 13, 2021
    Assignee: Apple Inc.
    Inventors: Lionel D. Desai, Benjamin C. Trumbull
  • Patent number: 10970415
    Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Purvi Sharadchandra Patel, Elpida Tzortzatos, Scott B. Compton, Hong Min
  • Patent number: 10956577
    Abstract: An apparatus and methods are provided to defending device against attacks. When it is determined that a device is under attack, a determination is made as to whether a layout of objects within said at least one resource at said device is protecting said device against said attack. The determination is then transferred to a remote server together with a layout of the resource at the device. When it is determined that the layout of objects within the at least one resource at the device is not protecting the device against the attack, then the layout of the at least one resource is changed. Either the remote server or the device may determine whether to change the layout in response to the attack.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 23, 2021
    Assignee: ARM IP Limited
    Inventors: Alessandro Angelino, Milosch Meriac, Brendan James Moran
  • Patent number: 10949198
    Abstract: Disclosed herein is an online platform for facilitating the development of software applications based on an executable statechart using a microservices architecture, in accordance with some embodiments. Accordingly, the online platform may include a communication device, a processing device, and a storage device. Further, the communication device may be configured for transmitting a software application design interface to a user device. Further, the communication device may be configured for receiving a plurality of design commands, through the software application design interface, from the user device. Further, the processing device may be configured for generating an executable statechart design based on the plurality of design commands. Further, the storage device may be configured for storing the at least one executable statechart design.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 16, 2021
    Inventor: Clarence Yandell Weston
  • Patent number: 10924502
    Abstract: Techniques for providing network security and anomaly detection are disclosed. In some embodiments, network traffic may be monitored in order to create a model of network traffic over a first period of time. Based on the model of network traffic, one or more inflated files may be created and stored on a system, wherein the inflated files are of a sufficient file size such that attempts to exfiltrate one or more of the files may be detected based by network monitoring tools. The inflated files may further include one or more indicators of sensitivity, including indicators of the presence of sensitive information that is not actually included in the inflated files. Network traffic characteristics may then be repeatedly or continuously monitored in order to update the size of the one or more inflated files based on changes in network traffic characteristics.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 16, 2021
    Assignee: NOBLIS, INC.
    Inventors: Matthew K. Monaco, Daniel Negron, Brian Satira, Michael Collins
  • Patent number: 10909621
    Abstract: A system and method is disclosed for quantifying temporal fairness on an electronic trading venue as a scalar value with unit time. The system may, for an instrument traded on the venue, construct some pluralities of time deltas associated with each pair of market participants in a plurality of such that are active on the instrument. The system may populate these pluralities of time deltas by determining the amount of time that elapses between when the first and second participant in a pair each send (or are sent) a similar message to (or from) the venue. Through analysis of these pluralities of time deltas the system may find two minimum values, fords and fmktdata, the sum of which may quantify temporal fairness for the instrument on the venue. The resultant sum may inform the value of a latency floor deployed for the instrument on the venue.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 2, 2021
    Assignee: Refinitiv US Organization LLC
    Inventor: Hayden Paul Melton
  • Patent number: 10901620
    Abstract: A storage system and method for thin provisioning are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to provide a logical exported capacity of the memory to a host, wherein the logical exported capacity is greater than an actual storage capacity of the memory; receive a command from the host to write data to a logical address; determine whether there is available actual storage capacity in the memory to write the data; and write the data to a physical address in memory that corresponds to the logical address only if it is determined that there is available actual storage capacity in the memory to write the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Michael Zaidman, Rotem Sela, Hadas Oshinsky
  • Patent number: 10901891
    Abstract: A controller for controlling a memory device including memory dies includes: a processor suitable for checking whether or not any of the memory dies in the memory device is idle after transferring a write command to the memory device, and when there is an idle memory die, performing a garbage collection read operation of the idle memory die; and a garbage collection (GC) data region suitable for storing a valid data of a victim block, which is read through the garbage collection read operation; and wherein the processor transfers the valid data to the memory device based on an amount of valid data stored in the GC data region and controlling the memory device to perform a garbage collection write operation of programming the valid data in a target block.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10896055
    Abstract: An access data collector collects access assignment data characterizing active access assignment operations of a hypervisor in assigning host computing resources among virtual machines for use in execution of the virtual machines. Then, a capacity risk indicator calculator calculates a capacity risk indicator characterizing a capacity risk of the host computing resources with respect to meeting a prospective capacity demand of the virtual machines, based on the access assignment data.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 19, 2021
    Assignee: BMC Software, Inc.
    Inventors: Jeyashree Sivasubramanian, Sudheer Apte
  • Patent number: 10831607
    Abstract: In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen, Sanjeev Ghai, Hung Doan
  • Patent number: 10831663
    Abstract: An approach is disclosed that tracks memory transactions by a node. The approach establishes a transaction processing state corresponding to common virtual addresses accessed by a processing threads. Transactions are executed by the threads. A selected transaction is allowed to complete. In response to detecting a conflict in the transaction processing state, completion of a non-selected transaction is inhibited.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: James A. Kahle, Charles R. Johns
  • Patent number: 10809942
    Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
  • Patent number: 10802984
    Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Vivekananthan Sanjeepan, Leena K. Puthiyedath, Chandan Apsangi, Nikhil Talpallikar, Abinash K. Barik
  • Patent number: 10795604
    Abstract: The disclosure relates in some aspects to reporting the amount of available physical storage space of a non-volatile memory (NVM) array. A device including an NVM array may send reports regarding the amount of available physical storage space in the non-volatile memory device to a host device or some other suitable apparatus. The amount of available physical storage space takes into account whether any of the physical address blocks of the NVM array have been designated as worn-out. The host device (or other suitable apparatus) may send a report to a user when the amount of available physical storage space is relatively low.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 6, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michal Silbermintz, David Haliva, Gadi Vishne
  • Patent number: 10795768
    Abstract: Apparatus and method for managing data in a multi-device storage system, such as a RAID (redundant array of independent discs) system. Distributed data sets are stored across a plurality of storage devices. A selected storage device is replaced with a new storage device responsive to an anomalous event. A rebuild operation is performed to reconstruct data from the selected storage device to the new storage device. The rebuild process includes accessing a list of distributed data sets in a local memory. For each distributed data set in the list identified as constituting valid data, read commands are issued to the remaining storage devices and a write command is issued to the new storage device. For each distributed data set in the list identified as constituting unused data, a data clear command is issued to each of the remaining storage devices and to the new storage device.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Seagate Technology LLC
    Inventors: Kushal R. Hosmani, Thomas George Wicklund, Ian Davies, Ryan Patrick McCallister
  • Patent number: 10783113
    Abstract: Systems, methods, and other embodiments associated with a data retention framework that enforces archive eligibility criteria beyond a simple retention period are described. In one embodiment, a method includes identifying a record that has been stored in a primary data store for at least a retention period prescribed for the record and evaluating the record to determine if archive eligibility criteria for the record are met. When the archive eligibility criteria is met, the record is marked as eligible for archiving. When the archive eligibility criteria is not met, the record is marked as not eligible for archiving.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 22, 2020
    Assignee: Oracle International Corporation
    Inventors: Anthony Shorten, Shrenik Jain
  • Patent number: 10761933
    Abstract: A storage system comprises a plurality of storage nodes each comprising one or more storage devices. At least a given one of the storage nodes is configured to read data blocks from its one or more storage devices, and for a given one of the data blocks, to determine based at least in part on a content-based signature of that data block whether or not the given data block is appropriate for use in a prefilling operation of the given storage node. Responsive to the given data block being appropriate for use in the prefilling operation of the given storage node, the given storage node uses the data block in the prefilling operation of the given storage node. Responsive to the given data block not being appropriate for use in the prefilling operation of the given storage node, the given storage node sends the data block to another one of the storage nodes for use in a prefilling operation of that other storage node.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: William F. Moore, Anton Kucherov, Boaz Binia, Zvi Schneider
  • Patent number: 10754547
    Abstract: Disclosed is a method of managing a disaggregated memory. According to the present disclosure, the method includes: assigning at least one memory page to a local memory and a remote memory; checking a request for access to the memory page; checking whether a target performance ratio required in service is satisfied or not when the memory page requested to be accessed is assigned to the remote memory; predicting a size of the local memory on the basis of an LRU distance-based histogram when the target performance ratio is not satisfied; and reassigning the memory page requested to be accessed in consideration of the predicted size of the local memory.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 25, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kang Ho Kim, Kwang Won Koh
  • Patent number: 10725763
    Abstract: An updated version of a configuration of a computing resource may be rolled back to a previous version. The computing resource can include code for a function or the computing resource can be used to implement calls of an API. In some cases, the computing resource can be tagged to indicate that rollback functionality is applicable to the computing resource. The rollback to a previous version of code for a function or a previous version of an API may take place based on a rollback condition being satisfied that is related to error rates that take place when updated versions of a function or an API are utilized. The computing resource may be implemented in conjunction with a cloud-based storage system.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Andrew Christopher Chud
  • Patent number: 10719439
    Abstract: A method operable with the storage device includes determining a workload to the storage device based on host Input/Output (I/O) requests to the storage device. When the workload is above a threshold, a first portion of the storage device is selected for garbage collection based on the I/O requests. Otherwise, when the workload is below the threshold, a second different portion of the storage device is selected for garbage collection based on a storage ability of the second portion of the storage device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: July 21, 2020
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Siddhartha K. Panda, Daniel J. Benjamin, Ryan C. Weidemann
  • Patent number: 10681146
    Abstract: The present invention discloses a method and an apparatus for isolating a page cookie. The method includes: when a predetermined login account logs in, assigning an independent cookie storage for the predetermined login account; after a request of creating a page associated with the predetermined login account is acquired, establishing a mapping relation table for storing a mapping relation between a page view identification of the page associated with the predetermined login account and the independent cookie storage; when the page associated with the predetermined login account is loaded, looking up the mapping relation table; and initiating, according to the independent cookie storage corresponding to the page view identification of the page associated with the predetermined login account found in the mapping relation table, a request of loading the page associated with the predetermined login account.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 9, 2020
    Assignee: Guangzhou UCWEB Computer Technology Co., Ltd.
    Inventor: Xiangyang Zhao
  • Patent number: 10678754
    Abstract: A storage controller coupled to a multi-tenant storage array receives a request from a client device to write a data block to a volume resident on the storage array, wherein the client device is associated with a tenant of the storage array. The storage controller determines a tenant identifier associated with the tenant, generates a hash value for the data block based at least in part on the data block and the tenant identifier, and performs at least one data deduplication operation on the data block using the hash value by determining whether the hash value matches with any of the plurality of previous hash values that are identified in a deduplication map. Responsive to determining that the hash value does not match with any of the plurality of previous hash values that are identified in the deduplication map, the hash value is stored in the deduplication map.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 9, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Rajesh Kanungo, Ronald Karr, Ethan L. Miller
  • Patent number: 10635358
    Abstract: A memory management method is provided. The method includes storing an acquired first command into a command queue, wherein in response to determining that the first command is a flush command, a flush phase value of the flush command and a corresponding second command is set according to a current flush phase, a command phase count value corresponding to the current flush phase is calculated, and the current flush phase is adjusted; selecting a new target command from the command queue, and executing the target command according to a target flush phase value of the target command and a corresponding target flush phase count value, wherein the target flush phase count value not being a preset value is adjusted; determining, according to the adjusted target flush phase count value, whether to respond to a host system that an execution of a target flush command corresponding to the target flush phase value is completed.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: April 28, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Hung-Chih Hsieh
  • Patent number: 10628304
    Abstract: Garbage collection in a first node server of an in-memory replication system includes: in response to a garbage collection trigger in the first node server, determining whether identification information for a data object eligible for garbage collection in the first node server has been received by the first node server from at least a second node server in the in-memory replication system; and if the identification information has been received from at least the second node server, performing garbage collection on the data object with the first node server.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li Li, Ju Wei Shi, Rui Xiong Tian, Yi Xin Zhao
  • Patent number: 10613767
    Abstract: A non-volatile memory system includes a NAND flash memory device including at least one NAND flash memory and a memory controller that controls the NAND flash memory, a host device including a file system and a host controller that receives a command from the file system to provide the command to the NAND flash memory device, and a save storage manager that monitors a number and location of run-time bad blocks in the NAND flash memory, monitors a logical address use-state of the file system, and reduces a logical address space which the file system is able to use as the number of the run-time bad blocks is increased.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 7, 2020
    Assignees: The-AiO Inc., Essencore Limited
    Inventors: Seok Cheon Kwon, Seung Hyun Han
  • Patent number: 10579276
    Abstract: A storage scheme allocates portions of a logical volume to storage nodes in excess of the capacity of the storage nodes. Slices of the storage nodes and segments of slices are allocated in response to write requests such that actual allocation on the storage nodes is only in response to usage. Segments are identified with virtual segment identifiers that are retained when segments are moved to a different storage node. Logical volumes may therefore be moved seamlessly to different storage nodes to ensure sufficient storage capacity. Data is written to new locations in segments having space and a block map tracks the last segment to which data for a given address is written. Garbage collection is performed to free segments that contain invalid data, i.e. data for addresses that have been subsequently written to.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 3, 2020
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Dhanashankar Venkatesan, Partha Sarathi Seetala
  • Patent number: 10572350
    Abstract: A production host for hosting virtual machines includes a persistent storage and a production agent. The persistent storage stores virtual machine data associated with a virtual machine of the virtual machines and a virtual machine shadow copy associated with the virtual machine data. The production agent obtains a backup generation request for the virtual machine; in response to the backup generation request, generates the virtual machine shadow copy; makes a determination that the virtual machine shadow copy comprises an auto-recovery disk that comprises some data; in response to the determination, merges the virtual machine shadow copy using a parent block set storage template to obtain a backup of the virtual machine; and store the backup in backup storage. The parent block set storage template is not associated with the virtual machine shadow copy.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Aaditya Rakesh Bansal, Sunil Yadav, Shelesh Chopra, Soumen Acharya, Manish Sharma, Sudha Vamanraj Hebsur, Hareej G. Hebbur
  • Patent number: 10572448
    Abstract: A system for managing data using purging includes an input interface and a processor. The input interface is to receive an indication of a data object to be purged. The processor is to prepare the data object to be purged, which includes severing weak relations of the data object as of a purge prepare time. Preparing the data object to be purged transitions the data object from an operational state to a purge prepared state. The weak relations of the data object are relations to non-purge data objects of an object tree. The data object in a purge prepared state is monitored for access. In response to a detection of an attempt to access the data object, reinstate the data object, which includes rebuilding the weak relations. Reinstating the data object transitions the data object from the purge prepared state to the operational state.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 25, 2020
    Assignee: Workday, Inc.
    Inventors: Seamus Donohue, Sergio Mendiola Cruz, Ken Pugsley, John Levey, Gerald Green, Iacopo Pace
  • Patent number: 10572351
    Abstract: A production host includes a persistent storage for storing backup policies and a production agent that obtains a backup generation request for a virtual machine of the virtual machines; in response to the backup generation request, performs a continuity chain verification of a continuity chain associated with the virtual machine to identify a continuity state of backups associated with the virtual machine; makes a first determination, based on the continuity state of the backups associated with the virtual machine, that the backups associated with the virtual machine are in a remediable state; and, in response to the first determination, performs a remediation of the continuity chain to change the backups associated with the virtual machine to be in a continuous state; and generates a backup of the virtual machine using the backup policies while the continuity state of the backups associated with the virtual machine are in the continuous state.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Aaditya Rakesh Bansal, Sunil Yadav
  • Patent number: 10558382
    Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for grouping the memory blocks based on type into a plurality of super blocks according to a preset condition and managing the memory blocks by managing the super blocks, the controller may manage one or more of the super blocks, in each of which at least one bad memory block and good memory blocks are grouped, by classifying the one or more superblocks as first super blocks, and the controller may differently manage uses of the respective first super blocks based on the numbers of bad memory blocks included in the respective first super blocks.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Ik-Sung Oh, Kyeong-Rho Kim, Sung-Kwan Hong, Jin-Woong Kim
  • Patent number: 10552387
    Abstract: A system for managing data using simulated purging includes an input interface and a processor. The input interface is to receive an indication of a data to simulate purging. The processor is to mark the data as purge simulated at a purge simulated time, to monitor the data for an attempt to access the data after the purge simulated time, to increase a count of a number of attempts to access the data after the purge simulated time by one in response to an attempt to access the data after the purge simulated time, and to unmark the data as purge simulated and cease monitoring the data for the attempt to access the data in response to the count of the number of attempts to access the data after the purge simulated time exceeding a threshold.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 4, 2020
    Assignee: Workday, Inc.
    Inventors: Seamus Donohue, Sergio Mendiola Cruz, Ken Pugsley, John Levey, Gerald Green, Iacopo Pace
  • Patent number: 10552254
    Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh
  • Patent number: 10529427
    Abstract: A semiconductor memory system includes a memory device including a plurality of memory blocks; a partial memory block detector suitable for detecting at least one partial memory block among the plurality of memory blocks; an open page detector suitable for detecting addresses and a number of a plurality of open pages among a plurality of pages included in the partial memory block; and a controller suitable for controlling the memory device to perform a one-shot program operation with dummy data according to the addresses and the number of the plurality of open pages.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10503658
    Abstract: The present disclosure is directed to techniques for migrating data between heterogeneous memories in a computing system. More specifically, the techniques involve migrating data between a memory having better access characteristics (e.g., lower latency but greater capacity) and a memory having worse access characteristics (e.g., higher latency but lower capacity). Migrations occur with a variable migration granularity. A migration granularity specifies a number of memory pages, having virtual addresses that are contiguous in virtual address space, that are migrated in a single migration operation. A history-based technique that adjusts migration granularity based on the history of memory utilization by an application is provided. A profiling-based technique that adjusts migration granularity based on a profiling operation is also provided.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 10, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arkaprava Basu, Jee Ho Ryoo
  • Patent number: 10496535
    Abstract: Embodiments of the invention include systems and methods for recovering the system status and maintaining drive coherency after an unexpected power loss. In particular, these systems and methods reduce overhead for maintaining drive coherency by providing for pre-allocation of groups of write addresses and recording the pre-allocated groups of addresses to the non-volatile memory. Write processes can write to the pre-allocated group of addresses while the next group of addresses are pre-allocated and recorded to non-volatile memory.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 3, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Lyndon S. Chiu, Frederick H. Adi