Entry Replacement Strategy Patents (Class 711/159)
  • Patent number: 12259747
    Abstract: Two pointers are initialized. The first pointer is incremented every M cycles of a monitored clock and the second pointer is incremented every N cycles of a reference clock, where M and N are determined from a frequency relationship between the clocks. If the positions of the pointers are determined to differ by more than a drift threshold, an error is detected and corrective action may be taken.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: March 25, 2025
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Madhusudhan Harigovindan Thekkeettil, Josef Mueller
  • Patent number: 12242339
    Abstract: In a memory error processing method, a processor of a computer apparatus obtains from a basic input/output system (BIOS) first error description information that describes a type of a first error that has occurred in a first memory page. Based on the first error description information, the processing device identifies the type of the first error to be a first type, wherein an error of the first type is a corrected error and is not a mirror scrub success error. The processor then determines that a number of errors of the first type that occurred in the first memory page has reached a threshold. In response to the determining, the processing device takes the first memory page offline.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 4, 2025
    Assignee: XFUSION DIGITAL TECHNOLOGIES CO., LTD
    Inventors: Zhong Li, Jia Lou, Dongshu Zhou
  • Patent number: 12210450
    Abstract: According to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. When an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. The controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: January 28, 2025
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Aurelien Nam Phong Tran, Yuki Sasaki
  • Patent number: 12206686
    Abstract: The present disclosure relates to Overlay Content Forwarding (OCF) Methods to transfer data across a wide area network without introducing a single point of data breach or wire-tapping on a Zero Trust Data transfer paradigm. Methods are applied on a system built upon Data Transport Controllers (DTC) and USC with AIOps capabilities. System modules are deployed across various geo locations in a Wide Area Network, operating at the control of Universal Security Controller (USC). USC extracts system, security and storage activity telemetry data from DTC controllers, update Routes through XML updates and Routing update exchanges, to orchestrate Autonomous, de-duplicated, segmented data forwarding across exclusive path overlay network guided by AIOps mechanisms. Data is segmented in unintelligible manner based on information theory and sent across different, exclusive path across DTC nodes in an overlay network in different application sessions and reassembled at destination DTC node to recover the original content.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: January 21, 2025
    Inventor: Peter Chacko
  • Patent number: 12189526
    Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: January 7, 2025
    Assignee: SK hynix Inc.
    Inventor: Hye Mi Kang
  • Patent number: 12177328
    Abstract: Embodiments protect against memory-based side-channel attacks by efficiently shuffling data. In an example implementation, in response to a data access request by an encryption methodology regarding a first data element from amongst a plurality of data elements stored in memory, a storage address of a second data element of the plurality is determined. This storage address is determined using (i) an address of the first data element in the memory, (ii) a permutation function, and (iii) a random number. In turn, the first data element is stored at the determined storage address of the second data element and the second data element is stored at the address of the first data element. In this way, embodiments protect encryption methodologies from memory-based side-channel attacks.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: December 24, 2024
    Assignee: NORTHEASTERN UNIVERSITY
    Inventors: Yunsi Fei, Zhen Jiang
  • Patent number: 12174786
    Abstract: Techniques described herein relate to a method for performing data protection of file system data on a host. The method includes identifying, by a data protection agent, a backup access event associated with a backup of a file system stored on a backup storage; in response to identifying the backup access event: obtaining backup metadata associated with the backup from a data protection manager; generating a placeholder file system using the backup metadata and storing the placeholder file system in virtual hard disk file; loading the virtual hard disk file on a target application; performing, after the loading, prefetching of backup data using the virtual hard disk file and the backup metadata to store the backup data in a cache; and performing backup access services using the virtual hard disk file, the backup metadata, and the cache.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: December 24, 2024
    Assignee: Dell Products L.P.
    Inventors: Sunil Yadav, Shelesh Chopra
  • Patent number: 12178041
    Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, Brett D. Lowe
  • Patent number: 12158859
    Abstract: An amount of expiration time extension for one or more objects associated with a first archive of a first snapshot of a source storage is determined based at least in part on a second data management policy associated with a second archive and one or more dynamically determined metrics. The first archive that includes the one or more objects is caused to be stored to a remote storage. At least a portion of content of the first archive is referenced by data chunks stored in a first chunk object of the remote storage and the first archive is associated with a first data management policy. Based on the determined amount of expiration time extension, an expiration time for the one or more objects associated with the first archive is stored in an archive metadata of the one or more objects associated with the first archive.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: December 3, 2024
    Assignee: Cohesity, Inc.
    Inventors: Dane Van Dyck, Praveen Kumar Yarlagadda
  • Patent number: 12147352
    Abstract: A method, including: identifying static application features of an application; identifying resource access features of the application; labeling a translation lookaside buffer (TLB) miss threshold of a runtime feature of the application; determining utilization of larger pages during the runtime based on the TLB miss threshold; and setting the TLB miss threshold based on the determined utilization of the larger pages.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: November 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naijie Li, Dong Hui Liu, Jing Lu, Peng Hui Jiang, Xiao Yan Tang, Bao Zhang, Yong Yin, Jun Su, Jia Yu
  • Patent number: 12131181
    Abstract: The removal of software operators can be managed according to some aspects described herein. In one example, a system can receive a command to remove an operator from a computing cluster and, in response, determine a set of actions previously performed in the computing cluster in relation to adding the operator to the computing cluster. Each action can involve the creation, modification, or deletion of at least one object in the computing cluster. The system can also determine a particular order in which the set of actions were previously performed relative to one another. The system can then assist with removing the operator from the computing cluster by causing an inverse of each action in the set of actions to be performed in the computing cluster in a reverse order to the particular order.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 29, 2024
    Assignee: Red Hat, Inc.
    Inventors: Arie Bregman, Steve Mattar
  • Patent number: 12112045
    Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a buffer memory, a first volatile memory, a second volatile memory, a processor and a buffer context backup circuit. The buffer memory temporarily stores read data and write data. The first and second volatile memories are included in different power domains. The processor generates buffer allocation information, stores the buffer allocation information in the first volatile memory, and controls an access to the buffer memory based on the buffer allocation information. The buffer context backup circuit performs a context backup operation to back up the buffer allocation information from the first volatile memory to the second volatile memory when entering a power down mode and performs a context restoring operation to restore the buffer allocation information from the second volatile memory to the first volatile memory when exiting from the power down mode.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 8, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seongwan Hong, Youngmin Lee
  • Patent number: 12111838
    Abstract: A system includes one or more memory devices storing instructions, and one or more processors configured to execute the instructions to perform steps of a method for processing a large file. The system may receive record data comprising a plurality of records having an identification value in a common field having a data format. The system may determine a plurality of focus values based on the data format and create a plurality of virtual processing units based on the plurality of focus values. Each of the plurality of virtual processing units may process a sub-group of the plurality of records that corresponds to the focus value associated with the respective virtual processing unit.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: October 8, 2024
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventor: Japan Bhatt
  • Patent number: 12099408
    Abstract: An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 24, 2024
    Assignee: Intel Corporation
    Inventors: Duane E. Galbi, Matthew J. Adiletta
  • Patent number: 12093564
    Abstract: A die command from a requestor is received. The die command into a die command queue is stored. The die command from the die command queue into a plurality of partition commands is partitioned. The plurality of partition commands into one of a first plurality of partition command queues or a second plurality of partition command queues is mapped. The partition command of the first plurality of partition command queues or the second plurality of partition command queues is issued to a command processor to be applied to the one or more memory devices.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: September 17, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Juane Li, Jason Duong, Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu
  • Patent number: 12093947
    Abstract: The disclosure proposes a method in a first device comprising a transaction history and a generation counter, this device processing transactions with a second device. During a current transaction: receipt of data comprising a public key of the second device, a second generation counter and an identifier of the current transaction; verification that the first and second generation counters coincide; verification that the history comprises an input associated with the public key; approval of the current transaction if the transaction identifier satisfies a condition indicating the uniqueness of the current transaction; storage in the history of a new input with the public key; and update of an account balance to pay a credit to an account. The method also comprises: detection of a risk of saturation of the memory of the first device; update of the first generation counter and eviction of the memory.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: September 17, 2024
    Assignee: IDEMIA FRANCE
    Inventors: Emmanuelle Dottax, Lauren Del Giudice
  • Patent number: 12066945
    Abstract: An embodiment of an integrated circuit may comprise a core, a first level core cache memory coupled to the core, a shared core cache memory coupled to the core, a first cache controller coupled to the core and communicatively coupled to the first level core cache memory, a second cache controller coupled to the core and communicatively coupled to the shared core cache memory, and circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Prathmesh Kallurkar, Anant Vithal Nori, Sreenivas Subramoney
  • Patent number: 12061545
    Abstract: Techniques are disclosed relating to managing page pools for sets of processing work. In some embodiments, a processor assigns sets of processing work to respective primary slots. Page manager circuitry may maintain, in a memory, page pool descriptor information for memory pages allocated to multiple different page pools, maintain a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools, and cache page pool descriptor entries in the page pool descriptor cache. The page manager circuitry may provide pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. In some embodiments, the page manager circuitry pre-fetches virtual pages. The page manager circuitry may include primary and distribute components.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: August 13, 2024
    Assignee: Apple Inc.
    Inventors: Arjun Thottappilly, Frank W. Liljeros
  • Patent number: 12061812
    Abstract: Unmap extents transmitted in delta sets are used to unmap LBAs on remote replicas of asynchronously replicated storage objects. A host server sends a SCSI unmap command to a production storage array to unmap a range of logical block addresses. In response, the production storage array creates an unmap extent that identifies the local and remote replicas, starting LBA, and number of LBAs to be unmapped. At the end of each asynchronous replication cycle, unmap extents and updated data are sent to a disaster recovery storage array in a delta set that preserves chronological ordering. The disaster recovery storage array receives the delta set and discards cached data corresponding to the unmapped LBAs indicated in the unmap extents and de-allocates the backend storage space. Integrating unmap extents with updated data in delta sets maintains point-in-time consistency and is more efficient than sending zero data.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: August 13, 2024
    Assignee: Dell Products L.P.
    Inventors: Guruprasad Pattar, Jeffrey Wilson, Benjamin Yoder
  • Patent number: 12056086
    Abstract: An information management system according certain aspects for archiving file system content may include a third-party application archiving data agent configured to: access third-party application archiving rules for archiving data to one or more secondary storage devices, wherein the third-party application archiving rules are defined by a third-party application to archive files associated with the third-party application; access third-party metadata associated with a plurality of files in a file system, wherein the plurality of files is associated with the third-party application and the third-party metadata is defined by the third-party application; determine whether to archive one or more files of the plurality of files based at least in part on the third-party application archiving rules and the third-party metadata; and in response to determining that a first file of the plurality of files should be archived, archive the first file to the one or more secondary storage devices.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: August 6, 2024
    Assignee: Commvault Systems, Inc.
    Inventors: Jun H. Ahn, Waqas Ashraf, Arun Kumar Krishna Shankar
  • Patent number: 12050551
    Abstract: A data management system (DMS) may support intelligent snapshot protection techniques. For example, the DMS may backup a computing system and facilitate that capture and storage of snapshots of the computing system. The DMS may identify a deletion event associated with one or more of the snapshots, the deletion event being associated with the one or more snapshots being deleted at a first time. The DMS may determine that deletion event is anomalous and retain the one or more snapshots beyond the first time. For example, the DMS may determine that one or more parameters associated with the deletion event are indicative of the deletion event being anomalous. In response, the DMS may retain the one or more snapshots for a retention period beyond the first time.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: July 30, 2024
    Assignee: Rubrik, Inc.
    Inventors: Daniel Mark Rogers, Soham Mazumdar, Michael Wronski, Inderpal Arora, Mudit Malpani, Vasu Murthy
  • Patent number: 12001714
    Abstract: An apparatus in one embodiment comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to obtain buffer availability information from a storage system, the buffer availability information indicating that the storage system is currently experiencing a deficiency in a number of available buffers of a given one of at least first and second different buffer sizes supported by the storage system, and to select particular input-output operations for delivery to the storage system over one or more networks based at least in part on the obtained buffer availability information. Obtaining the buffer availability information from the storage system illustratively comprises sending at least one command from a host device to the storage system. First and second different buffer types having the first and second different buffer sizes may comprise respective different write buffer types within a larger write buffer.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 4, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Krishna Deepak Nuthakki, Arieh Don
  • Patent number: 11989093
    Abstract: Methods and apparatus for selection of memory devices in a distributed storage network. In an example, a computing device receives a data object for storage and selects a set of storage nodes of a plurality of sets of storage nodes for storing the data object. Selection of the set of storage nodes includes determining storage attributes associated with each set of storage nodes of the plurality of sets of storage nodes. Selection of the set of storage nodes additionally includes determining a storage preference associated with the data object, and comparing the storage preference with the storage attributes of the plurality of sets of storage nodes to determine a best match. Following selection of a set of storage nodes, the computing device facilitates storage of the data object in the selected set of storage nodes.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: May 21, 2024
    Assignee: Pure Storage, Inc.
    Inventors: S. Christopher Gladwin, Timothy W. Markison, Greg R. Dhuse, Thomas F. Shirley, Jr., Wesley B. Leggette, Jason K. Resch, Gary W. Grube
  • Patent number: 11983606
    Abstract: Disclosed are a method and device for constructing a quantum circuit of a QRAM architecture, the QRAM architecture being configured for accessing data and being a binary tree structure, the method including: partitioning the binary tree structure into basic circuit structures, wherein a basic circuit structure comprises address bits and data bits of one subtree node and data bits of two child nodes in the lower layer of the one subtree node; determining qubits required for a basic quantum circuit to be constructed, according to qubits included in the basic circuit structure; determining an input and an output of the basic quantum circuit to be constructed, according to action relationships between the qubits required for the basic quantum circuit to be constructed; and constructing a basic quantum circuit corresponding to the basic circuit structure, according to the input and the output using the required qubits and quantum logic gates.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: May 14, 2024
    Assignee: Origin Quantum Computing Technology (Hefei) Co., Ltd.
    Inventors: Ye Li, Ningbo An, Menghan Dou
  • Patent number: 11983204
    Abstract: The mobile terminal-oriented complex condition geographic information query method, device and medium are disclosed, and the method includes: determining geographic information query condition semantics, and setting complex condition query contents according to condition semantic regulations; based on a preset query rule, analyzing conditions meeting the rule, and obtaining attribute information of target objects and attribute information of condition objects forming complex conditions; and according to the attribute information of the target objects and the attribute information of the condition objects, performing server calculation query and returning a geographic information query result. Based on collection, storage and classification of the geographic entity position information, the geographic entity position information of a specific type and space limitation is inquired, so that the function of simultaneously limiting the conditions of target objects by the mobile terminal is enriched.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: May 14, 2024
    Assignee: BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Shuai Zhao, Bo Cheng, Shengjie Li, Junliang Chen
  • Patent number: 11977489
    Abstract: Apparatuses, systems, and techniques for memory management are disclosed. In at least one embodiment, memory management is provided for a heterogenous system, for example, a system including a CPU and a GPU, in which redundant or unnecessary memory transfers are reduced.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA Corporation
    Inventors: Weixi Zhu, Guilherme Cox
  • Patent number: 11940919
    Abstract: System and techniques for recall pending cache line eviction are described herein. A queue that includes a deferred memory request is kept for a cache line. Metadata for the queue is stored in a cache line tag. When a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request ID. After the recall request is transmitted, the memory request ID is written to a second recall storage referenced by the message ID of the recall request. Upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message ID in the response to lookup the memory request ID from the second recall storage, then using the memory request ID to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony M. Brewer
  • Patent number: 11934695
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chandramani, Dinesh Agarwal, Sharath Shivakumar, Ruchir Sinha
  • Patent number: 11907556
    Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
  • Patent number: 11907725
    Abstract: A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: February 20, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Richard Osborne, Matthew Fyles
  • Patent number: 11893243
    Abstract: A storage system has a memory that is organized in wordlines. Each wordline has a number of strings. A controller in the storage system changes, in each of the wordlines, which of the strings is a last string programmed. Doing so can unmask a program disturb error when triple-level cells in the memory are used as pseudo-multi-level cells. By unmasking the program disturb error, the controller can detect and correct the error.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel J. Linnen, Prakash Subedi, Khanfer A. Kukkady, Mark Murin
  • Patent number: 11875045
    Abstract: A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: January 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jixing Chen, Weibing Shang
  • Patent number: 11868271
    Abstract: A method for accessing compressed computer memory residing in physical computer memory is disclosed. In the method, compressed memory blocks are represented as sectors, wherein all sectors contain a fixed number of compressed memory blocks, have a fixed logical size in the form of the fixed number of compressed memory blocks, and have varying physical sizes in the form of the total size of data stored in the respective compressed memory blocks.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 9, 2024
    Assignee: Zeropoint Technologies AB
    Inventors: Angelos Arelakis, Vasileios Spiliopoulos, Per Stenström
  • Patent number: 11853202
    Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventor: Hye Mi Kang
  • Patent number: 11841873
    Abstract: Data sources provide access to data. The data stored by the data source may be transformed before use by an application. Different data sources support different transformations. A data agent sidecar for the application accepts work orders from the application and submits work orders to data sources. A work order identifies a data source from which data is requested. The work order optionally includes one or more transformations to be applied to the data from the data source. The data agent sidecar determines, for the data source from which data is requested, which transformations can be performed by the data source and which transformations are not supported by the data source. The data transformations that can be performed by the data source are included in the work order to the data source. The remaining data transformations are performed by the data agent sidecar.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 12, 2023
    Assignee: SAP SE
    Inventors: Daniel Bos, Qing Liu, Tobias Maximilian Karpstein
  • Patent number: 11824932
    Abstract: An information management system according to certain aspects can implement application archiving. The system may archive one or more applications on computing devices to make more storage space available on these devices. The system can determine which applications on client computing device to archive based on various factors. Some examples of factors can include frequency of use, application type, amount of application data and/or storage, user and/or device location, etc. The data to be archived can include one or more executable file(s), metadata, actual data, etc. After an application is archived, the system can generate a placeholder for the application; a placeholder can include information for restoring the archived application.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: November 21, 2023
    Assignee: Commvault Systems, Inc.
    Inventors: Bhavyan Bharatkumar Mehta, Rajiv Kottomtharayil, Tirthankar Chatterjee, Jun H. Ahn
  • Patent number: 11809283
    Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for deleting backup data. The method includes determining a set of non-backup time periods for an object based on a set of backup time periods for the object. The method further includes selecting a subset of non-backup time periods from the set of non-backup time periods on the basis of a time length. The method further includes deleting backup data of the object in the subset of non-backup time periods. By the embodiments of the present disclosure, a suitable time period can be selected, and unnecessary backup data is effectively deleted from the selected time period, thus improving the success rate of deletion of backup data.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: November 7, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Zengjie Zhang, Jinru Yan, Yudai Wang, Kai Ji, Zheyi Zhu
  • Patent number: 11797575
    Abstract: A request may be received to transform records in a data lake that match one or more query criteria. Data lake records that match the criteria may be retrieved. The retrieved records may include two data lake records associated with the same data lake record identifier. A transformed record may be generated based on time stamps associated with the retrieved records.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: October 24, 2023
    Assignee: Salesforce, Inc.
    Inventors: Shreedhar Sundaram, Mahalaxmi Sanathkumar, Aaron Zhang, Parin Kenia, Violet Gong, Priya Sethuraman, Zhidong Ke, Kevin Terusak
  • Patent number: 11797525
    Abstract: Techniques for reconstructing or building metadata pages in storage nodes that have a delta-log based architecture. The techniques include walking “up” an ancestor chain of a metadata page, detecting the most recent delta update for a metadata entry of the metadata page, writing the most recent delta update to a location of the metadata entry in the metadata page, setting a bitmap entry corresponding to the location of the metadata entry in the metadata page, detecting a less recent delta update for the metadata entry of the metadata page, and, having previously set the bitmap entry corresponding to the location of the metadata entry in the metadata page, avoiding writing the less recent delta update to the location of the metadata entry in the metadata page. In this way, the need to save in memory the entire ancestor chain of the metadata page can be eliminated.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 24, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Ami Sabo
  • Patent number: 11790993
    Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: October 17, 2023
    Assignee: Kioxia Corporation
    Inventors: Riki Suzuki, Yoshihisa Kojima
  • Patent number: 11777790
    Abstract: The present invention relates to methods and apparatus for migrating and/or changing the allocation of network interface(s) or Internet Protocol address(es) of network interface(s) from one Pod, e.g., a failed Pod, to another Pod, e.g., a live Pod, in a Kubernetes system. An exemplary method of operating a Kubernetes system in accordance with an embodiment of the invention includes: establishing, by the Kubernetes system, a first service including a first Pod located on a first node and a second Pod located on a second node, allocating by the Kubernetes system an external network interface including an Internet Protocol address for use by the first Pod, the allocation of said external network interface for use by the first Pod being unknown to a first Kubelet managing the first node; and upon failure of the first Pod, changing allocation of the external network interface from the first Pod to the second Pod.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 3, 2023
    Assignee: Ribbon Communications Operating Company, Inc.
    Inventors: Tolga Asveren, Souvik Dey, Mark St. Pierre, Suyash Suhas Karmarkar
  • Patent number: 11768763
    Abstract: A system with storage memory and a processing device has a logical deletion to physical erasure time bound. The system dereferences data, responsive to a direction to delete the data. The system monitors physical blocks in storage memory for live data and the dereferenced data. The system cooperates garbage collection with monitoring the physical blocks, so that at least a physical block having the dereferenced data is garbage collected and erased within a logical deletion to physical erasure time bound.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 26, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Igor Ostrovsky, Constantine P. Sapuntzakis, Peter E. Kirkpatrick, John Colgrove
  • Patent number: 11762573
    Abstract: A method of preserving the contiguity of large pages of a workload during migration of the workload from a source host to a destination host includes the steps of: detecting at the destination host, receipt of a small page of zeros from the source host, wherein, at the source host, the small page is part of one of the large pages of the workload; and upon detecting the receipt of the small page of zeros, storing, at the destination host, all zeros in a small page that is part of one of the large pages of the workload.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: September 19, 2023
    Assignee: VMware, Inc.
    Inventors: Arunachalam Ramanathan, Yury Baskakov, Anurekh Saxena, Ying Yu, Rajesh Venkatasubramanian, Michael Robert Stunes
  • Patent number: 11763896
    Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seungjune Jeon, Zhenming Zhou, Zhenlei Shen
  • Patent number: 11740801
    Abstract: This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: August 29, 2023
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, Alan Chen, Robert Lercari
  • Patent number: 11734277
    Abstract: An approach is provided for optimizing a database buffer pool. Based on statistics about read and write operations in a range of pages, the range of pages is determined to be a candidate for a hot read range for which locks and latches are avoided in processing operations in the hot read range. Using an on-time trigger or pre-trigger process, the hot read range is created from the range of pages by marking start and end points in the range of pages. Write operation(s) are determined to be included in the hot read range by marking an object control block. The write operation(s) are added to a write pending list. The read operations in the hot read range are performed without a latch or lock. The write operation(s) are merged from the write pending list to the range of pages and the write operation(s) are performed.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Shuo Li, Xiaobo Wang, Hong Mei Zhang, Sheng Yan Sun
  • Patent number: 11734113
    Abstract: A solid state disk access method includes: determining, in response to a read error, a first read voltage of the current data block according to a current data storage time interval to which a data storage time of the current data block belongs; performing reread error correction on the data in the current data block based on the first read voltage; determining, if reread error correction of the current data block fails, a second read voltage corresponding to the current data block according to the current data storage time interval and a preset data read rule that is determined based on the data storage time interval and the number of data reads; and performing reread error correction on the data in the current data block based on the second read voltage until the reread error correction of the current data block meets a preset reread error correction condition.
    Type: Grant
    Filed: February 20, 2021
    Date of Patent: August 22, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Wenhao Shao
  • Patent number: 11726963
    Abstract: A data storage system for use with a multi-threaded processing system receives concurrent requests to store data to a common data store, and efficiently and securely swaps an active data store for a new data store while avoiding conflicts arising from multiple threads attempting to swap a same data store and minimizing reliance on operations that re-attempt actions upon failure of an attempted action, thereby improving performance of the data storage system and also the multi-threaded processing system.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: August 15, 2023
    Assignee: Chicago Mercantile Exchange Inc.
    Inventor: Kyle D. Kavanagh
  • Patent number: 11714573
    Abstract: Techniques for storage optimization in a distributed object store are described. A storage optimization service of a provider network monitors changes to data objects in a distributed object store that are part of a data lake and are referenced by a table index. The storage optimization service determines whether particular storage optimizations involving the data objects would be beneficial, prioritizes the ordering of these optimizations with a focus on performing impactful optimizations first, while intelligently scheduling the optimizations to avoid overutilization of available resources.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: August 1, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Shashank Bhardwaj, Roman Gavrilov, Brian Scott Ross, Mehul A. Shah, Benjamin Sowell, Anthony A. Virtuoso, Linan Zheng
  • Patent number: 11693663
    Abstract: Methods and apparatus for managing circular queues are disclosed. A pointer designates an index position of a particular queue element and contains an additional pointer state, whereby two pointer values (split indexes) can designate the same index position. Front and rear pointers are respectively managed by dequeue and enqueue logic. The front pointer state and rear pointer state distinguish full and empty queue states when both pointers designate the same index position. Asynchronous dequeue and enqueue operations are supported, no lock is required, and no queue entry is wasted. Hardware and software embodiments for numerous applications are disclosed.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: July 4, 2023
    Assignee: UT-Battelle, LLC
    Inventors: Narasinga Rao Miniskar, Frank Y. Liu, Jeffrey S. Vetter