Concurrent Accessing Patents (Class 711/168)
  • Patent number: 10776276
    Abstract: Examples may bypass storage class memory (SCM) read cache based on a queue depth threshold. Examples may adjust a queue depth threshold for an SCM read cache based on an amount of data read from and written to the SCM read cache in a time period, and may bypass the SCM read cache based on a comparison of a number of outstanding IOs for the SCM read cache to a queue depth threshold for the SCM read cache.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 15, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gurinder Shergill, Kouei Yamada
  • Patent number: 10740237
    Abstract: In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 11, 2020
    Assignee: NXP USA, Inc.
    Inventors: Andrey Kovalev, George Adrian Ciusleanu, Richard Soja
  • Patent number: 10678698
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The data writing method includes transmitting a command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in a sequence order in the host system, obtaining first data among the plurality of data and obtaining second data after obtaining the first data. The method further includes writing the first data to a corresponding physical page on a first word line among a plurality of word lines, and writing the second data to another corresponding physical page on a second word line among the plurality of word lines, wherein the first and second word lines belong to first and second memory sub-modules, and the first data and the second data are discontinuously arranged in the sequence order. The first and second data may each comprise sub-data, and the sub-data may be written into physical pages on the first and second word lines.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: June 9, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10664178
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz
  • Patent number: 10620880
    Abstract: Provided are a computer program product, system, and method for using a delay timer to delay code load operations to process queued write requests. A code load is performed to a selected storage device in a storage array comprised of a plurality of the storage devices. Writes are queued to the storage array in a non-volatile storage while performing the code load. A determination is made as to whether the queued writes to the storage array exceed a threshold. A delay timer is started in response to determining that the queued writes to the storage array exceed the threshold. An additional code load is initiated to an additional selected storage device in the storage array in response to determining that the delay timer has expired. The additional code load is initiated to the additional selected storage device in response to determining that the queued writes are less than the threshold.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Samantha A. Utter, Kevin J. Ash, Karl A. Nielsen, Matthew J. Kalos
  • Patent number: 10621119
    Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Sun Young Lim, Indong Kim, Jangseok Choi, Craig Hanson
  • Patent number: 10599178
    Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Michael C. Rifani, Alan B. Kyker, Alan S. Geist, David M. Lee
  • Patent number: 10552347
    Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Yoichi Yuyama
  • Patent number: 10496448
    Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: December 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, David J. Cowperthwaite, Abhishek R. Appu, Joydeep Ray, Vasanth Ranganathan, Altug Koker, Balaji Vembu
  • Patent number: 10275247
    Abstract: Methods and apparatuses relating to accelerating vector multiplication. In one embodiment, an apparatus includes a first buffer to store a first cache line of indices for elements of a first vector, a second buffer to store a second cache line of indices for elements of a second vector, a comparison unit to compare each index of the first cache line of indices with each index of the second cache line of indices, a plurality of multipliers to each multiply an element from the first vector and an element from the second vector for an index match from the comparison unit to produce a product, and an adder to add together the product from each of the plurality of multipliers.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Asit K. Mishra, Deborah T. Marr
  • Patent number: 10262391
    Abstract: A graphics processing unit (GPU) configured to perform a graphics pipeline may generate operation data based on base operation data representing a base state of a plurality of components and implement the plurality of components to perform the graphics pipeline according to the generated operation data. The GPU may determine a priority of a plurality of instances of state version data based on frequencies of use associated with the plurality of instances of state version data, maintain first state version data having a determined highest priority from among the plurality of instances of state version data, and control second state version data having a determined lower priority than the first state version data to be updated based on a graphics pipeline being performed. The state version data may include code associated with performing the graphics pipeline in each of a plurality of states of the plurality of components.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghun Jin, Santosh George Abraham
  • Patent number: 10061618
    Abstract: Aspects include computation systems that can identify computation instances that are not capable of being reentrant, or are not reentrant capable on a target architecture, or are non-reentrant as a result of having a memory conflict in a particular execution situation. A system can have a plurality of computation units, each with an independently schedulable SIMD vector. Computation instances can be defined by a program module, and a data element(s) that may be stored in a local cache for a particular computation unit. Each local cache does not maintain coherency controls for such data elements. During scheduling, a scheduler can maintain a list of running (or runnable) instances, and attempt to schedule new computation instances by determining whether any new computation instance conflicts with a running instance and responsively defer scheduling. Memory conflict checks can be conditioned on a flag or other indication of the potential for non-reentrancy.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: August 28, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Luke Tilman Peterson, James Alexander McCombe
  • Patent number: 9940137
    Abstract: Data processing apparatus comprises a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception t
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: April 10, 2018
    Assignee: ARM Limited
    Inventors: Matthew Lee Winrow, Antony John Penton
  • Patent number: 9934828
    Abstract: Systems and methods are provided for a sense amplifier/write driver circuit. A system includes a set of transistors responsive to a memory cell, the set of transistors configured to operate as a sense amplifier in a first mode and to operate as a write driver in a second mode. One or more switches are configured to switch the set of transistors from the first mode to the second mode based on a control signal. Particular transistors of the set of transistors are configured by the one or more switches to amplify and retain data at a pair of input/output nodes for a period of time in the first mode. The particular transistors are further configured by the one or more switches to drive data to the pair of input/output nodes in the second mode.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Kai Hsieh, Cheng Hung Lee, Fu-An Wu
  • Patent number: 9870316
    Abstract: A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 16, 2018
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Ronny Van Keer, Guillaume Docquier
  • Patent number: 9851915
    Abstract: A memory device includes a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells. A control circuit performs a first read/write operation during a first time interval by writing a first data value to the first group while concurrently reading a second data value from the second group. The control circuit performs a second read/write operation during a second time interval, which is after the first time interval, by writing a third data value to the third group while concurrently reading a fourth data value from the fourth group. The first and third data values are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device prior to the first time interval.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang Ting Chen, Ching-Wei Wu
  • Patent number: 9727459
    Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 8, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Antoine Khoueir, Ryan James Goss, Jon Trantham, Kevin Gomez, Frank Dropps
  • Patent number: 9547623
    Abstract: A flexible memory interface system includes a control module, instruction memory, a command processing unit, an address processing unit, and a data processing unit. The control module controls storing and retrieving of a command portion, an addressing portion, and data of an instruction to access memory to and from the instruction memory and the command processing unit, the address processing unit, and the data processing unit, respectively. The command processing unit is operably coupled to process a command portion of an instruction to access memory. The address processing unit is operably coupled to process an addressing portion of the instruction to access the memory. The data processing unit is operably coupled to process data conveyance to or from the external memory based on the instruction to access the memory.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: January 17, 2017
    Assignee: SIGMATEL, INC.
    Inventors: Steve Vu, Jean Charles Pina
  • Patent number: 9448926
    Abstract: A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: September 20, 2016
    Assignee: Proton World International N.V.
    Inventors: Ronny Van Keer, Guillaume Docquier
  • Patent number: 9405687
    Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Bahaa Fahim, Samuel D. Strom, Vedaraman Geetha, Robert G. Blankenship, Yen-Cheng Liu, Krishnakumar Ganapathy, Cesar Maldonado
  • Patent number: 9372752
    Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Patent number: 9342452
    Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: May 17, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gary Gostin, Craig Warner, John W Bockhaus
  • Patent number: 9335940
    Abstract: A method includes storing an operating system in minor stripes on a first data storage device forming a first logical storage unit, and storing data in major stripes across a plurality of data storage devices forming a second logical data storage unit. Each major stripe includes a plurality of minor stripes storing data and a parity stripe. The method further includes calculating the parity stripe from the plurality of minor stripes within the major stripe and a corresponding one of the minor stripes on the first data storage device, wherein the minor stripes on the first data storage device match the size of the minor stripes on the array of data storage devices.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 10, 2016
    Assignee: Lenovo Enterprises Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Lydia M. Do, Christopher J. Hardee, Adam Roberts
  • Patent number: 9292205
    Abstract: The invention may be embodied in a multiple-disk data storage system including a controller module that initiates an optimization algorithm to set maximum queue depth of each disk of the data storage system to desired queue depth of each disk. Desired queue depth of each disk may be associated with performance factors including, but not limited to, input/output operations per second (IOPs), average response time, and/or maximum response time of each disk. Desired queue depth of each disk may be further associated with priority rankings of performance factors.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 22, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Kapil Sundrani
  • Patent number: 9280293
    Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method includes storing an operating system in minor stripes on a first data storage device forming a first logical storage unit, and storing data in major stripes across a plurality of data storage devices forming a second logical data storage unit. Each major stripe includes a plurality of minor stripes storing data and a parity stripe. The method further includes calculating the parity stripe from the plurality of minor stripes within the major stripe and a corresponding one of the minor stripes on the first data storage device, wherein the minor stripes on the first data storage device match the size of the minor stripes on the array of data storage devices.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 8, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Lydia M. Do, Christopher J. Hardee, Adam Roberts
  • Patent number: 9268697
    Abstract: A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Ilan Pardo, Niranjan Cooray, Stanislav Shwartsman, Shlomo Raikin
  • Patent number: 9263106
    Abstract: An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 16, 2016
    Assignee: NVIDIA CORPORATION
    Inventor: Alok Gupta
  • Patent number: 9256557
    Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: February 9, 2016
    Assignee: Rambus Inc.
    Inventors: Craig E. Hampel, Frederick A. Ware
  • Patent number: 9251380
    Abstract: A storage drive includes a first memory that stores first text. A first processor generates a first instruction to decrypt the first text. A cryptographic module includes a second memory, a cryptographic device, a memory module, and a second processor. The second memory is inaccessible to the first processor and stores a cryptographic key. The cryptographic device accesses the second memory to obtain the cryptographic key and based on the first instruction, decrypts the first text. The memory module stores a status of execution of the first instruction by the cryptographic device. The second processor, prior to the cryptographic device decrypting the first text, forwards the first instruction to the cryptographic device and stores the status of execution of the first instruction in the memory module. The memory module is connected between the first and second processors and isolates the first processor from the second processor.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 2, 2016
    Assignee: Marvell International Ltd.
    Inventors: Siu-Hung Fred Au, Gregory Burd, Wayne C. Datwyler, Leonard J. Galasso, Tze Lei Poo, Minda Zhang
  • Patent number: 9071269
    Abstract: A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: June 30, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Alon Kipnis, Itai Dror
  • Patent number: 9043518
    Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Terry M. Grunzke
  • Patent number: 9036718
    Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: David J. Zimmerman, Michael W. Williams
  • Patent number: 9038077
    Abstract: A system for providing model level protection for resources holding data accessed by multiple tasks in a model is discussed. The protection occurs at the model level so that the protection mechanism does not interfere with model dynamics. Resources concurrently accessed by multiple tasks are identified so that a unified protection mechanism can be applied to the resource. A user interface may be provided which enables the selection of a particular type of protection mechanism for the data in the resource. User supplied protection mechanisms may also be implemented.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 19, 2015
    Assignee: The MathWorks, Inc.
    Inventors: Biao Yu, James E. Carrick
  • Patent number: 9037827
    Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Feng Wang, Ethan Miller, Craig Harmer
  • Patent number: 9032174
    Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishiguchi
  • Patent number: 9032167
    Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating writing, in a sequential order, portions of the file data to a first buffer and a second buffer. The disclosure also provides for writing from a first buffer and a second buffer to a first track until the first track is filled.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 12, 2015
    Assignee: Comcast Cable Communications, LLC
    Inventor: Niraj K. Sharma
  • Patent number: 9026746
    Abstract: A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively; an address collision detection unit detecting collision between addresses in which the first and second CPUs respectively read and write the data signal from and to the dual port RAM; a first storage unit storing the data signal read by the first CPU; a second storage unit storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM when the collision between the addresses is detected; and a switching unit switching a reading source outputting the data signal to the port to which the first CPU is connected and outputting the read data signal to the first CPU entering a readable state.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 5, 2015
    Assignee: Sony Corporation
    Inventor: Shinjiro Tanaka
  • Patent number: 9026763
    Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On
  • Patent number: 9021228
    Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On
  • Publication number: 20150113244
    Abstract: When a first transaction needs to conduct a writing operation to first data, after there is a determination that there exists a second transaction that has conducted a reading operation of the first data or is to conduct a reading operation of the first data, a record that indicates a conflict between the writing operation of the first transaction and the reading operation of the second transaction is generated. A processing of the second transaction is performed. After the processing is completed, the second transaction is submitted and the first transaction is notified according to the record. A processing of the first transaction is performed. After the processing is completed and a notification of the second transaction is received, the first transaction is submitted. The present techniques improve concurrently visiting transaction memory at a multi-core system, avoid rollbacks incurred by conflicts, and improve overall system performance.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 23, 2015
    Inventors: Ling Ma, Sihai Yao, Lei Zhang
  • Patent number: 9009436
    Abstract: A method and system are disclosed herein for performing operations on a parallel programming unit in a memory system. The parallel programming unit includes multiple physical structures (such as memory cells in a row) in the memory system that are configured to be operated on in parallel. The method and system perform a first operation on the parallel programming unit, the first operation operating on only part of the parallel programming unit and not operating on a remainder of the parallel programming unit, set a pointer to indicate at least one physical structure in the remainder of the parallel programming unit, and perform a second operation using the pointer to operate on no more than the remainder of the parallel programming unit. In this way, the method and system may realign programming to the parallel programming unit when partial writes to the parallel programming unit occur.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: April 14, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventor: Nicholas James Thomas
  • Patent number: 9009410
    Abstract: A system and method for locking data in a cache memory. A first processing thread may be operated to run a program requesting data, where at least some of the requested data is loaded from a source memory into a non-empty cache. A second processing thread may be operated independently of the first processing thread to determine whether or not to lock the requested data in the cache. If the requested data is determined to be locked, the requested data may be locked in the cache at the same time as the data is loaded into the cache.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: April 14, 2015
    Assignee: Ceva D.S.P. Ltd.
    Inventors: Amos Rohe, Alex Shlezinger
  • Patent number: 9003121
    Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Weihuang Wang, Chien-Hsien Wu
  • Patent number: 9003154
    Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Montage Technology (Shanghai) Co., Ltd.
    Inventors: Chunyi Li, Qingjiang Ma
  • Publication number: 20150095606
    Abstract: A method, computer program product, and computing system for defining an optimal execution time (t) for a concurrent memory operation to be performed on a transactional memory system. An abort probability (p) is associated with the optimal execution time (t) based, at least in part, upon a probability curve. The probability curve is empirically derived and based upon the performance of the transactional memory system. A probable execution time (Ttm) is determined for the concurrent memory operation based, at least in part, upon the abort probability (p).
    Type: Application
    Filed: September 12, 2014
    Publication date: April 2, 2015
    Inventors: Alexeev Alexander Nikolayevich, Anton Genadyevich Pegushin, Rafikov Rustem Valeryevich
  • Patent number: 8977832
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8972688
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8972686
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8972650
    Abstract: Systems and methods are disclosed for increasing efficiency of read operations by selectively adding pages from a pagelist to a batch, such that when the batch is executed as a read operation, each page in the batch can be concurrently accessed. The pagelist can include all the pages associated a read command received, for example, from a file system. Although the pages associated with the read command may have an original read order sequence, embodiments according to this invention re-order this original read order sequence by selectively adding pages to a batch. A page is added to the batch if it does not collide with any other page already added to the batch. A page collides with another page if neither page can be accessed simultaneously. One or more batches can be constructed in this manner until the pagelist is empty.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Matthew Byom
  • Patent number: 8972689
    Abstract: A storage processor identifies latency of memory drives for different numbers of concurrent storage operations. The identified latency is used to identify debt limits for the number of concurrent storage operations issued to the memory drives. The storage processor may issue additional storage operations to the memory devices when the number of storage operations is within the debt limit. Storage operations may be deferred when the number of storage operations is outside the debt limit.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: March 3, 2015
    Assignee: Violin Memory, Inc.
    Inventor: Erik de la Iglesia