Abstract: Methods, systems, and computer program products for de-duplicating data in executable files in a container image are disclosed. The method may include receiving a request to read a file in a first layer in a container image including a plurality of layers, wherein the file is a delta file which is from an updated executable file based on a base executable file, the base executable file is in a lower layer than the first layer in the container image, and the delta file includes block mappings between the updated executable file and the base executable file and different data between the two files, and blocks included in the two files are based on respective file structure. The method may also include restoring the updated executable file based on the delta file and the base executable file. The method may further include returning data in the updated executable file.

Abstract: Snapshots may be used to implement remote replication, for example, asynchronously, between a first storage system, A1, and a second storage system, A2. A1 may take a first snapshot, SS21, of a logical storage unit, R1. After the snapshot SS21 it taken, any dependent write operations associated with SS21 may be reconciled, and differences between SS21 and the last snapshot for R1, SS11, may be determined and recorded as a difference set. One or more replication instructions for R1 that include the write operations (or data and metadata corresponding thereto) of the difference set may be sent from A1 to A2. A2 may apply the differences to R2, and then take (activate) a snapshot of R2, SS22, which is a replica of SS21. After A2 activates SS22, A2 may send an acknowledgement to A1 indicating that SS22 has been activated, and A2 may take a next snapshot of R1.

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

Abstract: In one example, a command pattern sequencer includes a set of registers to store values used to configure a command sequence for configuring a memory. The command pattern sequencer further includes state machine circuitry coupled to the set of registers, the state machine circuitry configured to generate and execute the command sequence. The command pattern sequencer still further includes timing circuitry configured to manage timing between commands of the command sequence.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A dual-model memory interface of a computing system is provided, configurable to present memory interfaces having differently-graded bandwidth capacity to different processors of the computing system. A mode switch controller of the memory interface controller, based on at least an arbitration rule written to a configuration register, switches the memory interface controller between a narrow-band mode and a wide-band mode. In each mode, the memory interface controller disables either a plurality of narrow-band memory interfaces of the memory interface controller according to a first bus standard, or a wide-band memory interface of the memory interface controller according to a second bus standard. The memory interface controller virtualizes a plurality of system memory units of the computing system as a virtual wide-band memory unit according to the second bus standard, or virtualizes a system memory unit of the computing system as a virtual narrow-band memory unit according to the first bus standard.

Abstract: Systems and methods for disseminating backup data sets to targets. Backup data sets are classified with an attribute. A gateway device between the backup application and potential target destinations for the backup data set determines where to send the backup data set based on the attribute.

Abstract: A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array.

Abstract: Techniques for dynamic application management are provided. For example, an apparatus comprises at least one processing platform configured to: execute a portion of an application program in a first virtual computing element, wherein the application program comprises at least one portion of marked code; receive a request for execution of the portion of marked code; determine, based at least in part on the portion of marked code, one or more cloud platforms on which to execute the portion of marked code; and cause the portion of marked code identified in the request to be executed on the one or more cloud platforms.

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

Abstract: According to one aspect of the present disclosure, a technique for job distribution within a grid environment includes receiving jobs at a submission cluster for distribution of the jobs to one or more execution clusters where each of the execution clusters has one or more execution hosts and maintains a pending job queue. A resource capacity corresponding to each respective execution cluster is determined, and resource requirements for the jobs is determined. A length of the pending job queue indicating a quantity of pending jobs to maintain in the pending job queue for the respective execution cluster is dynamically calculated and periodically adjusted based on the resource capacity and the resource requirements of the respective execution clusters. The jobs are allocated to the respective execution clusters according to the length of the pending job queue of the respective execution clusters.

Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

Abstract: An example operation includes one or more of receiving a smart contract code by an analyzer node, building, by the analyzer node, a control flow-graph comprising a plurality of basic code blocks based on the smart contract code, computing, by the analyzer node, a read and write set for each of the basic code blocks from the plurality of the basic code blocks, and determining, by the analyzer node, at least two basic code blocks from the plurality of the basic code blocks that may be executed in parallel.

Abstract: Embodiments for optimizing connectivity in a storage system by a processor. A preferred connectivity path may be determined between a host and a storage controller via one or more selected nodes, one or more storage virtualization systems, or combination thereof. A current connectivity path between the host and the storage controller may be determined to fail to match the preferred connectivity path. The host may be triggered to reconnect to the storage controller via the preferred connectivity path to enhance connectivity to between the host and the storage controller.

Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: Examples may bypass storage class memory (SCM) read cache based on a queue depth threshold. Examples may adjust a queue depth threshold for an SCM read cache based on an amount of data read from and written to the SCM read cache in a time period, and may bypass the SCM read cache based on a comparison of a number of outstanding IOs for the SCM read cache to a queue depth threshold for the SCM read cache.

Abstract: In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The data writing method includes transmitting a command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in a sequence order in the host system, obtaining first data among the plurality of data and obtaining second data after obtaining the first data. The method further includes writing the first data to a corresponding physical page on a first word line among a plurality of word lines, and writing the second data to another corresponding physical page on a second word line among the plurality of word lines, wherein the first and second word lines belong to first and second memory sub-modules, and the first data and the second data are discontinuously arranged in the sequence order. The first and second data may each comprise sub-data, and the sub-data may be written into physical pages on the first and second word lines.

Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: Provided are a computer program product, system, and method for using a delay timer to delay code load operations to process queued write requests. A code load is performed to a selected storage device in a storage array comprised of a plurality of the storage devices. Writes are queued to the storage array in a non-volatile storage while performing the code load. A determination is made as to whether the queued writes to the storage array exceed a threshold. A delay timer is started in response to determining that the queued writes to the storage array exceed the threshold. An additional code load is initiated to an additional selected storage device in the storage array in response to determining that the delay timer has expired. The additional code load is initiated to the additional selected storage device in response to determining that the queued writes are less than the threshold.

Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.

Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

Abstract: Methods and apparatuses relating to accelerating vector multiplication. In one embodiment, an apparatus includes a first buffer to store a first cache line of indices for elements of a first vector, a second buffer to store a second cache line of indices for elements of a second vector, a comparison unit to compare each index of the first cache line of indices with each index of the second cache line of indices, a plurality of multipliers to each multiply an element from the first vector and an element from the second vector for an index match from the comparison unit to produce a product, and an adder to add together the product from each of the plurality of multipliers.

Abstract: A graphics processing unit (GPU) configured to perform a graphics pipeline may generate operation data based on base operation data representing a base state of a plurality of components and implement the plurality of components to perform the graphics pipeline according to the generated operation data. The GPU may determine a priority of a plurality of instances of state version data based on frequencies of use associated with the plurality of instances of state version data, maintain first state version data having a determined highest priority from among the plurality of instances of state version data, and control second state version data having a determined lower priority than the first state version data to be updated based on a graphics pipeline being performed. The state version data may include code associated with performing the graphics pipeline in each of a plurality of states of the plurality of components.

Abstract: Aspects include computation systems that can identify computation instances that are not capable of being reentrant, or are not reentrant capable on a target architecture, or are non-reentrant as a result of having a memory conflict in a particular execution situation. A system can have a plurality of computation units, each with an independently schedulable SIMD vector. Computation instances can be defined by a program module, and a data element(s) that may be stored in a local cache for a particular computation unit. Each local cache does not maintain coherency controls for such data elements. During scheduling, a scheduler can maintain a list of running (or runnable) instances, and attempt to schedule new computation instances by determining whether any new computation instance conflicts with a running instance and responsively defer scheduling. Memory conflict checks can be conditioned on a flag or other indication of the potential for non-reentrancy.

Abstract: Data processing apparatus comprises a processor configured to execute instructions, the processor having a pipelined instruction fetching unit configured to fetch instructions from memory during a pipeline period of two or more processor clock cycles prior to execution of those instructions by the processor; exception logic configured to respond to a detected processing exception having an exception type selected from a plurality of exception types, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of an exception of that exception t

Abstract: Systems and methods are provided for a sense amplifier/write driver circuit. A system includes a set of transistors responsive to a memory cell, the set of transistors configured to operate as a sense amplifier in a first mode and to operate as a write driver in a second mode. One or more switches are configured to switch the set of transistors from the first mode to the second mode based on a control signal. Particular transistors of the set of transistors are configured by the one or more switches to amplify and retain data at a pair of input/output nodes for a period of time in the first mode. The particular transistors are further configured by the one or more switches to drive data to the pair of input/output nodes in the second mode.

Abstract: A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page.

Abstract: A memory device includes a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells. A control circuit performs a first read/write operation during a first time interval by writing a first data value to the first group while concurrently reading a second data value from the second group. The control circuit performs a second read/write operation during a second time interval, which is after the first time interval, by writing a third data value to the third group while concurrently reading a fourth data value from the fourth group. The first and third data values are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device prior to the first time interval.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: A flexible memory interface system includes a control module, instruction memory, a command processing unit, an address processing unit, and a data processing unit. The control module controls storing and retrieving of a command portion, an addressing portion, and data of an instruction to access memory to and from the instruction memory and the command processing unit, the address processing unit, and the data processing unit, respectively. The command processing unit is operably coupled to process a command portion of an instruction to access memory. The address processing unit is operably coupled to process an addressing portion of the instruction to access the memory. The data processing unit is operably coupled to process data conveyance to or from the external memory based on the instruction to access the memory.

Abstract: A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page.

Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: A method includes storing an operating system in minor stripes on a first data storage device forming a first logical storage unit, and storing data in major stripes across a plurality of data storage devices forming a second logical data storage unit. Each major stripe includes a plurality of minor stripes storing data and a parity stripe. The method further includes calculating the parity stripe from the plurality of minor stripes within the major stripe and a corresponding one of the minor stripes on the first data storage device, wherein the minor stripes on the first data storage device match the size of the minor stripes on the array of data storage devices.

Abstract: The invention may be embodied in a multiple-disk data storage system including a controller module that initiates an optimization algorithm to set maximum queue depth of each disk of the data storage system to desired queue depth of each disk. Desired queue depth of each disk may be associated with performance factors including, but not limited to, input/output operations per second (IOPs), average response time, and/or maximum response time of each disk. Desired queue depth of each disk may be further associated with priority rankings of performance factors.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method includes storing an operating system in minor stripes on a first data storage device forming a first logical storage unit, and storing data in major stripes across a plurality of data storage devices forming a second logical data storage unit. Each major stripe includes a plurality of minor stripes storing data and a parity stripe. The method further includes calculating the parity stripe from the plurality of minor stripes within the major stripe and a corresponding one of the minor stripes on the first data storage device, wherein the minor stripes on the first data storage device match the size of the minor stripes on the array of data storage devices.

Abstract: A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.

Abstract: An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A storage drive includes a first memory that stores first text. A first processor generates a first instruction to decrypt the first text. A cryptographic module includes a second memory, a cryptographic device, a memory module, and a second processor. The second memory is inaccessible to the first processor and stores a cryptographic key. The cryptographic device accesses the second memory to obtain the cryptographic key and based on the first instruction, decrypts the first text. The memory module stores a status of execution of the first instruction by the cryptographic device. The second processor, prior to the cryptographic device decrypting the first text, forwards the first instruction to the cryptographic device and stores the status of execution of the first instruction in the memory module. The memory module is connected between the first and second processors and isolates the first processor from the second processor.

Abstract: A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data.

Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Abstract: A system for providing model level protection for resources holding data accessed by multiple tasks in a model is discussed. The protection occurs at the model level so that the protection mechanism does not interfere with model dynamics. Resources concurrently accessed by multiple tasks are identified so that a unified protection mechanism can be applied to the resource. A user interface may be provided which enables the selection of a particular type of protection mechanism for the data in the resource. User supplied protection mechanisms may also be implemented.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.