Abstract: A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software.

Abstract: The invention provides, in one aspect, an improved system for data access comprising a file server that is coupled to a client device or application executing thereon via one or more networks. The server comprises static storage that is organized in one or more directories, each containing, zero, one or more files. The server also comprises a file system operable, in cooperation with a file system on the client device, to provide authorized applications executing on the client device access to those directories and/or files. Fast file server (FFS) software or other functionality executing on or in connection with the server responds to requests received from the client by transferring requested data to the client device over multiple network pathways. That data can comprise, for example, directory trees, files (or portions thereof), and so forth.

Abstract: An SD/SDIO host controller is disclosed, which includes a control register and interrupt generation module, an internal DMA module, an SD/SDIO command interface module, an SD/SDIO data interface module, and a frequency divider and trigger/sampling enable signal generation module which is connected to an output end of the control register and interrupt generation module; the frequency divider and trigger/sampling enable signal generation module employs a frequency divider to perform frequency division on a local high-speed clock so as to obtain the operating clock of the SD/SDIO card, and simultaneously generates a trigger/sampling enable signal by the frequency divider and enables the position of the enable signal to be adjustable with respect to the operating clock of the SD/SDIO card. The present invention is capable of solving the setup/hold time issues caused by delay in digital signals.

Abstract: Multi-threaded, transactional memory systems may allow concurrent execution of critical sections as speculative transactions. These transactions may abort due to contention among threads. Hardware feedback mechanisms may detect information about aborts and provide that information to software, hardware, or hybrid software/hardware contention management mechanisms. For example, they may detect occurrences of transactional aborts or conditions that may result in transactional aborts, and may update local readable registers or other storage entities (e.g., performance counters) with relevant contention information. This information may include identifying data (e.g., information outlining abort relationships between the processor and other specific physical or logical processors) and/or tallied data (e.g., values of event counters reflecting the number of aborted attempts by the current thread or the resources consumed by those attempts).

Abstract: A non-volatile semiconductor memory module is disclosed comprising a memory device and memory controller operably coupled to the memory device, wherein the memory controller is operable to receive a host command, split the host command into one or more chunks comprising a first chunk comprising at least one logical block address (LBA), and check the first chunk against an active chunk coherency list comprising one or more active chunks to determine whether the first chunk is an independent chunk, and ready to be submitted for access to the memory device, or a dependent chunk, and deferred access to the memory device until an associated dependency is cleared.

Abstract: Various embodiments of the present invention allow concurrent accesses to a cache. A request to update an object stored in a cache is received. A first data structure comprising a new value for the object is created in response to receiving the request. A cache pointer is atomically modified to point to the first data structure. A second data structure comprising an old value for the cached object is maintained until a process, which holds a pointer to the old value of the cached object, at least one of one of ends and indicates that the old value is no longer needed.

Abstract: An apparatus for and method of processing a vertex in relation to 3 dimensional (3D) graphics pipeline are provided. According to the method, while a processor processes vertex data in units of batches, vertex data corresponding to a batch to be processed next is extracted and temporarily stored in a buffer independently of the processor. If the processor finishes processing of the current batch, the batch stored in the buffer is output so that the processor can immediately process the batch.

Abstract: An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.

Abstract: Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.

Abstract: Embodiments of the invention include systems and methods for reducing bus transfers for a storage device. In particular, these systems and methods reduce bus transfers by modifying an interface transfer protocol which designates the size of a multiple block read or write command is transmitted in a separate block transfer size command. Separate block transfer size commands can be omitted where the storage device maintains a record of a previously used block transfer size and reuses the size for subsequent multiple block read or write commands.

Abstract: In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the address/control signal path and outputting the write data on the data signal path.

Abstract: Reducing contentions between processes or tasks that are trying to access shared resources is described herein. According to embodiments of the invention, a method of writing a set of data associated with a task to a memory resource is provided. The method includes calculating the amount of memory required to write said data to the memory resource and updating an expected end marker to reflect the amount of memory required to write the data to the memory resource. A flag is then set to an incomplete state, and the data is written to the memory resource. The flag can be set to a complete state and an end marker is updated. The end marker indicates the end of the data stored in the memory resource.

Abstract: Dynamic file streaming divides a read/write operation into an initial number of requests of an initial size. Each of the initial number of requests is transmitted to a remote data processing system and a read/write performance value and a user interactivity value is determined based on the transmitting. A local data processing system increases the initial number of requests or the initial size by a first factor if the read/write performance value is less than a threshold. The local data processing decreases the initial number of requests or the initial size by a second factor if the user interactivity is less than a second threshold.

Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: In one embodiment, a method receives current latency values from a plurality of host computers where a current latency value is calculated by a respective host computer based on an amount of time spent in the respective host computer's issue queue by an IO request most recently removed from the issue queue of the respective host computer. The issue queue of the respective host computer is used to transmit IO requests from the respective host computer to a storage system. The method then calculates a combined average latency value based on the current latency values and sends the combined average latency value to the plurality of host computers. Each respective host computer adjusts a size of the respective host computer's issue queue based on the combined average latency value, and the size controls a number of IO requests that are added to the respective host computer's issue queue.

Abstract: A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Abstract: A system for providing model level protection for resources holding data accessed by multiple tasks in a model is discussed. The protection occurs at the model level so that the protection mechanism does not interfere with model dynamics. Resources concurrently accessed by multiple tasks are identified so that a unified protection mechanism can be applied to the resource. A user interface may be provided which enables the selection of a particular type of protection mechanism for the data in the resource. User supplied protection mechanisms may also be implemented.

Abstract: A system and method described herein allows a virtual tape library (VTL) to perform multiple simultaneous or parallel read/write or access sessions with disk drives or other storage media, particularly when subject to a sequential SCSI-compliant layer or traditional limitations of VTLs. In one embodiment, a virtualizing or transaction layer can establish multiple sessions with one or more clients to concurrently satisfy the read/write requests of those clients for physical storage resources. A table or other data structure tracks or maps the sessions associated with each client and the location of data on the physical storage devices.

Abstract: A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.

Abstract: A method for executing a processing routine that utilizes an external memory is provided. The processing routine requires more than one external memory access. The method comprises the step of distributing the external memory access after a predetermined number of external memory accesses.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.

Abstract: A software transactional memory system is provided with multiple global version counters. The system assigns an affinity to one of the global version counters for each thread that executes transactions. Each thread maintains a local copy of the global version counters for use in validating read accesses of transactions. Each thread uses a corresponding affinitized global version counter to store version numbers of write accesses of executed transactions. The system adaptively changes the affinities of threads when data conflict or global version counter conflict is detected between threads.

Abstract: A memory location determining device determines memory locations for storing M pieces of compressed data each of which is compressed from one of M pieces of N-bit data. For each piece of compressed data, the memory location determining device performs a first arithmetic operation on an address value of a corresponding piece of N-bit data, and determines to store X bits of the piece of compressed data and a flag indicating whether or not the piece of compressed data exceeds X bits at a location indicated by the result value of the first arithmetic operation. When the piece of compressed data exceeds X bits, the memory location determining device further performs a second arithmetic operation on the address value of the corresponding piece of N-bit data and determines to store one or more bits of the piece of compressed data other than the X bits.

Abstract: According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: According to the embodiment, a nonvolatile semiconductor memory that includes a plurality of banks capable of operating in parallel, a command analyzing unit that, upon receiving a power management command from a host, analyzes the received power management command, and a recording control unit that dynamically and variably controls an upper limit of the number of banks to be operated in parallel at a time of writing in accordance with an analysis result by the command analyzing unit are included, thereby suppressing the upper limit of a power consumption in accordance with an instruction from the host.

Abstract: A system (10) for virtual disks version control includes a selectively read-only volume (12); at least one topmost overlay (141, 142, 143, 144, 145); and at least two intermediate, selectively read-only overlays (16, 16?, 16?, 16??) configured as at least two mounting points. The at least one topmost overlay (141, 142, 143, 144, 145) is configured to store the results of redirected write operations. One of the at least two mounting points (16, 16?, 16?, 16??) and the volume (12) form an image, and the other of the at least two mounting points (16, 16?, 16?, 16??) and the volume (12) form another image. The at least two intermediate overlays (16, 16?, 16?, 16??) are operatively located between the volume (12) and the at least one topmost overlay (141, 142, 143, 144, 145).

Abstract: Timing parameters that influence an install time interval for installing a product on computing machines in a test environment in accordance with an installation configuration option are identified. A test value of the timing parameter and a test value of the install time are determined for each of the computing machines. The test values of the timing parameter and the install time determined for the sample computing machines are analyzed to determine an install time calculation expression for the installation configuration option. For installation in accordance with the installation configuration option in a normal operating environment, a current value of each of the timing parameters of the predetermined install time calculation expression for the installation configuration option. The install time interval in the normal operating environment is estimated based on the current value of the timing parameters and the install time calculation expression.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.

Abstract: A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Abstract: After serially receiving several MSBs of the address, a microcontroller may determine whether a write operation is occurring in the same particular partition. If it is determined that a write operation is not occurring in the same partition, then the microcontroller may immediately perform the read operation. If a write operation is occurring, however, then the microcontroller may first begin to interrupt the write operation before beginning the read operation.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks.

Abstract: System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

Abstract: According to one embodiment, a semiconductor memory device includes a command processing module, a plurality of storage units, a plurality of control modules, an adjustment circuit, and a setting register. The adjustment circuit is configured to exclude the control module connected to the storage unit of a second group from a write operation in accordance with identification data, and to cause the control module connected to the storage unit of the second group to perform a read operation in a period overlapping the write operation performed by the control module connected to the storage unit of a first group.

Abstract: In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.

Abstract: A solid-state drive, a solid-state drive access unit allocation/data storage approach, and a solid-state drive access unit access/data retrieval approach are described that improve the efficiency with which data, that has been stored to the solid-state drive in association with a series of logical block addresses, can be retrieved from the solid-state drive. The described access unit allocation approach assures that data stored in the solid-state drive in association with a sequential series of logical block addresses is stored and maintained in solid-state drive access units, i.e., addressable units of solid-state drive memory that allow parallel read access to the data via parallel memory access I/O channels internal to the solid-state drive. In this manner, the time required to retrieve data associated with a sequential series of logical block addresses from corresponding access units within the solid-state drive is reduced.

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract: A memory integrated circuit comprises first and second memory arrays and first and second interfaces. The first interface receives a signal for accessing a memory location in one of the first and the second memory arrays during a first time interval. The second interface receives a signal for accessing a memory location in one of the first and the second memory arrays during the first time interval. The first interface receives signals for accessing memory locations in the first and the second memory arrays, and the second interface is disabled from accessing the first and the second memory arrays during the second time interval. A signaling rate of a signal received by the second interface, a supply voltage of the second interface, an on-chip termination impedance of the second interface, or a voltage amplitude of a signal received by the second interface is adjusted during the second time interval.

Abstract: According to one embodiment, an error correction channel determination module determines, a channel to be allocated to a logical page as an error correction channel so that each of a plurality of channels is allocated to a uniform number of logical pages as the error correction channel. A command list generation module generates a list of write commands each specifying that a corresponding logical page is to be written using, in parallel, channels included in the plurality of channels and excluding the error correction channel, based on the determination of the channel to be allocated to the corresponding logical page as the error correction channel. A command list issue module issues the list of the write commands.

Abstract: Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits.

Abstract: Embodiments of computer processing systems and methods are provided that include a memory protection unit (MPU), and a plurality of region descriptors associated with the MPU. The region descriptors include address range and translation identifier values for a respective region of memory. Control logic determines whether a translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, the control logic allows a first process being executed by the processing system to access a memory region allocated to a second process being executed by the processing system.

Abstract: Synchronization of data layouts and resource utilizations at one or more remote replica sites with the workload and data tiering decisions being made at the primary site allows for an efficient and effective workload support transfer in the event of site failover from a primary site to a remote site. Relevant data access information about workload being supported at the primary site is collected and from that raw information, characterized data access information is generated that condenses the raw data access information or otherwise provides relevant encapsulated information about the raw data access information. The characterized data access information is transmitted to the one or more remote sites allowing each remote site to make its own independent decisions on how best to utilize its available resources to match the performance requirements currently being supported by the primary site.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.