Access Timing Patents (Class 711/167)
  • Patent number: 10996888
    Abstract: Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 4, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kuljit Singh Bains, Raj Ramanujan, Wesley Queen, Liyong Wang
  • Patent number: 10997049
    Abstract: A memory system includes a memory device including first storage elements which store data, a temperature sensor which measures a temperature of the memory device, and a controller including a processor which acquires a current temperature from the temperature sensor as a first temperature, acquires a temperature when the data is written into the first storage element, from the memory device as a second temperature, determines whether a difference between the first temperature and the second temperature exceeds a predetermined temperature difference, and when the difference exceeds the predetermined temperature difference, instructs the memory device to rewrite the data written in the first storage element. The memory device includes a sequencer which determines a voltage for the rewrite, based on the difference and a voltage when the data is written into the first storage element.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 4, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsuro Hiruta
  • Patent number: 10990325
    Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 27, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Yu-Han Hsiao, Yang-Chih Shen, Huan-Jung Yeh
  • Patent number: 10990296
    Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 27, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES. INC.
    Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
  • Patent number: 10978118
    Abstract: Disclosed is a DDR SDRAM signal calibration device capable to adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal pad configured to output a DQS signal; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and the DQS signal; and a calibration circuit configured to output a calibration signal according to the DQS enablement setting signal and at least one of the DQS enablement signal and the DQS signal so that the enablement signal setting circuit can maintain or adjust the DQS enablement setting according to the calibration signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chi Yu, Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou
  • Patent number: 10976955
    Abstract: A semiconductor device includes a first processor configured to process a first code based on a first clock signal; and a second processor, controlled by the first processor, electrically coupled to a memory, and configured to process a second code based on the first clock signal and a second clock signal, wherein the second clock signal has a faster cycle than the first clock signal.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Byoung In Joo
  • Patent number: 10949301
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by selecting a plurality of network edge units for staging public pillar encoded data slices. The method continues by identifying target content for partial download to the plurality of network edge units. The method continues by identifying public pillars corresponding to the target content for partial download. The method continues by determining a partial downloading schedule for sending public pillar encoded data slices, corresponding to the public pillars, to each network edge unit of the plurality of network edge units and facilitating partial downloading of the target content by facilitating sending of the public pillar encoded data slices to each network edge unit of the plurality of network edge units.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: March 16, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: S. Christopher Gladwin, Gary W. Grube, Timothy W. Markison
  • Patent number: 10942677
    Abstract: A method for performing access management of a memory device and associated apparatus (e.g. the memory device and controller thereof such as a memory controller within the memory device, an associated host device and an associated electronic device) are provided. The method may include: when the host device sends a host command to the memory device, utilizing the memory controller to estimate a completion time of the host command, to generate completion time information corresponding to the completion time; and utilizing the memory controller to send the completion time information to the host device, to allow the host device to perform polling after the completion time to obtain execution result of the host command.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 9, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Wen-Long Wang
  • Patent number: 10916290
    Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 9, 2021
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Farid Nemati
  • Patent number: 10909054
    Abstract: A method for status monitoring of acceleration kernels in a storage device is provided. The method includes: receiving an asynchronous event reporting (AER) command by a controller of the storage device from a host, the AER command corresponding to a first operation assigned to a first acceleration kernel on an acceleration co-processor by the host; adding the received AER command to a look-up table in the controller; receiving a completion message from the first acceleration kernel corresponding to the first operation; comparing the received completion message to the AER commands in the look-up table; and when a match is found between the received completion message and one of the AER commands in the look-up table, sending a command completion entry to the host.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Divya Subbanna, Vinit Sadanand Apte, Ramdas P. Kachare
  • Patent number: 10897738
    Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: January 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek Kyun Shin, Jun Ho Seo, Jung Hun Heo
  • Patent number: 10891241
    Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 12, 2021
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Trung A. Diep
  • Patent number: 10884639
    Abstract: Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Liyong Wang, Kuljit Singh Bains, Wesley Queen
  • Patent number: 10884667
    Abstract: This application relates to the field of storage technologies, and discloses a storage controller. The storage controller includes a distribution core, a plurality of ranking cores, and a request processing core. The three types of cores are respectively configured to: distribute IO requests to different ranking cores, generate a processing ranking index for each IO request, and process the IO request based on a value of the processing ranking index of the IO request, to flexibly schedule an IO request received by the storage controller.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Si Yu, Junhui Gong, Cong Zhao, Cheng Wang, Yue Lu
  • Patent number: 10880387
    Abstract: A first request may be received to write a first set of data to a first storage device of a first storage node. The first storage device may be capable of transferring or receiving data directly to or from a second storage device without transferring the data to or from a host device mapped to the first storage node. It may be determined that a first token clash check does not need to occur for the first request. The first token clash check may include determining whether the first request is requesting to write to one or more addresses that are associated with one or more tokens owned by one or more transactions. The one or more tokens may be a proxy for a set of data within one or more particular address ranges of the first storage device.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shrirang S. Bhagwat, Pankaj Deshpande, Subhojit Roy, Rajat Toshniwal
  • Patent number: 10861577
    Abstract: A test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. The built-in repair analysis (BIRA) circuit receives the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. The repair target memory package is selected by considering an error correction capability of an error correction code (ECC) circuit and usability of redundancy regions included in each of the plurality of memory packages.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Su Hae Woo
  • Patent number: 10860319
    Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Mark Dechene, Manjunath Shevgoor, Faruk Guvenilir, Zhongying Zhang, Jonathan Perry
  • Patent number: 10861516
    Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hun-Dae Choi, Hwapyong Kim
  • Patent number: 10831377
    Abstract: The present disclosure provides techniques for implementing an apparatus, which includes processing circuitry that performs an operation based on target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
  • Patent number: 10819615
    Abstract: A network bridging device, a bus test method and a system thereof are disclosed. The method comprises the steps of: receiving a packet signal via a first network port, wherein the packet signal is specified to be transmitted to a second network connection device; turning off a MAC learning function of a network switching module; setting a port isolation function of the network switching module to isolate a connection between the first network port and a second network port, such that the packet signal is transmitted to a processing module; controlling the processing module to enable a remote loopback function of a media access control port to cause the processing module to return the packet signal to the second network connection device so as to acquire a throughput of a bus.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 27, 2020
    Assignee: Pegatron Corporation
    Inventors: Cyuan-Cheng Wong, Shun-I You
  • Patent number: 10809945
    Abstract: One example method includes reading a data chunk from a data stream, compressing the data chunk, and calculating a chunk delta. When the chunk delta is greater than zero, the compressed data chunk is appended to an incomplete data chunk. When the chunk delta is zero or less, the boundaries of a completed and compressed data chunk having a size at least as large as a minimum size are declared.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 20, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Kedar Shrikrishna Patwardhan, Rajesh K. Nair
  • Patent number: 10803000
    Abstract: Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to detect a first phase value of a first signal. In some embodiments, the bus controller may process a second command following passage of the first time period, and wait for a second time period, based on the detected first phase value and a ratio of the first and second clock speeds.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 13, 2020
    Assignee: Synopsys, Inc.
    Inventor: Jun Zhu
  • Patent number: 10795830
    Abstract: In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: October 6, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Dexter Tamio Chun, Yanru Li
  • Patent number: 10795382
    Abstract: A computer apparatus runs a hydraulic model using real-time or near-real-time data from an Automated or Advanced Metering Infrastructure (AMI), to improve model accuracy, particularly by obtaining more accurate, higher-resolution water demand values for service nodes in the model. Improving the accuracy of water demand calculation for the service nodes in the model stems from an improved technique that more accurately determines which consumption points in the water distribution system should be associated with each service node and from the use of real-time or near-real-time consumption data. The computer apparatus uses the water demand values to improve the accuracy and resolution of its water flow and pressure estimates. In turn, the improved flow and pressure estimation provides for more accurate control, e.g., pumping or valve control, flushing control or scheduling, leak detection, step testing, etc.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 6, 2020
    Assignee: SENSUS USA, INC.
    Inventor: Michael Ehsan Shafiee
  • Patent number: 10789015
    Abstract: The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Frank F. Ross, Matthew A. Prather
  • Patent number: 10783032
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 22, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 10783281
    Abstract: A data processing system includes technology to detect a memory attack. The data processing system comprises a processing core, a memory controller, a memory bus, and memory. The memory controller comprises a memory attack detection module (MADM). The MADM comprises first and second input units and control logic in communication with the first and second input units. The control logic is configured to determine, based on first and second signals from the first and second input units, respectively, whether the memory bus is carrying a clock enable (CKE) signal of high (H), even though the memory controller is generating the CKE signal of low (L). The control logic is also configured to generate a physical memory attack detection indicator that indicates whether the memory bus is carrying the CKE signal of H, even though the memory controller is generating the CKE signal of L. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Anna Trikalinou, Daniel S. Lake, Shigeki Tomishima
  • Patent number: 10777253
    Abstract: A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Riduan Khaddam-Aljameh, Manuel Le Gallo-Bourdeau, Abu Sebastian, Evangelos Stavros Eleftheriou, Pier Andrea Francese
  • Patent number: 10777293
    Abstract: To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 15, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomonori Sasaki, Tatsuya Saito, Hideshi Maeno, Takeshi Ueki
  • Patent number: 10754769
    Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 25, 2020
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10725681
    Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 28, 2020
    Assignee: Synopsys, Inc.
    Inventors: Gyan Prakash, Nidhir Kumar, Chandrashekar Narla, Praphul Malige
  • Patent number: 10714160
    Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam
  • Patent number: 10698830
    Abstract: A data storage device includes a nonvolatile memory device; and a controller including a descriptor generation unit, a memory controller and a buffer unit. The descriptor generation unit: transmits a first read descriptor for first data, to the memory controller, queues a first cache output descriptor for the first data, and transmits the first cache output descriptor to the memory controller by referring to a state of clusters included in the buffer unit. The memory controller transmits a first read command to the nonvolatile memory device based on the first read descriptor, and transmits a first cache output command to the nonvolatile memory device based on the first cache output descriptor.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10691638
    Abstract: The subject matter of this specification can be implemented in, among other things, a method that includes receiving, from within a guest operating system, a request to create a data file in a guest file system of the guest operating system. The method further includes in response to the receipt of the request to create the data file, creating an external data file in a first storage device for a file system outside the guest file system, creating a sparse file in the guest file system, and storing metadata that directs requests to access the sparse file from within the guest operating system to the external data file in the first storage device.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: June 23, 2020
    Assignee: Parallels International GmbH
    Inventors: Maxim Lyadvinsky, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10692170
    Abstract: Embodiments described herein provide a graphics processor in which dependency tracking hardware is simplified via the use of compiler provided software scoreboard information. In one embodiment the shader compiler for shader programs is configured to encode software scoreboard information into each instruction. Dependencies can be evaluated by the shader compiler and provided as scoreboard information with each instruction. The hardware can then use the provided information when scheduling instructions. In one embodiment, a software scoreboard synchronization instruction is provided to facilitate software dependency handling within a shader program. Using software to facilitate software dependency handling and synchronization can simplify hardware design, reducing the area consumed by the hardware. In one embodiment, dependencies can be evaluated by the shader compiler instead of the GPU hardware.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Supratim Pal, Jorge E. Parra, Chandra S. Gurram, Ashwin J. Shivani, Ashutosh Garg, Brent A. Schwartz, Jorge F. Garcia Pabon, Darin M. Starkey, Shubh B. Shah, Guei-Yuan Lueh, Kaiyu Chen, Konrad Trifunovic, Buqi Cheng, Weiyu Chen
  • Patent number: 10691438
    Abstract: The subject matter of this specification can be implemented in, among other things, a method that includes receiving, from within a guest operating system hosted by a host operating system at a computer system, requests to access sparse files within a guest file system of the guest operating system. The sparse files each correspond to an external data file outside the guest file system. Each of the requests to access the sparse files within the guest file system is directed to the corresponding external data file outside the guest file system. The method includes identifying a frequency with which each of the sparse files is accessed. The method includes moving an external data file from a first type of storage device to a second type of storage device based on the frequency with which the external data file is accessed relative to others of the external data files.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: June 23, 2020
    Assignee: Parallels International GmbH
    Inventors: Maxim Lyadvinsky, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10691347
    Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
  • Patent number: 10691345
    Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark Schmisseur
  • Patent number: 10692550
    Abstract: Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. A timing delta from the comparison can be applied to calculate a correction value make adjustments that can include adjustment to a subsequent timing signal, adjustment to a reference voltage setting associated with the subsequent timing signal, other adjustments, or combinations thereof. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Gregory A. King
  • Patent number: 10672450
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Patent number: 10653315
    Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Infineon Technologies AG
    Inventor: Neil Stuart Hastie
  • Patent number: 10644865
    Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Chun Yang, Mu-Shan Lin, Wen-Hung Huang
  • Patent number: 10642612
    Abstract: A memory module includes a first memory device configured to receive data and first information from a hardware accelerator, to generate an arithmetic result by performing arithmetic processing using the data and the first information, and to output the arithmetic result through an interface with at least one other memory device; and a second memory device configured to receive the arithmetic result from the first memory device through the interface without using the hardware accelerator, and to store the arithmetic result.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jin-hyun Kim
  • Patent number: 10637533
    Abstract: An apparatus includes a controller die and a group of dies that communicate with each other via a transmission line. Less than all of the dies of the group includes a respective on-die termination resistance circuit coupled to the transmission line. In some embodiments, one of the dies that includes an on-die termination resistance circuit is an end die of the group. In particular embodiments, the end die is the only die of the group that includes an on-die termination resistance circuit coupled to the transmission line. Transmission frequencies or data rates may be increased without degrading signal quality by removing capacitance associated with on-die termination resistance circuits from at least one of the dies of the group.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Sayed Mobin, David Zhang, Gokul Kumar
  • Patent number: 10628166
    Abstract: Embodiments of the present invention include methods, systems, and computer program products for allocating and deallocating reorder queue entries for an out-of-order (OoO) processor. An example method includes dividing the reorder queue into a plurality of regions to store reorder queue entries; allocating a plurality of reorder queue entries into an instruction tag array for tracking the reorder queue entries based at least in part on an associated instruction tag; loading instruction tags into each region of the plurality of regions beginning with a first region of the plurality of regions, wherein a first plurality of instruction tags is loaded into the first region; deallocating all of the first plurality of instruction tags of the first region; and subsequent to all of the instruction tags of the first region being deallocated, loading a second plurality of instruction tags to the first region of the plurality of regions.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bryan Lloyd, Balaram Sinharoy
  • Patent number: 10623523
    Abstract: A system is presented to efficiently communication data between a sub-network and a third-party application system, such that the third-party application system is able to perform one or more functions based on data sourced from the sub-network. A process scheduler system is presented to provide multiple communication paths to populate a data store of the third-party application system.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 14, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mohini Mohana Sahoo, Ramasimha Rangaraju, Sharath Kumar Madenahatti Nanjaiah, Deepankar Narayanan, Ravi Shankar
  • Patent number: 10621117
    Abstract: The present disclosure includes apparatuses and methods related to a memory controller, such as a host memory controller. An example apparatus can include a host memory controller coupled to a first memory device and a second memory device via a channel, wherein the host memory controller is configured to send a first number of commands to the first memory device using a first device select signal, and send a second number of commands to the second memory device using a second device select signal.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James A. Hall, Jr., Robert M. Walker
  • Patent number: 10613956
    Abstract: A terminal device, a system, and a method for efficiently processing sensor data streams. The system for processing sensor data streams includes: at least one data collection unit for receiving the sensor data streams from at least one terminal device; and an allocation unit for monitoring a status of the at least one data collection unit, selecting one of the at least one data collection unit by using a monitoring result, and allocating the at least one terminal device to the selected data collection unit, wherein the at least one data collection unit receives the sensor data streams from the at least one terminal device allocated by the allocation unit.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hae-dong Yeo
  • Patent number: 10592300
    Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for to a corresponding load, by determining if said store has an actual age but said corresponding load does not have an actual age, then said store is earlier than said corresponding load; if said corresponding load has an actual age but said store does not have an actual age, then said corresponding load is earlier than said store; if neither said corresponding load or said store have an actual age, then a virtual identifier table is used to determine which is earlier; and if both said corresponding load and said store have actual ages, then the actual ages are used to determine which is earlier.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10573357
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley