Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

Abstract: As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.

Abstract: Described apparatuses and methods relate to a write request buffer for a memory system that may support a nondeterministic protocol. A host device and connected memory device may include a controller with a read queue and a write queue. A controller includes a write request buffer to buffer write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores most-recent write data associated with the unique write addresses. Incoming read requests are compared with the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to backend memory. Accordingly, the write request buffer can improve the latency and bandwidth in accessing a memory device over an interconnect.

Abstract: A method of scheduling input/output operations for a storage system including determining a deadline for a storage operation, wherein the deadline is dependent on an expected latency of the storage operation; adding the storage operation to a queue of storage operations; and reordering the queue dependent upon the deadline of the storage operation and one or more deadlines of one or more storage operations in the queue of storage operations.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: Systems and methods for providing a mobile memory module in an automatic transfer switch (ATS) allow the memory module to be easily removed from a controller of the ATS. The mobile memory module is a discrete, nonvolatile memory module that stores operational settings for the ATS and can be mounted and removed via a removable fastener. When thus mounted, the mobile memory module is connected to a signal path that allows data communication with a microprocessor on the controller. The microprocessor can retrieve operational settings from the mobile memory module as needed and store updated or new operational settings on the mobile memory module as required. In some embodiments, the mobile memory module has a protective outer housing that is hardened to withstand catastrophic transfer switch failure while still retaining all operational settings stored on the module.

Abstract: A method includes monitoring a plurality of packets received by a network sensor associated with a port of a network, determining a ratio of unicast, multicast or broadcast packets to a total number of packets for the plurality of packets, determining that the ratio is outside the bounds of a threshold range, detecting that a port is misconfigured based on the determination that the ratio is outside the bounds of a threshold range, and automatically notifying a network administrator that the port is misconfigured based on the determination that the ratio is outside the bounds of a threshold range. Further disclosed is a computer system and computer program product configured to perform the method.

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

Abstract: A storage device includes a memory controller, including: a controller configured to receive a read command from an external device, determine whether the read command is a general read command or a read-ahead command; continue an erase operation or a program operation currently in progress if the read command is a read-ahead command; and temporarily suspend an erase operation or a program operation currently in progress and process the read command if the read command is a general read command.

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: In an approach to optimize server connection timeout errors in a cloud environment, embodiments create a knowledge corpus associated with connection timeout patterns based on historical learning of transaction parameters and predicts a criticality of a transaction based on one or more identified contextual situations. Further, embodiments dynamically adjust a connection timeout range of the transaction based on the predicted criticality and one or more identified contextual situations of the transaction, and selectively identify a connection timeout range for the transaction based on an evaluation of the one or more contextual situations. Additionally, embodiments analyze generated timeout errors on a remote server from within a service mesh, and adjust timeout values of the transaction based on the analyzed generated timeouts errors. Responsive to the transaction receiving a timeout error, embodiments output a recommended timeline detailing when the transaction can be reinitiated.

Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Abstract: A requesting device includes a memory, a controller, and a communication interface. The memory is configured to store a plurality of work elements in one or more requesting queues. Each work element indicates a requestor, a responder, and an operation. The controller is configured to retrieve at least a first work element of the plurality of work elements from the memory, generate a first hint message that includes an indication of at least one operation of the first work element, and transmit the first hint message to a first responding device over the communication interface. The first responding device corresponds to a first responder of the first work element. The controller is further configured to transmit a first request relating to the at least one operation of the first work element to the first responding device over the communication interface. The first request indicates the at least one operation.

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

Abstract: Methods and apparatus for enhancing performance of a wireline communication network backhaul for a wireless node. In one embodiment, the node comprises a small-cell or other wireless base station that is backhauled by a DOCSIS system within a managed HFC network, and the methods and apparatus enable enhanced communication between the small cell/base station and the backhaul network so as to support adaptation by the wireline network for frequencies used by the node so as to mitigate interference or other issues. In one implementation, enhanced cable modem (CM), cable modem termination system (CMTS) and node devices coordinate to inform the CMTS of use of potentially interfering frequencies by the base station so that the CMTS can monitor, and reconfigure as necessary, any affected wireline RF channels.

Abstract: A display panel and a drive method therefor, where when a gate electrode drive circuit (100) scans pixels line-by-line, a drive chip (300) controls a clock signal end to input a clock control signal (CK) into the gate electrode drive circuit (100), which causes a gate electrode scan signal (G(n)) to be output by the gate electrode drive circuit (100), and a data signal (Vd) output by a data signal end is controlled to be written to a corresponding row of pixel circuits (200). Where an active level period of the clock control signal (CK) falls within an active level period of the data signal (Vd), and a start time for the active level period of the data signal (Vd) is at least 1-2 ?s earlier than a start time for the active level period of the clock control signal (CK).

Abstract: Migration of data to maintain data resiliency, including receiving user-input indicating a first data resiliency of first data; storing the first data at a first storage device of the storage devices, the first storage device associated with the first data resiliency; monitoring vectors associated with performance of the storage devices; determining, based on the monitoring, that a particular vector fails to meet an associated performance criteria for the first data resiliency of the first data, and in response: analyzing characteristics of each of the storage devices, including a resiliency of each of the storage devices; identifying, based on the characteristics of each of the storage devices, a second storage device of the storage devices for migration of the first data such that the first resiliency of the first data is maintained; and migrating the first data from the first storage device to the second storage device.

Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.

Abstract: Various embodiments described herein provide for a pre-fetch operation on a memory sub-system, which can help avoid a cache miss when the memory sub-system subsequently processes a read command from a host system.

Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.

Abstract: An information processing apparatus is described for processing a workload. The information processing apparatus comprises a processor and a memory element connected to the processor via a data link. In advance of processing a workload, the information processing apparatus estimates an access time required to transfer an amount of the workload that is to be transferred from the external memory element to the processor, and estimates a processing time for the processor to process the workload. A processing rate characteristic of the processor and/or a data transfer rate between the memory and the processor is set in dependence upon the estimated processing time and estimated access time. Methods for varying a quality of service (QoS) value of requests to the external memory element are also described.

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

Abstract: A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.

Abstract: A memory control circuit is configured to access a memory including a plurality of banks. The memory control circuit comprises: a holding unit configured to hold an access request from an external circuit; a management unit configured to manage states of the plurality of banks; a determination unit configured to determine, based on an access type of an access request held in the holding unit and the states of the plurality of banks, which access type of command issuance that is read or write is to be prioritized; and an issuance unit configured to issue a command of an access request corresponding to the access type determined to be prioritized by the determination unit, among the access requests held in the holding unit.

Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

Abstract: A method of scheduling input/output operations for a storage system including determining a deadline for a storage operation, wherein the deadline is dependent on an expected latency of the storage operation; adding the storage operation to a queue of storage operations; and reordering the queue dependent upon the deadline of the storage operation and one or more deadlines of one or more storage operations in the queue of storage operations.

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

Abstract: A vehicle master device includes a decryption key storage unit that cannot be read from an outside and that stores a decryption key for generation of a security accesses key used to perform device authentication of a rewrite target electronic control unit. The vehicle master device acquires rewrite specification data from an outside, analyzes the rewrite specification data acquired, extracts a key derivation value corresponding to the rewrite target electronic control unit from an analysis result of the rewrite specification data, and by using the decryption key corresponding to the rewrite target electronic control unit stored in the decryption key storage unit, decrypts the key derivation value extracted, and generate a security accesses key.

Abstract: Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations, set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Abstract: Embodiments provide a data processing circuit and a device. The circuit includes: a first bank group 301 and a second bank group 302, a write circuit 303 including one write input buffer circuit 3031, and a write circuit 304 including one write input buffer circuit 3041. The two write circuits 303 and 304 are configured to: receive stored data from a same write bus 306 by means of the write input buffer circuits 3031 and 3041 respectively, write the stored data into the first bank group 301 by means of a first read-write bus 307, and write the stored data into the second bank group 302 by means of a second read-write bus 308. Frequencies of control signals employed by the two write input buffer circuits 3031 and 3041 both are half of a clock frequency configured for writing the stored data by the write bus 306.

Abstract: A data relay device including: a storage circuit that stores, for each of storages, an upper limit number indicating a number of input/output (I/O) commands that are transmittable; a relay circuit that relays data transmitted and received between one or more control devices and the storages; and a control circuit that performs: counting, for each storage, a number of commands indicating a number of the I/O commands that have been transmitted via the relay circuit and for which no response has been returned from transmission destination storages among the storages; in response to a request to retry transmission of the I/O commands from one storage among the storages, registering a first number in the storage circuit as the upper limit number of commands that corresponds to the one storage, the first number being a number obtained by subtracting one from a counted value of the number of commands.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: Techniques herein train a multilayer perceptron, sparsify edges of a graph such as the perceptron, and store edges and vertices of the graph. Each edge has weight. A computer sparsifies perceptron edges. The computer performs a forward-backward pass on the perceptron to calculate a sparse Hessian matrix. Based on that Hessian, the computer performs quasi-Newton perceptron optimization. The computer repeats this until convergence. The computer stores edges in an array and vertices in another array. Each edge has weight and input and output indices. Each vertex has input and output indices. The computer inserts each edge into an input linked list based on its weight. Each link of the input linked list has the next input index of an edge. The computer inserts each edge into an output linked list based on its weight. Each link of the output linked list comprises the next output index of an edge.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.

Abstract: Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.

Abstract: The present disclosure includes apparatuses and methods related to a memory controller, such as a host memory controller. An example apparatus can include a host memory controller coupled to a first memory device and a second memory device via a channel, wherein the host memory controller is configured to send a first number of commands to the first memory device using a first device select signal, and send a second number of commands to the second memory device using a second device select signal.

Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Abstract: Described herein are techniques for automating media agent state management. For example, if a media agent is running poorly, then the media agent can be disabled and an alternate media agent can perform secondary copy job operations in place of the poorly running media agent. To determine whether a media agent is running poorly, a storage manager can determine whether the media agent has an anomalous number of failed jobs, pending jobs, and/or long running jobs and/or can determine whether the amount of resources used by the media agent is high or is increasing constantly, at a constant rate, or at a near constant rate.

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

Abstract: A semiconductor memory device includes: a memory cell array including banks; a command/address buffer receiving a command/address based on a system dock; a data input/output circuit inputting/outputting data based on a data clock; a mode control circuit generating mode selection signals indicating different latencies according to a burst length signal and operation information on a first operation mode differentiated based on a ratio of the data dock to the system clock, and a second operation mode differentiated based on a bank mode; and a latency setting circuit setting a latency according to an activated one of the mode selection signals, generating an internal write command by delaying a write command at least by the set latency according to the system dock during a write operation, and generating an internal read command by delaying a read command by the set latency according to the system dock during a read operation.

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed.

Abstract: Aspects of a storage device including a memory and a controller are provided that allow for storage of tags identifying data types and sequence numbers with data to facilitate data recovery and system integrity checks following a power failure or other system failure event. The controller is configured during a write operation to include a tag in the data identifying the data type as a host write, a recycle write, or another internal write. Following a system failure event, the controller is configured to read the tags to identify the data type in the write. Based on the tags, the controller is configured to properly rebuild or update a logical-to-physical (L2P) table of the storage device to assign correct logical addresses to the most recent data during data recovery, as well as to verify correct logical addresses during system integrity checks.

Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.