Abstract: A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.

Abstract: A memory control circuit is configured to access a memory including a plurality of banks. The memory control circuit comprises: a holding unit configured to hold an access request from an external circuit; a management unit configured to manage states of the plurality of banks; a determination unit configured to determine, based on an access type of an access request held in the holding unit and the states of the plurality of banks, which access type of command issuance that is read or write is to be prioritized; and an issuance unit configured to issue a command of an access request corresponding to the access type determined to be prioritized by the determination unit, among the access requests held in the holding unit.

Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

Abstract: A method of scheduling input/output operations for a storage system including determining a deadline for a storage operation, wherein the deadline is dependent on an expected latency of the storage operation; adding the storage operation to a queue of storage operations; and reordering the queue dependent upon the deadline of the storage operation and one or more deadlines of one or more storage operations in the queue of storage operations.

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

Abstract: A vehicle master device includes a decryption key storage unit that cannot be read from an outside and that stores a decryption key for generation of a security accesses key used to perform device authentication of a rewrite target electronic control unit. The vehicle master device acquires rewrite specification data from an outside, analyzes the rewrite specification data acquired, extracts a key derivation value corresponding to the rewrite target electronic control unit from an analysis result of the rewrite specification data, and by using the decryption key corresponding to the rewrite target electronic control unit stored in the decryption key storage unit, decrypts the key derivation value extracted, and generate a security accesses key.

Abstract: Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations, set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Abstract: Embodiments provide a data processing circuit and a device. The circuit includes: a first bank group 301 and a second bank group 302, a write circuit 303 including one write input buffer circuit 3031, and a write circuit 304 including one write input buffer circuit 3041. The two write circuits 303 and 304 are configured to: receive stored data from a same write bus 306 by means of the write input buffer circuits 3031 and 3041 respectively, write the stored data into the first bank group 301 by means of a first read-write bus 307, and write the stored data into the second bank group 302 by means of a second read-write bus 308. Frequencies of control signals employed by the two write input buffer circuits 3031 and 3041 both are half of a clock frequency configured for writing the stored data by the write bus 306.

Abstract: A data relay device including: a storage circuit that stores, for each of storages, an upper limit number indicating a number of input/output (I/O) commands that are transmittable; a relay circuit that relays data transmitted and received between one or more control devices and the storages; and a control circuit that performs: counting, for each storage, a number of commands indicating a number of the I/O commands that have been transmitted via the relay circuit and for which no response has been returned from transmission destination storages among the storages; in response to a request to retry transmission of the I/O commands from one storage among the storages, registering a first number in the storage circuit as the upper limit number of commands that corresponds to the one storage, the first number being a number obtained by subtracting one from a counted value of the number of commands.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: Techniques herein train a multilayer perceptron, sparsify edges of a graph such as the perceptron, and store edges and vertices of the graph. Each edge has weight. A computer sparsifies perceptron edges. The computer performs a forward-backward pass on the perceptron to calculate a sparse Hessian matrix. Based on that Hessian, the computer performs quasi-Newton perceptron optimization. The computer repeats this until convergence. The computer stores edges in an array and vertices in another array. Each edge has weight and input and output indices. Each vertex has input and output indices. The computer inserts each edge into an input linked list based on its weight. Each link of the input linked list has the next input index of an edge. The computer inserts each edge into an output linked list based on its weight. Each link of the output linked list comprises the next output index of an edge.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.

Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.

Abstract: Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

Abstract: The present disclosure includes apparatuses and methods related to a memory controller, such as a host memory controller. An example apparatus can include a host memory controller coupled to a first memory device and a second memory device via a channel, wherein the host memory controller is configured to send a first number of commands to the first memory device using a first device select signal, and send a second number of commands to the second memory device using a second device select signal.

Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.

Abstract: Described herein are techniques for automating media agent state management. For example, if a media agent is running poorly, then the media agent can be disabled and an alternate media agent can perform secondary copy job operations in place of the poorly running media agent. To determine whether a media agent is running poorly, a storage manager can determine whether the media agent has an anomalous number of failed jobs, pending jobs, and/or long running jobs and/or can determine whether the amount of resources used by the media agent is high or is increasing constantly, at a constant rate, or at a near constant rate.

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.

Abstract: A semiconductor memory device includes: a memory cell array including banks; a command/address buffer receiving a command/address based on a system dock; a data input/output circuit inputting/outputting data based on a data clock; a mode control circuit generating mode selection signals indicating different latencies according to a burst length signal and operation information on a first operation mode differentiated based on a ratio of the data dock to the system clock, and a second operation mode differentiated based on a bank mode; and a latency setting circuit setting a latency according to an activated one of the mode selection signals, generating an internal write command by delaying a write command at least by the set latency according to the system dock during a write operation, and generating an internal read command by delaying a read command by the set latency according to the system dock during a read operation.

Abstract: Aspects of a storage device including a memory and a controller are provided that allow for storage of tags identifying data types and sequence numbers with data to facilitate data recovery and system integrity checks following a power failure or other system failure event. The controller is configured during a write operation to include a tag in the data identifying the data type as a host write, a recycle write, or another internal write. Following a system failure event, the controller is configured to read the tags to identify the data type in the write. Based on the tags, the controller is configured to properly rebuild or update a logical-to-physical (L2P) table of the storage device to assign correct logical addresses to the most recent data during data recovery, as well as to verify correct logical addresses during system integrity checks.

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed.

Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

Abstract: A massively parallel database management system includes an index store and a payload store including a set of storage systems of different temperatures. Both the index store and the storage system each include a list of clusters. Each cluster includes a set of nodes with storage devices forming a group of segments. Nodes and clusters are connected over high speed links. Each cluster receives data and splits the data into data rows based on a predetermined size. The data rows are randomly and evenly distributed between all nodes of the cluster.

Abstract: A host system can be queried to determine whether new data has been received based on a first time interval. After completion of the first time interval, a determination can be made as to whether the new data has been received and whether a portion of the new data was not stored. In response to the portion of the new data not being stored, the host system can be queried to determine whether subsequent data has been received based on a second time interval where the second time interval is different from first time interval.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

Abstract: An embodiment of the invention may include a first electrode, a second electrode, and a multi-level nonvolatile electrochemical cell located between the first electrode and second electrode. The multi-level nonvolatile electrochemical cell may have a read path and a write path through the cell, where the read path and the write path are different.

Abstract: Embodiments of the invention include methods for handling packets in a communications network. In one embodiment, a method is implemented in an electronic device. The method includes at a first end of a queue in the electronic device, determining admission of a first packet to the first end of the queue based on a length of the first packet, where when the admission of the first packet would cause the queue to become full, the admission is further based on a packet value of the first packet and a data structure tracking packet value distribution of packets in the queue. The method further includes at a second end of the queue, dropping a second packet from the second end of the queue when the second packet's corresponding packet value is marked as to be dropped in the data structure upon admitting packets to the first end of the queue.

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

Abstract: Various implementations described herein are directed to technologies for providing error detection for a disk drive of a digital video recorder (DVR). Access data is measured according to a degree of usage of a disk drive of a DVR. The access data is stored. The stored access data is analyzed to detect performance degradation of the disk drive.

Abstract: Some embodiments provide a network forwarding integrated circuit (IC) that includes at least one packet processing pipeline. The packet processing pipeline includes multiple match-action stages, at least one of which includes a stateful processing unit that operates at a line rate of the network forwarding IC. The stateful processing unit is configured to receive data stored in a memory location associated with a stateful table of the match-action stage. The data includes a set of values. The stateful processing unit is further configured to identify one of a maximum value and a minimum value from the set of values, and to output the identified value for use by a next match-action stage.

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

Abstract: The invention introduces a non-transitory computer program product for scheduling execution of host commands when executed by a processing unit of a flash controller. Space of a random access memory of the flash controller is allocated for a first queue and a second queue, and the first queue stores the host commands issued by a host side in an order of time when the host commands arrive to the flash controller. The non-transitory computer program product includes program code to: migrate one or more host write commands from the top of the first queue to the second queue in an order of time when the host write commands arrive to the flash controller until the top of the first queue stores a host read command; fetch the host read command from the top of the first queue; execute the host read command to read user data from a flash module; and reply to the host side with the user data.

Abstract: A pixel includes a pixel circuit and an organic light emitting diode. The pixel circuit has first, second, third, and fourth transistors. The first transistor controls an amount of current flowing from a first driving power supply coupled to a first node to a second driving power supply through the organic light emitting diode. The turns on when a scan signal is supplied to a first scan line. The third transistor turns on when a scan signal is supplied to a second scan line. The fourth transistor turns on when a scan signal is supplied to a third scan line. The first transistor is a p-type Low Temperature Poly-Silicon thin film transistor and the third transistor and the fourth transistor are n-type oxide semiconductor thin film transistors.

Abstract: A memory sequencer system for external memory protocols including a control center and a microcontroller; a control center network-on-chip having nodes connected point-to-point to synchronize and co-ordinate communication; whereby a command and address sequencer to generate command, control and address commands for specific memory protocols; and at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface; wherein said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging; wherein said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer to provide firmware controllability.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage devices, for processing data requests. One of the methods include receiving, by a storage system, a processing request of data of a distributive ledger system. Types of the data of the distributive ledger system include block data, transaction data, state data, and index data. The storage system determines a type of the data among the types of the data of the distributive ledger system, and applies a type of a processing engine specified for processing the type of the data.

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.

Abstract: A state management server applies configuration information to a set of virtual computer system instances in accordance with one or more limitations specified by an administrator. In an embodiment, the limitations include a velocity parameter that limits the number of virtual computer system instances to which the configuration may be applied concurrently. In an embodiment, the limitations include an error threshold that stops the application of the configuration if the number of configuration failures meets or exceeds the error threshold. In an embodiment, the set of virtual computer systems is identified by providing a list of the individual virtual computer system instances, or by specifying one or more tags that are associated with the virtual computer systems in the set. In an embodiment, the administrator is able to specify that an association be applied according to a predetermined schedule.

Abstract: A system is configured for managing data migration from a legacy platform to a target platform is disclosed. The system determines relevant data for the data migration. The system determines frequently used relevant data, where the relevant data is determined to be frequently used when the relevant data is used more than an occurrence threshold number in a particular time period by the legacy platform. The system assigns a migration priority to the frequently used relevant data based on its frequency of occurrence. The system migrates the frequently used relevant data from the legacy platform to the target platform.

Abstract: A method for data management is provided. The method comprises: storing the plurality of items in a contiguous space within the memory, executing an instruction containing an address and a size that together identify the contiguous space to transmit the plurality of items from the main memory to a random-access memory (RAM) on a chip, and the chip includes a computing unit comprising a plurality of multipliers; and instructing the computing unit on the chip to: retrieve multiple of the plurality of items from the RAM; and perform a plurality of parallel operations using the plurality of multipliers with the multiple items to yield output data.

Abstract: In various embodiments, a device classification service makes a determination that an endpoint device in a network is eligible for expedited device classification based on a policy. The device classification service obtains, after making the determination that the endpoint device in the network is eligible for expedited device classification, telemetry data regarding the endpoint device generated by actively probing the endpoint device. The device classification service determines whether the telemetry data regarding the endpoint device matches any existing device classification rules. The device classification service generates, based on the telemetry data, a device classification rule that assigns a device type to the endpoint device, when the telemetry data does not match any existing device classification rules.

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: A distribution of response times of a storage system can be estimated for a proposed workload using a trained learning process. Collections of information about operational characteristics of multiple storage systems are obtained, in which each collection includes parameters describing the configuration of the storage system that was used to create the collection, workload characteristics describing features of the workload that the storage system processed, and storage system response times. For each collection, workload characteristics are aggregated, and the storage system response information is used to train a probabilistic mixture model. The aggregated workload information, storage system characteristics, and probabilistic mixture model parameters of the collections form training examples that are used to train the learning process.

Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.