Abstract: A distribution of response times of a storage system can be estimated for a proposed workload using a trained learning process. Collections of information about operational characteristics of multiple storage systems are obtained, in which each collection includes parameters describing the configuration of the storage system that was used to create the collection, workload characteristics describing features of the workload that the storage system processed, and storage system response times. For each collection, workload characteristics are aggregated, and the storage system response information is used to train a probabilistic mixture model. The aggregated workload information, storage system characteristics, and probabilistic mixture model parameters of the collections form training examples that are used to train the learning process.

Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

Abstract: A semiconductor device includes an arithmetic circuit executing an arithmetic operation regarding input data, and a control circuit causing the arithmetic circuit to execute an arithmetic operation regarding first data that is an arithmetic operation target of an arithmetic command when the arithmetic command is included in a supplied command sequence, and causing the arithmetic circuit to execute an arithmetic operation regarding second data different from the first data when an arithmetic command is not included in the command sequence and the command sequence is in a specific state.

Abstract: A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: An electronic device includes an operation control circuit and an input data generation circuit. The operation control circuit generates a detection signal and an internal masking signal based on a masking signal and data during a write operation. The input data generation circuit converts input data based on the internal masking signal to generate converted data. In addition, the input data generation circuit selects and outputs either the converted data or drive data as the input data, which are input to a data storage circuit, based on the detection signal.

Abstract: A data storage system can optimize deterministic window operation of a data storage system where a host is connected to a data storage device via a system module having at least two controller inputs. A data access request can be stored in a first cache by the system module prior to analyzing an operational parameter of the system and generating a cache strategy that is directed to optimizing execution of the data access request with the two controller inputs during a deterministic window between the host and data storage device. The data of the data access request can be proactively moved to a second cache in accordance with the cache strategy to optimize the deterministic window performance.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. A subset of the number of memory storage devices is selected. A subset of the plurality of pins which do not correspond to the subset of the number of memory storage devices and are not part of a memory map of the computer system is selected. Each pin of the subset of the plurality of pins configured with a termination impedance. The subset of the number of memory storage devices is tested.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

Abstract: The present invention relates to a display apparatus for transmitting content data and a control method thereof. In particular, the present invention relates to a display apparatus for transmitting data of a content of an electronic device by using an electronic pen and a method thereof. In particular, a data sharing method of the display apparatus comprises the steps of: displaying a content; when one of objects included in the content is selected by an electronic pen, identifying a size of data corresponding to the selected object; and transmitting the data through the electronic pen when the size of the data is smaller than or equal to storage capacity of the electronic pen, or transmitting identification information on the data and access information of the display apparatus through the electronic pen when the size of the data exceeds the storage capacity of the electronic pen.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.

Abstract: Systems and methods are provided that include an interamble data strobe (DQS) counter configured to count cycles between write operations. The interamble DQS counter includes a decision feedback equalizer (DFE) reset mask circuit configured to generate a DFE reset enable signal and a DFE reset timing generator configured to generate timing signals for the DFE reset. The systems and methods also include a DFE reset generator configured to receive the DFE reset enable signal and the timing signals from the interamble DQS counter, to use the DFE reset enable signal and the timing signals to generate DFE reset signals for a plurality of DQS phases; and to transmit the DFE reset signals to the plurality of DQS phases.

Abstract: A system, method, and machine-readable storage medium for providing a quality of service (QoS) recommendation to a client to modify a QoS setting are provided. In some embodiments, a set of volumes of a plurality of volumes may be determined. Each volume of the set of volumes may satisfy a first QoS setting assigned to the volume and a second QoS setting assigned to the volume. The plurality of volumes may reside in a common cluster and may be accessed by the client. Additionally, a subset of the set of volumes may be determined. Each volume of the subset may satisfy an upper bound of a range based on a minimum IOPS setting of the volume. A QoS recommendation to the client to modify the first QoS setting may be transmitted for one or more volumes of the subset.

Abstract: A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Abstract: A semiconductor memory device includes: a memory cell for storing data; a page buffer connected to the memory cell through a bit line, to store data in the memory cell or read data from the memory cell; and a cache latch connected to the page buffer through a bus node. When bit data transmission operation between the page buffer and the cache latch is performed, the bus node is discharged before starting the bit data transmission operation.

Abstract: A processing system scales power to memory and memory channels based on identifying causes of stalls of threads of a wavefront. If the cause is other than an outstanding memory request, the processing system throttles power to the memory to save power. If the stall is due to memory stalls for a subset of the memory channels servicing memory access requests for threads of a wavefront, the processing system adjusts power of the memory channels servicing memory access request for the wavefront based on the subset. By boosting power to the subset of channels, the processing system enables the wavefront to complete processing more quickly, resulting in increased processing speed. Conversely, by throttling power to the remainder of channels, the processing system saves power without affecting processing speed.

Abstract: In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. Each of the enable outputs of the switch is connected to an enable input of one of the non-volatile storage units. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.

Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.

Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: receive input of an input program in which a plurality of statements is written in a loop; generate a counting program for causing a computing machinery to execute a process of counting the number of cache misses and the number of cache hits that are expected when the loop is executed for each of pairs of the statements by rewriting the input program; and split the loop into a plurality of loops based on the number of cache misses and the number of cache hits counted in the process.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

Abstract: The disclosure describes temporal optimization of data operations using distributed search and server management, including configuring one or more host groups, determining one or more stripes associated with one or more shards distributed among the one or more host groups, receiving a query to retrieve data, evaluating the query to identify a time characteristic associated with the data, identifying a location from which to retrieve the data, and rewriting the query to run on at least one of the one or more host groups at the location using a distributed search platform, the another query being targeted at a host group associated with the class.

Abstract: The disclosed computer-implemented method for switching replication modes in a volume replication system may include (i) in response to deciding to switch from a synchronous replication mode of a volume replication system to an asynchronous replication mode, changing, by a computing device, to the asynchronous replication mode, (ii) associating a new write request to write data to storage, (iii) determining, based on metadata of the existing write request, that the existing write request was issued in the synchronous replication mode, (iv) in response to determining that the existing write request was issued in the synchronous replication mode, processing the existing write request via the synchronous replication, and (v) processing the new write request via the asynchronous replication based on the metadata of the new write request. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A hypervisor virtual server system, including a plurality of virtual servers, a plurality of virtual disks that are read from and written to by the plurality of virtual servers, a physical disk, an I/O backend coupled with the physical disk and in communication with the plurality of virtual disks, which reads from and writes to the physical disk, a tapping driver in communication with the plurality of virtual servers, which intercepts I/O requests made by any one of said plurality of virtual servers to any one of said plurality of virtual disks, and a virtual data services appliance, in communication with the tapping driver, which receives the intercepted I/O write requests from the tapping driver, and that provides data services based thereon.

Abstract: Example implementations disclosed herein can be used to build, maintain, and use a hash table distributed across the plurality multiple nodes in a multi-node computing system. The hash table can include data pages associated by corresponding pointers according to a tree data structure. The data pages include leaf data pages. Each leaf data page can be associated with a corresponding hash value and include a tag bitmap. When a transaction associated with a key is executed, a hash value and a tag value are generated based on the key. The leaf data pages can be searched using the hash value. A probability that a leaf data page includes the key can be determined based on a comparison tag value with the tag bitmap.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: Methods, apparatuses, and systems related to scheduling internal operations are described. An apparatus detects a condition associated with repeated accesses to a memory address and/or region. In response to detection of the condition, the apparatus generates a scheduling output that secures a scheduled duration of inactivity for commanded operations. The apparatus initiates execution of one or more internal operations during the scheduled duration.

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

Abstract: A memory system includes a memory device including first storage elements which store data, a temperature sensor which measures a temperature of the memory device, and a controller including a processor which acquires a current temperature from the temperature sensor as a first temperature, acquires a temperature when the data is written into the first storage element, from the memory device as a second temperature, determines whether a difference between the first temperature and the second temperature exceeds a predetermined temperature difference, and when the difference exceeds the predetermined temperature difference, instructs the memory device to rewrite the data written in the first storage element. The memory device includes a sequencer which determines a voltage for the rewrite, based on the difference and a voltage when the data is written into the first storage element.

Abstract: Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.

Abstract: A write control method, an associated data storage device and the controller thereof are provided. The write control method includes: receiving one or more commands from a host device and executing the one or more commands, and performing determining operations to generate determining results; in response to the determining results, starting performing write collection; collecting and handling one or more write commands to buffer data of the one or more write commands through a buffer memory, and performing other determining operations to generate other determining results; in response to the other determining results, according to a quantity of one or more collected and handled write commands, determining whether data thereof has filled up a write buffer region of the buffer memory; and in response to the data having filled up the write buffer region, flushing the write buffer region to write the data therein into a non-volatile memory.

Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.

Abstract: A semiconductor device includes a first processor configured to process a first code based on a first clock signal; and a second processor, controlled by the first processor, electrically coupled to a memory, and configured to process a second code based on the first clock signal and a second clock signal, wherein the second clock signal has a faster cycle than the first clock signal.

Abstract: Disclosed is a DDR SDRAM signal calibration device capable to adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal pad configured to output a DQS signal; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and the DQS signal; and a calibration circuit configured to output a calibration signal according to the DQS enablement setting signal and at least one of the DQS enablement signal and the DQS signal so that the enablement signal setting circuit can maintain or adjust the DQS enablement setting according to the calibration signal.

Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by selecting a plurality of network edge units for staging public pillar encoded data slices. The method continues by identifying target content for partial download to the plurality of network edge units. The method continues by identifying public pillars corresponding to the target content for partial download. The method continues by determining a partial downloading schedule for sending public pillar encoded data slices, corresponding to the public pillars, to each network edge unit of the plurality of network edge units and facilitating partial downloading of the target content by facilitating sending of the public pillar encoded data slices to each network edge unit of the plurality of network edge units.

Abstract: A method for performing access management of a memory device and associated apparatus (e.g. the memory device and controller thereof such as a memory controller within the memory device, an associated host device and an associated electronic device) are provided. The method may include: when the host device sends a host command to the memory device, utilizing the memory controller to estimate a completion time of the host command, to generate completion time information corresponding to the completion time; and utilizing the memory controller to send the completion time information to the host device, to allow the host device to perform polling after the completion time to obtain execution result of the host command.

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

Abstract: A method for status monitoring of acceleration kernels in a storage device is provided. The method includes: receiving an asynchronous event reporting (AER) command by a controller of the storage device from a host, the AER command corresponding to a first operation assigned to a first acceleration kernel on an acceleration co-processor by the host; adding the received AER command to a look-up table in the controller; receiving a completion message from the first acceleration kernel corresponding to the first operation; comparing the received completion message to the AER commands in the look-up table; and when a match is found between the received completion message and one of the AER commands in the look-up table, sending a command completion entry to the host.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

Abstract: This application relates to the field of storage technologies, and discloses a storage controller. The storage controller includes a distribution core, a plurality of ranking cores, and a request processing core. The three types of cores are respectively configured to: distribute IO requests to different ranking cores, generate a processing ranking index for each IO request, and process the IO request based on a value of the processing ranking index of the IO request, to flexibly schedule an IO request received by the storage controller.

Abstract: Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.

Abstract: A first request may be received to write a first set of data to a first storage device of a first storage node. The first storage device may be capable of transferring or receiving data directly to or from a second storage device without transferring the data to or from a host device mapped to the first storage node. It may be determined that a first token clash check does not need to occur for the first request. The first token clash check may include determining whether the first request is requesting to write to one or more addresses that are associated with one or more tokens owned by one or more transactions. The one or more tokens may be a proxy for a set of data within one or more particular address ranges of the first storage device.

Abstract: A test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. The built-in repair analysis (BIRA) circuit receives the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. The repair target memory package is selected by considering an error correction capability of an error correction code (ECC) circuit and usability of redundancy regions included in each of the plurality of memory packages.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.