Abstract: A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Abstract: According to one embodiment of the invention, a method is provided in which memory requests from a first component and a second component are received. The memory requests are issued by the first component and the second component to access one or more memory devices via a memory controller. The memory requests received from the first component are accumulated in a first queue and the memory requests received from the second component are accumulated in a second queue, respectively. The memory requests accumulated in the first queue are sent to the memory controller for processing as a block of memory requests. The memory requests accumulated in the second queue are sent to the memory controller for processing as a block of memory requests.

Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein.

Abstract: In accordance with one embodiment, a method re-orders requests for shared resources. The method includes receiving requests for accessing the shared resources from one or more requestors, wherein a plurality of requests may be received from each requestor; arbitrating between the plurality of requests in such a way so that the plurality of requests from each requestor may be re-ordered in non-FIFO order; and selecting a next request to access the shared resources based on the re-ordering of requests. In accordance with another embodiment, a system re-orders requests for shared resources. The system includes one or more requestors for sending requests for accessing the shared resources, wherein a plurality of requests may be received from each requestor; and an arbiter for arbitrating between the plurality of requests in such a way so that the plurality of requests from each requestor may be re-ordered in non-FIFO order.

Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

Abstract: Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a resource to a processor, while at the same time, the fast memory of such a processor is maintained in a coherent state. An exemplary structure includes data structures that help to identify the portion of the fast memory of the processor to be maintained in a coherent state. An exemplary method includes a determination of past and present processors that have had access to the resource so as to maintain the coherency of the fast memory of the processor.

Abstract: An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.

Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The tag look-ups are performed in parallel with the memory module decodes. This improves latency for cache hits without penalizing the latency for cache misses.

Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.

Abstract: In one of the many embodiments disclosed herein, a method for dispatching read and write requests to a memory is disclosed which includes queuing at least one write request in a write queue and queuing an incoming read request in a read queue. The method also includes comparing the read request with at least one write request in the write queue to detect a matching write request, and if there is a matching write request, storing a write queue index of the matching write request as a first entry in an ordering queue. The method further includes dispatching the at least one write request to the memory in response to the first ordering queue entry.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires a predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: A multi-processor system includes a system bus communicating between processors, and a bus arbiter. Responsive to a cache line invalidation command, a processor cache conditionally casts back the cache line to a transition cache. Based on the system response to the invalidation command, the transition cache either discards the cast back or writes it to main memory. The processor also converts an exclusive read command requiring a reservation to non-exclusive if the reservation has been lost before placing the command on the system bus. Furthermore, the transition cache may shift memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command involving the same real address is snooped. Responsive to a cache line request, the cache copies that cache line to the transition cache and updates cache line state. The transition cache holds the cache line pending system response.

Abstract: An operating unit operates candidate operation data Da, Db. The candidate operation data Da, Db are contained in two source memories, respectively, or alternatively in one of the two source memories. An address-generating unit generates an address signal Aa and read enable signals RE1a, RE2a in connection with the candidate operation data Da. The address-generating unit further generates an address signal Ab and read enable signals RE1b, RE2b in connection with the candidate operation data Db. Thus, data output from the source memory is controlled with each data to be operated, not with each of the source memory. As a result, data transfer-caused loads can be suppressed. This feature provides a processor having enhanced performance, and further reduces electric power that the processor consumes.

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.

Abstract: A pipeline array includes a register, a pipeline clock input, and Narrow Pulse Triggered Latches (NPTL) stages connected in series. Each NPTL stage includes a Latch Pulse Generator (LPG) and a parallel set of single latches clocked by the LPG. The latches provide the parallel data input and the parallel data output of the stage. Each LPG provides a narrow latch clock pulse in response to a Pipeline Clock Pulse (PCP) supplied to the register and the last stage of latches. Each PCP arrives at each preceding LPG in the array after a delay provided by intervening time delay units. The delays increase for each preceding stage with the least delay at the penultimate stage and with the greatest delay at the first stage. The data input of the first stage is connected to the output of the register. The data input of the each of other stage is connected to the data output of the preceding stage in the array.

Abstract: A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.

Abstract: The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. An earlier indication can be provided that at least two memory accesses may be required to access a data item by performing a prediction based upon one or more operands generated from a memory instruction instead of waiting for a memory access generation stage to generate the memory access. Prediction logic can generate a prediction signal to prevent the memory access generation stage from receiving signals from a preceding pipeline stage while at least two memory accesses are being generated.

Abstract: In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

Abstract: A method for aging queued commands in a data storage device, wherein a next command is selected from the queued commands based on a combination of an expected access time (EAT) and an incentive term. The incentive term provides for selection of older ones of the queued commands that have larger EATs, instead of younger ones of the queued commands that have smaller EATs. Preferably, the value of the incentive term begins at zero, remains at zero for some number of queue sorts (which are performed before a command is selected for execution), and then increases continuously for some number of queue sorts or indefinitely. Both the incentive term's starting value and the rate at which it increases ate user-selectable parameters, and thus can be used to control service time and throughput in the disk drive's queue.

Abstract: A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.

Abstract: A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.

Abstract: A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register.

Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.

Abstract: A processing system includes a cache controller for managing requests for data from a cache memory by a processor. The cache controller includes an access queue that holds requests for data pending asynchronous retrieval of the requested data from the cache memory, and an exit queue that holds the requested data retrieved from the cache memory until released to the processor. This queuing arrangement allows data lines to be retrieved from cache memory without a pipeline, while latencies are minimized.

Abstract: A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: A processor core for realizing efficient operation processing by connecting an extended arithmetic unit to its exterior and a processor incorporating such a processing core are provided. The processor includes the processor core, a data memory accessed by the processor core, and the extended arithmetic unit connected to the exterior of the processor core for processing a particular instruction. The extended arithmetic unit executes an arithmetic operation by using arithmetic operation data retained in a register file in the processor core, and directly outputs an arithmetic operation result to the processor core. Then, the processor core saves the result of the arithmetic operation executed by the extended arithmetic unit and inputted therefrom in the register file in the processor core.

Abstract: A pipeline memory device including a data fetching control circuit and utilizes a data fetching method. The pipeline memory device includes a first, second, and third pipeline stages. A second pipeline control signal, for operating the second pipeline stage, is generated from a first pipeline control signal. The data fetching control circuit includes the following: A first edge trigger delay circuit that receives the clock signal for generating the first pipeline control signal and generates the first pipeline control signal. A second edge trigger delay circuit that receives the clock signal for generating the first pipeline control signal. A first inverter that inverts the first pipeline control signal. A NAND gate that inputs the outputs of the first inverter and the second edge trigger delay circuit. A second inverter that inverts the output of the NAND gate to output the second pipeline control signal.

Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Abstract: A unique system and method for ordering commands to reduce disc access latency while giving preference to pending commands. The method and system involves giving preference to pending commands in a set of priority queues. The method and system involve identifying a pending command and processing other non-pending commands in route to the pending command if performance will not be penalized in doing so. The method and system include a list of command node references referring to a list of sorted command nodes that are to be scheduled for processing.

Abstract: An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same doubleword detection unit receives a first instruction including a plurality of first instruction fields on a first pipe and a second instruction including a plurality of second instruction fields on a second pipe. The same doubleword detection unit generates a same doubleword signal in response to the first instruction fields and the second instruction fields. The cache storage reads data from a single doubleword in the cache storage and simultaneously provides the doubleword to the first pipe and the second pipe in response to the same doubleword signal.

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract: An input/output data pipeline circuit of a semiconductor memory device includes a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.

Abstract: A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers. In a read operation, the data read from the first data address is transferred to a first page register.

Abstract: A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.

Abstract: In a computer processor, a low-order portion of a virtual address for a pipelined operation is compared directly with the corresponding low-order portions of addresses of operations below it in the pipeline to detect an address conflict, without first translating the address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and a translation lookaside buffer (TLB) for determining the high-order portion of a real address. The comparison of low-order address portions provides conflict detection before the TLB can translate a real address of an instruction.

Abstract: In a method for adaptive arbitration of requests for accessing a memory unit in a multi-stage pipeline engine that includes a plurality of request queues corresponding to the stages of the pipeline engine, each of the request queues is assigned to one of a high-priority group and a low-priority group in accordance with an operating state of the memory unit. The request queues in the high-priority group are then processed prior to the request queues in the low-priority group.

Abstract: A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Abstract: An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. In one embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor.

Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.

Abstract: A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.

Abstract: A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue hat holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line. A control logic is added to remove stale cache lines. When a cache line fill is being processed, the control logic determines if the cache line exists in any other cache segments.

Abstract: This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

Abstract: A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.

Abstract: A method and system are employed within a processor for performing page table walks on speculative software prefetch operations. The system includes a first fault register to store information associated with a faulting micro-op relating to a non-prefetch memory access operation and a second fault register to store information associated with a faulting micro-op relating to a prefetch memory access operation. Also included in the system is a first unit to determine whether a currently pending micro-op relates to a non-prefetch operation or a prefetch operation. The first unit is configured to drop the currently pending micro-op from a pipeline if (1) the currently pending micro-op relates to a prefetch memory access and (2) the currently pending micro-op has previously faulted.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.