Abstract: A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.

Abstract: The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer comprises a larger storage capacity than the first data buffer. During a write operation, data is stored in the second data buffer and then stored in the memory array. During a read operation, data is read from the memory array and then stored in the first data buffer but not in the second data buffer. Because the smaller-storage-capacity buffer takes less time to fill than the larger-storage-capacity buffer, there is less of a delay in outputting data from the memory device as compared to memory devices that use a larger-storage-capacity buffer for both read and write operations. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract: The present invention provides a central processing unit-containing large-scale integration (hereinafter, referred to as a “CPU-containing LSI”) in which software stored in an external memory is incorporated partially into a random access memory (hereinafter, referred to as “RAM”) and thereby the capacity of the RAM to be used can be held down, and an optical disk device including the same. In the CPU-containing LSI, the RAM includes a software storage region where software read in from the external memory on a module-by-module basis is stored, and an entry table in which entries are stored, with the entries each containing at least information as to a location and a size of a module stored in the software storage region. The CPU refers to the entry table to decide the location where a module to be read in from the external memory to the software storage region is to be stored, according to an incorporation-location search program.

Abstract: A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.

Abstract: Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.

Abstract: A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.

Abstract: A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.

Abstract: A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

Abstract: The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.

Abstract: A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract: A general-purpose serial operation pipeline realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. A plurality of arithmetic-logic circuits (SALCs) that are controlled individually, and that can be operated together with another arithmetic-logic circuit (SALC) are connected in a cascade manner to form a serial operation pipeline. At least one of the plural SALCs includes a line for outputting data from an upstream SALC to a downstream SALC, a line for feeding back reverse data from the downstream SALC to the upstream SALC, and latch circuits for latching the data on the respective lines, thereby being capable of feeding back data from an arbitrary SALC to another SALC.

Abstract: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.

Abstract: A computing system is provided with enhanced data reliability by implementing mirroring and snapshot functionality of the system memory. In the computing system, a processor executes its programs from a first region of a physical memory. Using instructions from the system itself, or from an external console, the first region of the physical memory is periodically mirrored to a second region of the physical memory not used by the processor. This second region can be volatile or nonvolatile memory. The computing system also includes snapshot functionality by which images of the second region of the physical memory are taken at periodic intervals and stored to enable returning the system to a previous state when desired, or in the event of failure.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: A computer program product determines whether a loop has a high usage count. If the computer program product determines the loop has a high usage count, the computer program product determines whether the loop has an irregularly accessed load. If the loop has an irregularly accessed load, the computer program product inserts pattern recognition code to calculate whether successive iterations of the irregular memory load in the loop have a predictable access pattern. The computer program product implants conditional adaptive prefetch code including a prefetch instruction into the output code.

Abstract: A method and apparatus for processing data packets including generating an enqueue command specifying a queue descriptor associated with a new buffer. The queue descriptor is part of a cache of queue descriptors each having a head pointer pointing to a first buffer in a queue of buffers, and a tail pointer pointing to a last buffer in the queue. The first buffer having a buffer pointer pointing to next buffer in the queue. The buffer pointer associated with the last buffer and the tail pointer is set to point to the new buffer.

Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requesters in the order in which the read requests were originally received.

Abstract: A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.

Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.

Abstract: An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss. The data cache has pipeline stages that parallel portions of the main microprocessor pipeline. Replay buffers are employed to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache pipeline stages are restored upon detection that the stall will terminate. The bus requests for the missing data are issued only if the stalled instruction does not access a memory-mapped I/O region of the memory address space.

Abstract: In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write first and second primary data sections to the first and second memory assemblies, respectively, and write first and second redundant data sections to the second and first memory assemblies, respectively, wherein the first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Abstract: A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.

Abstract: In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required ¼ clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.

Abstract: A processor-based device (e.g., a wireless device) may include a processor and a semiconductor memory (e.g., a flash memory) to selectively pipeline and prefetch memory data, such as executable data, in one embodiment, using prefetch/pipeline logic that may enable storage of a first indication associated with executable data at a first storage location and a second indication associated with executable data at a second storage location. Upon retrieval, the prefetch/pipeline logic may selectively perform at least one of pipelining and prefetching of the executable data associated with the second storage location based on the first indication.

Abstract: A method and apparatus for storing and reading an entry having one of a plurality of entry types and storing order information about stored entries, using a single addressable storage array. An index pipe maintains first in, first out order of the entries stored in the addressable storage array. Stages in the index pipe store a value representing the address of the stored entry in the storage array, the type of the stored entry, and the validity of the stored entry. Additional control logic implements order rules between entry types.

Abstract: A memory controlling apparatus which receives from an upper module of a system a command to read data from a memory module or write data in the memory module and controls accessing the memory module in response to the command. The memory controlling apparatus includes a first transmitter which transmits an address of read data or write data and the write data to a memory module via an address line; and a second transmitter which transmits data read from a memory module to the upper module of the system via a data line.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence of 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

Abstract: A method and apparatus for efficient access to multiple lines of image data using a memory device with at least one memory module, wherein each memory module has at least one bank with multiple rows. The method includes the step of maintaining address information of a current row for each bank within each memory module. Next, the method receives a request for an incoming row. Finally, the method determines if the incoming row matches the current row based on the address information and if so, immediately accesses the current row without closing and reopening the current row.

Abstract: A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

Abstract: Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

Abstract: A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists between a first read request to the first bank and a second read request to the first bank, a first write request is executed to the second bank during a delay. The delay takes place after the first read request is executed and before the second read request is executed.

Abstract: A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.

Abstract: A system and method for analyzing data accesses to determine data accessing patterns is provided. Data address accesses are traced and transformed into Whole Program Data Accesses (WPDAs). WPDAs may then be used to discover higher-level data abstractions, such as hot data blocks. Hot data blocks provide information related to sequences of data addresses that are repeatedly accessed together. Hot data blocks may then be used to improve program performance.

Abstract: A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the memory subsystem in conformity with measured metrics to reduce the average latency of the memory subsystem. Counters provided within the memory controller track the number of consecutive row accesses and optionally the number of total accesses over a measurement interval. The number of counted consecutive row accesses can be used to control the closing of rows for subsequent accesses, reducing memory latency. The count may be validated using a second counter or storage for improved accuracy and alternatively the row close count may be set via program or logic control in conformity with a count of consecutive row hits in ratio with a total access count.

Abstract: Multiple read requests are prioritized. A first one of the prioritized read requests is issued to a memory device. Bits from the memory device are received for the first read request. After issuing the first read request, a second one of the prioritized read requests is issued to the memory device prior to or while receiving bits from the memory device for the first read request.

Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Abstract: A method and apparatus for a multi-channel high speed framer is described. In one embodiment, the invention is an apparatus. The apparatus includes a first plurality of pipeline stages suitable for data framing between a link layer and a network interface. The apparatus also includes a first memory coupled to each pipeline stage of the first plurality of pipeline stages, the first memory to store context information at predetermined stage locations for each pipeline stage. The apparatus further includes a first control logic coupled to the first memory and to each pipeline stage of the first plurality of pipeline stages, the first control logic to control transfer of data between the first memory and the first plurality of pipeline stages. Within the apparatus, each stage of the first plurality of pipeline stages is suitable for loading the context information from the first memory through first control logic and performing a sub-function of data framing.

Abstract: Methods, system and computer program product are provided to improve the efficiency of data transfers in a PPRC environment. A block of data to be transferred is divided into tracks. Each track is allocated to a data mover task control block (TCB) with a master TCB being assigned to supervise the data mover TCBs. The tracks are then transferred from the primary storage controller to the secondary controller in a piped fashion over a link coupling the primary and secondary storage controllers. However, the usage of resources is monitored by a resource management algorithm and, if too many TCBs are being used for a transfer or if the supply of data mover TCBs is exhausted, the transfer is automatically switched to a serial, non-piped transfer with the master TCB serving as the data mover TCB for the remaining tracks. In addition, the various links coupling the primary and secondary storage controllers is monitored to determine which link will provide the fastest transfer.

Abstract: Unified exception handling may be provided by processing a data packet through at least two pipelined processing stages in a data packet processor such as a switch, router, bridge, or similar network device, each of the data packets having associated with it (while it is being processed) an exception map disposed in a memory of the network device. The bits in the exception map are set, modified, or reset in response to exception conditions detected at the various processing stages. After the packet has been fully processed, an exception handler takes as an input the exception map and further processes the packet in response to the state of the exception map.

Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. It is a further goal of the present invention to satisfy load operations faster than prior art techniques in most cases. Finally, it is a goal of the present invention to provide an improved technique for satisfying load operations that does not significantly impact processor performance in the event that a present load is not satisfied within a predetermined amount of time.

Abstract: A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Abstract: A method for reducing the number of interface lines and non-volatile memory devices in a computer system includes providing a non-volatile memory having a SDRAM style interface. A system having both non-volatile memory and SDRAM has reduced interface lines by providing only one memory interface. A system where the SDRAM interface logic is initialized by code stored in the non-volatile memory having a SDRAM style interface, eliminating any requirement for other non-volatile memory, independent of the SDRAM interface, from which to initialize the system.

Abstract: A buffer is provided with a CBW area (a randomly accessible command storage area) and an EP1 area (data storage area set to FIFO), when a CBW and data are allocated as informations to be transferred through one end point EP1. When a phase switches from a USB command phase (command transport) to a data phase (data transport), the information write area is switched from the CBW area to the EP1 area and OUT data transferred from the host to the end point EP1 is written into the EP1 area. The area switches from the CBW area to the EP1 area on condition that an acknowledgment has returned to the host in the command phase. In case of a toggle missing, area switching does not occur even if ACK is returned.