Memory Partitioning Patents (Class 711/173)
  • Patent number: 11119813
    Abstract: Systems and methods are described for providing an implementation of the MapReduce programming model utilizing tasks executing on an on-demand code execution system or other distributed code execution environment. A coordinator task may be used to obtain a request to process a set of data according to the implementation of the MapReduce programming model, to initiate executions of a map task to analyze that set of data, and to initiate executions of a reduce task to reduce outputs of the map task executions to a single results file. The coordinator task may be event-driven, such that it executes in response to completion of executions of the map task or reduce tasks, and can be halted or paused during those executions. Thus, the MapReduce programming model may be implemented without the use of a dedicated framework or infrastructure to manage map and reduce functions.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 14, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Sunil Mallya Kasaragod
  • Patent number: 11099874
    Abstract: Technology for configuring and executing a shallow virtual machine to enhance memory protection between different portions of user space memory of a particular computing process. An example method may involve: associating a computing process with a virtual machine data structure, wherein the computing process initiates an update to the virtual machine data structure to cause a processor to switch between a page table structures; loading first and second executable code into user space memory of the computing process, wherein a first page table structure comprises mapping data for the first and second executable code and wherein the second executable code comprises driver code of a device; updating the second page table structure to disable execution of the first executable code and to map a portion of the user space memory to the device; and restricting the first executable code from accessing the memory mapped device.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 24, 2021
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Amnon Ilan
  • Patent number: 11100009
    Abstract: An application monitoring system for identifying and removing unused components from memory associated with an application. Embodiments identify a range, a set of historical logs associated with the range, and components in each historical log. Each component is classified based on a frequency of use of the component, the most recent time the component was used, the number of periods between the most recent use of the component and the range end point, and the number of periods between the most recent use of the component and the previous use of the component. Unused and rarely used components are isolated or removed from the memory.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 24, 2021
    Assignee: Bank of America Corporation
    Inventors: Rajalakshmi Arumugam, Sesharamanujam Padmanabhan, Kiran Subramanyam Darbha
  • Patent number: 11093327
    Abstract: A method includes detecting, by a vault management device, a failed storage unit common to a first vault and a second vault. The first vault is associated with a first set of storage units and the second vault is associated with a second set of storage units. The failed storage unit is in each of the first and second sets of storage units. The method further includes identifying a number of non-failed storage units of the first and second sets of storage units and comparing the number of non-failed storage units with first and second decode threshold numbers to determine a failure impact level. The first decode threshold number is associated with the first vault and the second decode threshold number is associated with the second vault. The method further includes determining a failure abatement approach based on the failure impact level and facilitating the failure abatement approach.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 17, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: Asimuddin Kazi, Jason K. Resch
  • Patent number: 11080130
    Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae In Lee, Yong Mi Kim
  • Patent number: 11074179
    Abstract: A method for managing objects stored in memory is presented. The method may include receiving, by a memory allocator in a garbage collected system, a first free memory chunk. The method may include creating a node to associate with the first free memory chunk and ensuring that a first memory region containing the node will be considered to be free memory during a sweeping phase of the garbage collected system.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 27, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Lokesh Gidra, Evan R Kirshenbaum
  • Patent number: 11074668
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient stripes is distributed across the plurality of storage devices such that each of the plurality of failure resilient stripes spans a plurality of the storage devices. A graphics processing unit is operable to access data files from the failure resilient stripes, while bypassing a kernel page cache. Furthermore, these data files may be accessed in parallel by the graphics processing unit.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: July 27, 2021
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel
  • Patent number: 11068392
    Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Liam Michael Parker
  • Patent number: 11042477
    Abstract: The present disclosure is directed to a memory management method and to a memory management device arranged to execute memory allocation and/or memory deallocation by use of segregated free lists, which provide information on memory chunks, wherein the memory allocation and/or the memory deallocation are executed according to states of the memory chunks, and wherein the states of the memory chunks comprise: an used state indicating that a memory chunk, which is in used state, is in use, and is not available for allocation; a linked state indicating that a memory chunk, which is in linked state, is not used, is linked within a free list of the segregated free lists, and is available for allocation; a free state indicating that a memory chunk, which is in free state, is not used, is not linked within any of the segregated free lists, and is not available for allocation.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 22, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Aleksandr Aleksandrovich Simak, Peter Sergeevich Krinov, Xuecang Zhang
  • Patent number: 11032130
    Abstract: Embodiments of the present disclosure describe a troubleshooting method, apparatus, and system, and pertain to the field of troubleshooting. An embodiment of the method may include monitoring, by a virtualized network function (VNF), an operating status of at least one virtual machine (VM) inside the VNF. The method may also include determining, by the VNF according to a fault when the fault occurs on the VM, whether to perform VM rebuilding recovery. Furthermore the method may include sending, by the VNF, a rebuilding recovery request to a virtualized network function manager (VNFM) when determining to perform the VM rebuilding recovery. In this way, when the fault occurs on the VM, the VIM performs automatic rebuilding recovery for the VM by interactions between the VNFM and the VIM.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 8, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Shoudong Yuan
  • Patent number: 11016882
    Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 25, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Liam Michael Parker
  • Patent number: 11010053
    Abstract: The present application is directed to a memory-access-multiplexing memory controller that can multiplex memory accesses from multiple hardware threads, cores, and processors according to externally specified policies or parameters, including policies or parameters set by management layers within a virtualized computer system. A memory-access-multiplexing memory controller provides, at the physical-hardware level, a basis for ensuring rational and policy-driven sharing of the memory-access resource among multiple hardware threads, cores, and/or processors.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 18, 2021
    Assignee: VMware, Inc.
    Inventor: Bhavesh Mehta
  • Patent number: 11005934
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for migrating data from a first storage system to a second storage system. That data is for a process (e.g., a virtual machine, application, or some other process) operating on a computer system that is separate from the first storage system and the second storage system. That data is stored according to data subsets that are each exclusive of each other. As each data set is migrated, access to the data set by the process is precluded, but access for the remaining data sets is not affected. Once the data migration is complete, access to the data set by the process is restored.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: May 11, 2021
    Assignee: Google LLC
    Inventor: Tyler Sanderson
  • Patent number: 10997151
    Abstract: Systems, methods, and devices for generating a transactional change tracking summary for a database. A method includes executing a transaction on a table of a database, wherein the table includes a micro-partition and the transaction is executed on the micro-partition. The method includes, in response to the transaction being fully executed, generating a change tracking entry comprising an indication of one or modifications made to the table by the transaction. The method includes storing the change tracking entry in a change tracking stream, wherein the change tracking stream includes one or more sequential change tracking entries that each correspond to a different transaction that is fully executed on the table.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 4, 2021
    Assignee: Snowflake Inc.
    Inventors: Subramanian Muralidhar, Istvan Cseri, Torsten Grabs, Benoit Dageville
  • Patent number: 10996977
    Abstract: An information processing apparatus includes a processor, a memory, and a storage device. The processor includes a plurality of sub-processors. The memory stores data of part of pages included in an address space allocated to processes executable in parallel using the plurality of sub-processors. The storage device retreats data of pages that are not stored in the memory. The processor acquires a working set size for each of the processes. The working set size indicates an amount of pages used for a unit time. The processor selects part of the processes when a sum of working set sizes of the processes exceeds a predetermined threshold value. The processor stops the selected processes for a predetermined time. The processor controls data of pages corresponding to the processes being stopped to be retreated from the memory to the storage device.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 4, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Ninomiya
  • Patent number: 10990539
    Abstract: A memory system includes a memory device and a controller. The memory device includes first and second memory groups. The controller includes a resource controller and first and second flash translation layer (FTL) cores. Each of the first and second FTL cores manages a plurality of logical addresses (LAs) that are mapped, respectively, to a plurality of physical addresses (PAs) of a corresponding memory group. The resource controller determines LA use rates of the first and second FTL cores, selects a source FTL core and a target FTL core from the first and second FTL cores using the LA use rates, and balances the LA use rates of the source FTL core and the target FTL core by moving data stored in storage spaces associated with a portion of the LAs from the source FTL core to storage spaces associated with the target FTL core.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 10983919
    Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 20, 2021
    Assignee: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M Van Dyke, Kun Fang
  • Patent number: 10977277
    Abstract: Systems and methods are provided to enable control and placement of data repositories. In some embodiments, the system segments data into zones. A website, for example, may need to segment data according to location. In this example, a zone may be created for North America and another zone may be created for Europe. Data related to operations executed in North America, for example, can be placed in the North America zone and data related to transactions in Europe can be placed in the Europe zone. According to some embodiments, the system may use zones to accommodate a range of deployment scenarios.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 13, 2021
    Assignee: MongoDB, Inc.
    Inventors: Dwight Merriman, Eliot Horowitz, Cory P. Mintz, Cailin Anne Nelson, Akshay Kumar, David Lenox Storch, Charles William Swanson, Keith Bostic, Michael Cahill, Dan Pasette, Mathias Benjamin Stearn, Geert Bosch
  • Patent number: 10977245
    Abstract: The subject technology obtains, at a database system, an ingest request to ingest one or more files into a table of a database. The subject technology, after obtaining the ingest request and prior to the ingesting of the one or more files, persists the one or more files in a file queue that corresponds to the table. The subject technology assigns the one or more files to one or more execution nodes to be ingested into the table. The subject technology operates an ingest puller to poll the file queue. The subject technology ingests, by the one or more execution nodes, the one or more files into one or more micro-partitions of the table via one or more pipes.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: April 13, 2021
    Assignee: Snowflake Inc.
    Inventors: Benoit Dageville, Varun Ganesh, Jiansheng Huang, Jiaxing Liang, Haowei Yu, Scott Ziegler
  • Patent number: 10956617
    Abstract: Systems and methods for random fill caching and prefetching for secure cache memories are provided. The system dynamically de-correlates fetching a cache line to the processor from filling the cache with this cache line, due to a demand memory access, in order to provide greater security from information leakage due to cache side-channel attacks on cache memories. The system includes a random fill engine which includes a random number generator and an adjustable random fill window. Also provided is an adaptive random fill caching system which dynamically adapts the random fill window to a wide variety of computational workloads. Systems and methods for cache prefetching to improve system performance using adaptive random fill prefetching and random fill prefetching are also provided.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 23, 2021
    Assignee: CoreSecure Technologies, LLC
    Inventors: Ruby B. Lee, Fangfei Liu
  • Patent number: 10936232
    Abstract: This application relates to apparatus and methods for automatically determining and providing digital advertisements to targeted users. In some examples, a computing device receives campaign data identifying items to advertise on a website, and generates campaign user data identifying a user that has engaged all of the items on the website. The computing device may then determine a portion of the users based on a relationship between each user and the campaign user data, and may determine user-item values for each of the items for each user of the portion of users, where each user-item value identifies a relational value between the corresponding user and item. The computing device may then identify one or more of the items to advertise to each user of the portion of users based on the user-item values, and may transmit to a web server an indication of the items to advertise for each user.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Walmart Apollo, LLC
    Inventors: Ashish Surana, Navinderpal Pal Singh Brar, Deepak Goyal, Giridhar Addepalli, Sébastien Péhu
  • Patent number: 10929388
    Abstract: A system for performing a computation includes an interface and a processor. The interface is configured to receive an indication of the computation. The processor is configured to determine whether the computation is with respect to a computation version number. In response to a determination that the computation is with respect to a computation version number: 1) determine whether the system has been updated to at least the computation version number; and 2) in response to a determination that the system has been updated to at least the computation version number: a) determine a set of data values for the computation associated with the computation version number; b) perform a partition reduce operation on the set of data values to determine a partition result; and c) provide the partition result.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 23, 2021
    Assignee: Workday, Inc.
    Inventors: Jason Howes, Noah Arliss
  • Patent number: 10915347
    Abstract: Systems and methods for migrating and/or replicating computer systems are disclosed. Computer systems may be migrated and/or replicated from physical systems or virtual systems to physical or virtual systems. Migrating/replicating computer systems comprises determining the structure of the source computer system, generating instructions for migrating/replicating the structure of the computer system, and packaging the instructions in an executable package. The instructions may be formatted as a template, such as an OVF template, and be packaged with an executable agent and task list. The executable agent may be received and executed by a destination computer system. Executing the executable package may cause the instructions to be executed, as well as the optional agent, there configuring the destination computer system, possibly copying data present on the source computer system, and possibly rebooting the destination computer system.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 9, 2021
    Assignee: ACRONIS INTERNATIONAL GMBH
    Inventors: Yuri Per, Serguei M. Beloussov, Vladimir Miroshkin, Stanislav Protasov, Maxim V. Lyadvinsky
  • Patent number: 10908832
    Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Sebastien Andre Jean, Jianmin Huang
  • Patent number: 10896172
    Abstract: Systems, methods, and devices for batch ingestion of data into a table of a database. A method includes determining a notification indicating a presence of a user file received from a client account to be ingested into a database. The method includes identifying data in the user file and identifying a target table of the database to receive the data in the user file. The method includes generating an ingest task indicating the data and the target table. The method includes assigning the ingest task to an execution node of an execution platform, wherein the execution platform comprises a plurality of execution nodes operating independent of a plurality of shared storage devices collectively storing database data. The method includes registering metadata concerning the target table in a metadata store after the data has been fully committed to the target table by the execution node.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 19, 2021
    Assignee: Snowflake Inc.
    Inventors: Benoit Dageville, Varun Ganesh, Jiansheng Huang, Jiaxing Liang, Haowei Yu, Scott Ziegler
  • Patent number: 10891163
    Abstract: A method, computer program product, and computer system for physical memory allocation of a computer system, the method including collecting computer system architecture specifications, a configuration, and user requirements, identifying a plurality of memory intervals to be allocated, based on the computer system architecture specification, the configuration, and the user requirements, grouping memory intervals into a plurality of color groups, wherein each memory interval within each of the plurality of color groups comprise identical memory attributes, dividing memory into sets of memory segments, wherein each set of memory segment is assigned a color of the plurality of color groups, allocating a memory interval of the plurality of memory intervals within the set of memory segments of corresponding color, and selecting a page size for a translation of a memory interval of the plurality of memory intervals, depending upon the allocation of the memory interval and the sets of memory segments.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shai Doron, Wesam Saleem Ibraheem, Hernan Theiler, Vitali Sokhin, Hagai Hadad
  • Patent number: 10884873
    Abstract: A method and an apparatus for recovery of a file system using metadata and data clusters. The apparatus for recovery of a file system generates an MFT entry list in a disc or an evidence image, collects at least one data cluster candidate, and uses at least one MFT entry and at least one data cluster candidate within the MFT entry list to generate at least one MFT entry-data cluster pair candidate. The apparatus for recovery of a file system analyzes the at least one MFT entry-data cluster pair candidate to determine attribute values of a virtual partition and generate the virtual partition based on the attribute values.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 5, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyunuk Hwang, Kibom Kim, Seungyong Lee, Seongtaek Chee
  • Patent number: 10846173
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10841235
    Abstract: Methods and apparatus to optimize memory allocation in response to a storage rebalancing event are disclosed. An example apparatus includes a telematics agent to detect a rebalancing event based on metadata; and a decision engine to identify a cluster corresponding to the rebalancing event by processing the metadata; and increase a number of jumbo buffers in a network switch corresponding to the cluster in response to the rebalancing event.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 17, 2020
    Assignee: VMWARE, INC
    Inventors: Raja Kommula, Raj Yavatkar, Priyanka Tembey
  • Patent number: 10831726
    Abstract: A computer-implemented method of importing data from a data source to a target storage system is disclosed. The method involves executing an automated data import process to retrieve data from the data source and update the target storage system based on the retrieved data. The automated data import process operates in dependence on a source data schema of the data source. The method involves detecting a change in the source data schema, and, in response to detecting the change in the source data schema, modifying the automated data import process. The modified automated data import process can subsequently be used to retrieve further data from the data source and update the target storage system based on the further retrieved data.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 10, 2020
    Assignee: GB GAS HOLDINGS LIMITED
    Inventor: Christopher Soza
  • Patent number: 10824353
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • Patent number: 10795581
    Abstract: A GPT hidden partition locking key system includes a server device coupled to the key management system through a network. The server device includes a storage system having a GPT identifying data storage partitions included on a storage system and a hidden partition included on the storage system. A remote access controller device in the server device retrieves a partition locking key from the key management system and provides it for storage in the hidden partition. A BIOS in the server device includes a runtime service that receives a request to provide access for the operating system application to a first data storage partition, accesses the partition locking key in the hidden partition, and uses the partition locking key to unlock the first data storage partition to allow the operating system application to access data stored thereon.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Dell Products L.P.
    Inventors: Chitrak Gupta, Shekar Babu Suryanarayana
  • Patent number: 10789251
    Abstract: Method and apparatus for stress management in a searchable data service. The searchable data service may provide a searchable index to a backend data store, and an interface to build and query the searchable index, that enables client applications to search for and retrieve locators for stored entities in the backend data store. Embodiments of the searchable data service may implement a distributed stress management mechanism that may provide functionality including, but not limited to, the automated monitoring of critical resources, analysis of resource usage, and decisions on and performance of actions to keep resource usage within comfort zones. In one embodiment, in response to usage of a particular resource being detected as out of the comfort zone on a node, an action may be performed to transfer at least part of the resource usage for the local resource to another node that provides a similar resource.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 29, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Patrick W. Ransil, Aleksey V. Martynov, James S. Larson, James R. Collette, Robert Wai-Chi Chu, Partha Saha
  • Patent number: 10777240
    Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 15, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yuheng Zhang, Po-Shen Lai, Hao Su
  • Patent number: 10775773
    Abstract: A management apparatus acquires backup data from a plurality of devices, and stores the acquired backup data in a database in association with position information of the plurality of devices. The management apparatus restores the backup data included in the database, to the device that is present at a position corresponding to the position information associated with the backup data.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 15, 2020
    Assignee: FANUC CORPORATION
    Inventor: Takeshi Ikki
  • Patent number: 10776035
    Abstract: A storage system and storage control method are provided in which a plurality of volumes to be processed by a storage control unit are distributed and evacuated in a normal storage control unit without recovering redundancy of the storage control unit having decreased redundancy, and the storage control unit itself having the decreased redundancy is deleted after the evacuating is completed, and thus reservation information processing resources for guaranteeing recoverability of the redundancy become unnecessary.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 15, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kenta Sato, Akira Deguchi, Tomohiro Kawaguchi
  • Patent number: 10754789
    Abstract: Provided are systems and methods for an address translation circuit for a memory controller. The address translation circuit can include an address translation table. A first set of rows in the address translation table can be associated with all virtual machine identifiers supported by the memory controller. A second set of rows can be associated with only a particular virtual machine identifier. The address translation circuit can receive an input address for a transaction to processor memory. The address translation circuit can determine an index by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes the address translation for the input address. The address translation circuit can generate and output a translated address using the address translation.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Steven Scott Larson
  • Patent number: 10749949
    Abstract: Embodiments described herein provide a system for facilitating dynamic content distribution in an enterprise environment. During operation, the system receives, from a controller of the enterprise environment, an instruction for downloading a piece of content from one or more peers of a peer-to-peer protocol. The instruction can include a file descriptor that indicates a set of blocks the piece of content is divided into. The system can receive an offer for a first block of the set of blocks from a first peer of the one or more peers and determine whether the system is in a full peer relationship with a second peer of the one or more peers. The full peer relationship indicates that the second peer and the system are clients and servers of each other. If the system is in a full peer relationship, the system elects, between the second peer and the system, a sender for a first request that responds to the first offer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Marc E. Mosko, Ehsan Hemmati
  • Patent number: 10706146
    Abstract: A method and apparatus for detecting kernel data structure tampering are disclosed. In the method and apparatus, a memory region of a computer system is scanned for one or more characteristics of a kernel data structure of an operating system kernel. It is then determined, based at least in part on identifying whether the one or more characteristics are found in the memory region, whether the kernel data structure is stored in the memory region of the computer system for tampering with the kernel data structure.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Nicholas Alexander Allen
  • Patent number: 10705902
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to store crash-dump information in a boot partition following a system crash within the data storage controller. Within illustrative examples described herein, the boot partition may be read by a host device without the host first re-installing valid firmware into the data storage controller following the system crash. In the illustrative examples, the data storage controller is configured for use with versions of Peripheral Component Interconnect (PCI) Express—Non-Volatile Memory express (NVMe) that provide support for boot partitions in the NVM. The illustrative examples additionally describe virtual boot partitions in random access memory (RAM) for storing crash-dump information if the NAND has been corrupted, where the crash-dump information is retrieved from the RAM without power-cycling the RAM.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: July 7, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinod Sasidharan, Rishabh Mahajan, Abhishek Mourya
  • Patent number: 10705752
    Abstract: Embodiments provide a method, a system, and a computer program product for performing copy operations of one or more data units in a hierarchical storage management (HSM) system. The HSM system includes an upper layer and a lower layer. The upper layer includes multiple storage nodes having a grid configuration. The method comprises scheduling a copy operations of multiple data units each of which is stored in at least one of the multiple storage nodes such that loads on the copy operations are distributed among the multiple storage nodes in which the multiple data units are stored and copying the multiple data units to the lower layer in accordance with the scheduling.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kousei Kawamura, Koichi Masuda, Sosuke Matsui, Shinsuke Mitsuma, Takeshi Nohta, Takahiro Tsuda
  • Patent number: 10705734
    Abstract: A set of data storage values is received. It is determined that a data storage value in the set will not fit in an available memory segment including variable data column widths based at least in part on data sizes specified in a plurality of segment layout maps. A memory segment is selected for which a column width of a column will be expanded. A column width of the selected memory segment is expanded. A segment layout map corresponding to the selected memory segment is updated. The set of data storage values is stored in the selected memory segment.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 7, 2020
    Assignee: MEDALLIA, INC.
    Inventor: Thorvald Natvig
  • Patent number: 10684881
    Abstract: A computer-implemented method, computer program product and computing system for batch processing computing elements on a computing system are provided. The computer-implemented method, computer program product and computing system determine a configuration of the computing system hosting the computing elements, identify a plurality of computing elements to batch process, and batch process the plurality of computing elements based on the determined configuration of the computing system.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robin Y. Bobbitt, Nicholas Ibarluzea, Matthew P. Jarvis, Brianna A. Kicia, Max W. Vohlken
  • Patent number: 10678703
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the name portion to the logical addresses defined for the entire non-volatile storage media.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 10671573
    Abstract: The method includes identifying a first data table that includes a set of rows and a structure. The method further includes creating a second data table and a third data table having a matching structure as the first table. The method further includes distributing the set of rows of the first data table, wherein the set of rows is distributed between one or more of the second data table and the third data table based upon preset parameters. The method further includes, generating one or more operations for the set of rows. The method further includes executing one of the one or more generated operations on the second data table and the third data table.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Timotheus D.B. Giuliani, Tunca Karabel, Johannes S. Kern, Philipp Klippel, Klaus J. Liegert
  • Patent number: 10673981
    Abstract: Techniques for rebalancing computing workloads between a set of on-premises resources of an on-premises system and a set of cloud computing resources of a cloud computing system. A method embodiment commences upon detecting a rebalancing trigger event. Responsive to the trigger event, a set of resource data corresponding to observations pertaining to the on-premises resources and resource data corresponding to observations pertaining the cloud resources is accessed. Based at least in part on the resource data, a plurality of candidate workload rebalancing plans are generated. The candidate workload rebalancing plans are evaluated against the likelihood of achieving quantitative objectives resulting from the rebalancing. A portion of the scheduling commands to carry out the workload rebalancing plans are sent to the cloud computing system, and another portion of the scheduling commands are sent to the on-premises computing system. The receiving computing systems carry out the scheduling commands.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 2, 2020
    Assignee: Nutanix, Inc.
    Inventors: Manjul Sahay, Ramesh U. Chandra
  • Patent number: 10664751
    Abstract: A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 26, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Douglas R. Reed
  • Patent number: 10664315
    Abstract: A distributed computing system for automatic constraint-based data resource arrangement, comprising a plurality of computing components being communicatively coupled to each other, each computing component comprising the following data resources: data storage media for storing client-related digital information, a data processor for processing said client-related digital information, and a network communications interface for communicating said client-related digital information; and a constraint engine for automatically determining alternate arrangements of said data resource assignments, said constraint engine comprising a constraint processor and a constraint database, said constraint database for receiving and storing changeable digital constraint parameters indicative of permissible operational constraints on said data resources, wherein said alternate arrangements comply with at least a first set of said changeable digital constraint parameters; wherein said data resource assignments are reassigned from
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 26, 2020
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Jacob Taylor Wires, Andrew Warfield
  • Patent number: 10664197
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 10628452
    Abstract: The invention relates to a method, computer program product and computer system for providing attribute value information for a data extent comprising a set of data entries.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michal Bodziony, Lukasz Gaza, Artur M. Gruszecki, Tomasz Kazalski, Konrad K. Skibski