Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

Abstract: A data storage device includes storage media with multiple media zone attributes of storage performance. The storage device includes a data channel that is connectable to a host system. The data channel receives an object from the host system that has a requested storage attribute attached to the object. The storage device comprises an object-based storage interface that couples between the data channel and the storage media. The object-based storage interface schedules the object for storage in a selected zone of the multiple media zones based on the attributes and requested attributes.

Abstract: A method for managing data in a memory of a computer. The method includes the steps of: prohibiting a specified memory area in a memory from being accessed temporarily or intermittently; and attaching, to first data, a first mark indicating that the first data has been read when a page fault has occurred as a result of an access by any process to read on the first data; where the first data is present in a specified memory area prohibited from being accessed; and where at least one of the steps is carried out using a computer device.

Abstract: Technologies are provided for reclaiming a file system coupled to a block device. In these technologies, a dummy file is created. The dummy file is expanded to fill a volume in the block device. A mapping of the dummy file to locations in the volume is retrieved. When the mapping of the dummy file to the locations in the volume is retrieved, corresponding space in the volume is reclaimed. This space may include the locations in the volume corresponding to the mapping of the dummy file. When this space in the volume is reclaimed, the dummy file is deleted.

Abstract: A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

Abstract: Described are techniques for partitioning storage of a data storage system. A plurality of storage groups is selected. Each of the plurality of storage groups includes one or more devices and is associated with an allocation policy including a first threshold specifying one of a minimum or a maximum amount of storage of a first of a plurality of storage tiers. Workload data for the plurality of storage groups is analyzed. Storage of a plurality of storage tiers is partitioned for use by the plurality of storage groups in accordance with criteria. The criteria includes workloads of the plurality of storage groups and the allocation policy associated with each of the plurality of storage groups.

Abstract: A computer-implemented method for discovering a plurality of storage area network (SAN) devices for a virtual machine. At a SAN device of the plurality of SAN devices, physically adjacent SAN devices connected to the SAN device are discovered. The physically adjacent SAN devices connected to the SAN device are registered at a name server.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.

Abstract: A system including a storage device and a controller. The storage device is configured to store a map. The map relates (i) a first portion of a memory to a first order of first dimensions, and (ii) a second portion of the memory to a second order of second dimensions. The first portion of the memory and the second portion of the memory are non-overlapping. Each of the first dimensions and each of the second dimensions has corresponding memory cells in the memory. The controller is configured to control access to the first portion of the memory according to the first order of first dimensions while controlling access to the second portion of the memory according to the second order of the second dimensions.

Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.

Abstract: Automatically aligning virtual blocks of partitions to blocks of underlying physical storage is disclosed. In some embodiments, a starting offset of a partition included in a logical container is detected. In some embodiments, a misalignment correction amount for a partition included in a logical container is detected. In some embodiments, a misalignment associated with a partition included in a logical container is corrected.

Abstract: Releasing a data set at a source device in connection with migrating data from the source device to a target device includes mapping application address space to address space containing metadata for the target device and providing additional local metadata therefor, replacing within the application the address of metadata for the source device with the address of metadata for the target device, setting a diversion flag that is part of the additional local metadata, where the diversion flag indicates a remapping of extent, and closing and unallocating the data set at the source device. Releasing a data set at a source device in connection with migrating data from the source device to a target device may also include determining if an application uses standard I/O operations. The metadata may include UCB data.

Abstract: A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.

Abstract: An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

Abstract: Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.

Abstract: Disclosed is a computer system with a physical storage device. The physical storage device has a plurality of partitions and allows a user to select and combine at least two partitions to form a virtual storage device to be accessed by the operating system and makes unselected partitions inaccessible to the operating system.

Abstract: A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.

Abstract: A storage device includes a memory and a processor. The processor is configured to store data items for a host in respective logical addresses, to identify a first subset of the logical addresses as frequently-accessed logical addresses and a second subset of the logical addresses as rarely-accessed logical addresses, to manage the frequently-accessed logical addresses separately from the rarely-accessed logical addresses, to receive from the host an indication of one or more logical addresses, which are used for storing data that is identified by the host as having been deleted by a user, and to add the logical addresses indicated by the host to the rarely-accessed logical addresses.

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other ways. A target active way count is maintained and the system cache attempts to keep the number of currently active ways equal to the target active way count. The bandwidth and allocation intention of the system cache is monitored. Based on these characteristics, the system cache adjusts the target active way count up or down, which then causes the number of currently active ways to rise or fall in response to the adjustment to the target active way count.

Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

Abstract: Methods, systems, and computer storage mediums including a computer program product method for formatting storage volumes are provided. One method includes creating a storage volume including a global counter and partitioned into multiple storage segments including a segment counter and partitioned into multiple stripes, wherein the global counter and each segment counter match at an initial time. The method further includes receiving a command to write data to a first stripe, comparing a first segment counter associated with the segment, determining if the segment and global counters match, and re-initializing first metadata associated with the segment to indicate the first segment requires formatting if the counters do not match. One system includes a processor for performing the above method and one computer storage medium includes a computer program product configured to perform the above method.

Abstract: Embodiments described herein are directed to providing scalability to software applications. A computer system partitions a portion of data stored in a directory services system into multiple different data partitions. Each data partition includes a primary writable copy and at least one secondary read-only copy of the data. The computer system receives a client request for a portion of the data that is stored in the directory services system and accesses various stored partition mappings to determine which of the different data partitions includes the requested data. The computer system also accesses a dynamic copy locator to determine which of the read-only copies of the indicated partition to access and provide the accessed primary writeable copy of the indicated partition and the determined read-only copy to the client in a virtualized manner so that the client is not aware of the data partitions.

Abstract: A mechanism is provided for cross-allocated block repair in a mounted file system. A set of cross-allocated blocks are identified from a plurality of blocks within an inode of the mounted file system, based on a corresponding bit associated with each cross-allocated block in a duplicated block information bitmap being in a first identified state. The set of cross-allocated blocks are repaired using a user-defined repair process. Then one or more of the set of cross-allocated blocks are deallocated based on results of the user-defined repair process.

Abstract: A file storage apparatus comprises: duplication determination unit that determines whether file supplied from client apparatus and file stored in storage unit coincide with each other in same format, and stores the file supplied from client apparatus in the storage unit if the files do not coincide in the same format; and storage management unit that associates, if duplication determination unit determines that the files coincide in the same format, format of the file supplied from the client apparatus with the file stored in the storage unit, reads file stored in the storage unit in response to file read request from client apparatus, converts, if format associated with the read file exists, the read file into the format, and provides the converted file.

Abstract: While system-directed checkpointing can be implemented in various ways, for example by adding checkpointing support in the memory controller or in the operating system in otherwise standard computers, implementation at the hypervisor level enables the necessary state information to be captured efficiently while providing a number of ancillary advantages over those prior-art methods. This disclosure details procedures for realizing those advantages through relatively minor modifications to normal hypervisor operations. Specifically, by capturing state information in a guest-operating-system-specific manner, any guest operating system can be rolled back independently and resumed without losing either program or input/output (I/O) continuity and without affecting the operation of the other operating systems or their associated applications supported by the same hypervisor.

Abstract: A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The system also includes a system memory coupled to the processor, wherein the system memory stores RAM resize instructions that, when executed, enable the public RAM and the secure RAM to be dynamically resized. The system memory may also store save/restore secure RAM instructions that, when executed, perform a save operation that saves the secure RAM to non-volatile memory and a restore operation that restores the secure RAM from the non-volatile memory. The system memory may also store arbitration instructions that, when executed, enable a cryptographic hardware accelerator (HWA) to be shared by a secure application and a public application.

Abstract: Techniques are described herein that are capable of optimizing (i.e., deduplicating) data in a virtualization environment. For example, optimization designations (a.k.a. deduplication designations) may be assigned to respective regions of a virtualized storage file. A virtualized storage file is a file that is configured to be mounted as a disk or a volume to provide a file system interface for accessing hosted files. In accordance with this example, each optimization designation indicates an extent to which the respective region is to be optimized (i.e., deduplicated). In another example, a virtualized storage file is mounted to provide a virtual disk that includes hosted files. In accordance with this example, optimization designations are assigned to the respective hosted files. In further accordance with this example, each optimization designation indicates an extent to which the respective hosted file is to be optimized.

Abstract: Described herein are at least one apparatus and methods for implementing partitioning in memory cards and modules. A representative memory card/module in accordance with the invention may include a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module may further include a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module may include means for controlling the partitioning of the memory device(s). The memory controller may be configured to operate the memory device(s) in accordance with the partition information.

Abstract: A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment are defined. Configuring a separate environment may include specifying a physical memory usage cap for the separate environment. A global resource capping background service enforces physical memory caps on any separate environments that have specified physical memory caps.

Abstract: Security parameters used to encrypt data stored on a storage device may be protected using embodiments of systems and methods described herein. During a resize operation, data stored on a memory unit in the storage device may be altered prior to communicating an updated partition size to a host computer. In some examples, data is altered prior to storing the updated partition sizes in the storage device. In this manner, a host system may not receive the updated partition sizes until after the data is altered. Altering data may avoid exposure encrypted data, information about one or more security parameters used to encrypt data on the memory unit or decrypt data retrieved from the memory unit, or combinations thereof.

Abstract: A storage device is disclosed, in which the device comprises memory (222) divisible into multiple zones, each zone comprising a plurality of physical blocks of the memory (222) and for associating with a zone-based address map for mapping between logical and physical addresses of said zone. The multiple zones are configurable independently of each other, and the memory (222) is non-volatile or volatile memory. A related zone-based block management and address mapping method, and a zone-based block management and address map for a storage device are also disclosed.

Abstract: A method may include storing data in one or more first-type stripes spanning a plurality of N storage resources and having N?1 data strips for storing the data and a parity strip for storing parity information for the data stored to the particular first-type stripe and each of the plurality of storage resources includes one of a data strip or a parity strip of the particular first-type stripe if the data to be stored exceeds a threshold size. If the data to be stored does not exceed a threshold size, the method may include storing the data in a second-type stripe and a third-type stripe each spanning N storage resources, such that each stripe comprises N?1 data strips for storing the data and a metadata strip for storing address information for the corresponding second-type strip or third-type strip.

Abstract: A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: In tiered storage subsystems in which pages are automatically allocated to appropriate storage media based on the access frequency in page units, since the number of storage media is not simply proportional to the performance, it was difficult to design in advance a tier configuration satisfying the required performance. According to the present invention, a cumulative curve of I/O distribution is created based on a result of measurement of I/O accesses performed to the storage subsystem, and RAID groups (RG) are allocated sequentially in order from RGs belonging to tiers having higher performances to the cumulative curve of I/O distribution. When either a performance limitation value or a capacity of the RG exceeds the cumulative curve of I/O distribution, a subsequent RG is allocated, and the process is repeated so as to compute the optimum tier configuration.

Abstract: An apparatus and associated method is provided employing data capacity determination logic. The logic dynamically changes a data storage capacity of an electronic data storage memory. The change in capacity is made in relation to a transient energy during a power state change sequence performed by the electronic data storage memory.

Abstract: A hybrid memory system includes a central processing unit, a storage device configured to store user data and code data, and a main memory including a volatile memory and a nonvolatile memory, the main memory being configured to receive data necessary to perform an operation of the central processing unit from the storage device and to store the data, a part of the volatile memory being allocated for a cache for data stored in the nonvolatile memory.

Abstract: Methods and systems for using one or more solid-state drives (SSDs) as a shared cache memory for a plurality of storage controllers coupled with the SSDs and coupled with a plurality of storage devices through a common switched fabric communication medium. All controllers share access to the SSDs through the switched fabric and thus can assume control for a failed controller by, in part, accessing cached data of the failed controller in the shared SSDs.

Abstract: A computer system and an operating method thereof are disclosed herein. The operating method includes: dividing a file into a plurality of file segments; transmitting the file segments to an integrated circuit (IC) sequentially: receiving, through the IC, the file segments sequentially, and writing an operating file segment in a target storage page of a target block when the operating file segment is received; determining whether the operating file segment s successfully written in the target storage page; commanding the IC to erase the target block in a case that the operating file segment is not successfully written in the target storage page; searching a re-transmission start file segment corresponding to a start address of the target block; and, sequentially transmitting a plurality of remaining file segments of the file started from the re-transmission start file segment to the IC.

Abstract: Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss in response to determining the page address miss in a page addressing buffer, and saving the mapping as an entry in an array. The computer implemented method creates a preserved array from the array in response to determining the dispatched partition to be an undispatched partition. The computer implemented method further analyzes of the preserved array for a compressed page in response to determining the undispatched partition is now redispatched, and decompresses the compressed page prior to the partition being redispatched.

Abstract: Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.

Abstract: An exemplary method of creating a target storage layout table referenced for partitioning a storage space of a storage device includes following steps: identifying defective storage areas in the storage space of the storage device, and accordingly generating an identification result; and creating the target storage layout table according to the identification result; wherein when the identification result indicates that an actual storage area corresponding to a pre-defined partition with a pre-defined partition size has at least one defective area, setting a partition size of a partition defined in the target storage layout table according to the pre-defined partition size and a size of the at least one defective area.

Abstract: Various systems and methods for cooperative tiering between an application and a storage device. One method can include receiving information from the application where the information identifies a storage object and identifies a location in a storage device. The location identifies one or more tiers of a plurality of tiers included in the storage device, and the storage object is assigned to the one or more tiers. The method also involves detecting whether the storage object is stored in the one or more tiers. If not, the storage device copies the storage object to the identified location. The information can also include an instruction by the application to move the storage object from a first tier to a second tier.

Abstract: An extent-based storage architecture is implemented by a storage server receiving a read request for an extent from a client, wherein the extent includes a group of contiguous blocks and the read request includes a file block number. The storage server retrieves an extent identifier from a first sorted data structure, wherein the storage server uses the received file block number to traverse the first sorted data structure to the extent identifier. The storage server retrieves a reference to the extent from a second sorted data structure, wherein the storage server uses the retrieved extent identifier to traverse the second sorted data structure to the reference, and wherein the second sorted data structure is global across a plurality of volumes. The storage server retrieves the extent from a storage device using the reference and returns the extent to the client.

Abstract: The relay unit splits the storage area in the buffer into a plurality of partitioned areas, manages the same and, upon receiving a read request from the access request source, selects and allocates one or more from the plurality of partitioned areas and, on condition that the relevant partitioned areas are allocated, transmits the read request to the memory control unit, wherein the memory control unit reads the data requested in the received read request from the memory, splits the data which is read into a plurality of units, and transmits the same to the relay unit, wherein the relay unit stores each of the data transmitted from the memory control unit in each of the allocated partitioned areas sequentially, on condition that all of the data is stored, reads each of the data from each of the allocated partitioned areas, compiles each of the data which is read into one, transmits the same as read data to the access request source, and releases all of the respective allocated partitioned areas.

Abstract: The performance and efficiency of file systems for data allocation access in random-access storage media is enhanced by isolating block addresses from other metadata and the actual data itself in a separate address space. Block addresses are stored in memory and file system structures that are separate from those structures that store other metadata and the actual data. This affords faster address lookup and access to data storage locations, and more efficient storage allocation and accessing algorithms. The block address isolation may be implemented in separate logic, in a hardware controller for a storage drive, or in software in a storage hierarchy.

Abstract: A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer memory including volatile RAM and non-volatile RAM. The memory controller is configured to select one of the volatile RAM and the non-volatile RAM to temporally store the write data based on a write pattern of the write data, and to transmit a host command complete signal to a host when the write data is stored in the non-volatile RAM.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.

Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.