Abstract: Described are techniques for overriding an existing device reservation. Discovery processing is performed by a first data storage system to locate a specified device. The discovery processing includes determining whether there is a reservation conflict for said device of a second data storage system. If there is a reservation conflict for the device, a command is issued from the first data storage system to the second data storage system during said discovery processing to create an override for said reservation conflict. The override causes processing to be performed at a subsequent point in time so that an existing reservation associated with the reservation conflict is overridden in connection with performing a first process on said first data storage system.

Abstract: A software-based RAID system is provided that enables configuration conflicts to be detected and resolved between a PD that is logically present but physically missing, and a PD that is physically and logically present. In accordance with the invention, a determination is made as to whether such a configuration conflict exists, and if so, the logically-present, but physically missing, reference identifier associated with the PD is remapped to a port number that currently is not in use.

Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.

Abstract: In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.

Abstract: The present invention provides an equalizer processing module within a wireless terminal having an equalizer interface that receives an incoming baseband signal from a baseband processor operably coupled to the equalizer processing module and outputs soft decisions. A processor or advanced reduced instruction set computer (RISC) machine (ARM) couples to the equalizer interface while an equalizer accelerator module operably couples to the processor or ARM. Processing of the incoming baseband signal to produce soft decisions is performed by the combination of the processor and equalizer accelerator module. A sample capture buffer and an equalizer output buffer which may or may not be within the equalizer processing module allow data to be sampled and serves as the input and output for the equalizer processing module. This equalizer accelerator may specifically perform compute intensive operations such as Trellis computations for MAP equalization or MLSE equalization.

Abstract: In a particular embodiment, a controller is disclosed that is adapted to control read/write access to a storage media. The controller includes data corruption detection logic to reconstruct a logical block address (LBA) lookup table from metadata stored at the storage media upon restart and re-initialization after a power loss event. The controller further includes duplicate conflict resolution logic to identify a valid data block from multiple data blocks that refer to a single LBA. The duplicate conflict resolution logic counts a first number of valid physical pages and a second number of different sectors in each of the multiple data blocks. The duplicate conflict resolution logic selects the valid data block from the multiple data blocks based on at least one of the first and second numbers.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.

Abstract: A method and apparatus for storing pattern matching data and a pattern matching method using the method and apparatus are provided. The method of storing original data for pattern matching in a pattern matching apparatus includes: dividing the original data into segments of a predetermined size; performing a hash operation on each of the divided segments; determining whether or not the hash operation value of each segment causes a hash collision with a hash operation value stored in a first external memory disposed outside the pattern matching apparatus; and controlling the hash operation value of each segment determined not to cause a hash collision to be stored in the first external memory. According to the method and apparatus, the original data desired to be used for pattern matching can be stored at a faster speed in a pattern matching data storing apparatus.

Abstract: In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The generation of the second object code takes into account one or more locations of one or more defects in a cache on a processor such that one or more instructions in the second object code are written only to nondefective locations in the cache.

Abstract: Dynamically allocated memory is managed in real-time. This real-time management capability enables an invalid access of the dynamically allocated memory to be detected at the time the invalid access occurs, rather than at some later point in time. This real-time management capability can be dynamically activated/deactivated on a per process basis.

Abstract: A disk drive or similar storage medium uses a semantic understanding of its associated file system to monitor file metadata and derive block liveness normally only known by the file system. Knowledge of block liveness can be used to improve the disk performance and to create a disk that provides for secure deletion without explicit instructions from the file system.

Abstract: The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cache line size, set associativity, address-to-cache-line mapping algorithm, and set replacement algorithm. The optimization parameters specify the minimum acceptable efficiency level. The application parameters include a list of object modules and functions within those modules. All possible orderings of the modules are stepped through to determine where the specified functions fall within the cache given the location of the function within the module. The function locations in each permutation of the orderings are analyzed to find a solution that matches or beats the optimization parameters.

Abstract: A dataset is divided into pieces and stored at multiple locations and the system dynamically increases or decreases the number of storage locations where the pieces of the data set may be stored. A data structure comprises a first data field including a first index and a first element, and one or more data fields each with an index and an element. The elements of the one or more data fields include a token representing a location associated with the index of the first data field. A data row of a data set is mapped to the index of a data field using a second index. The second index is derived from a data row of the data set using a hash function. The second index is then mapped to the index of a data field included in the one or more data fields using a modulus function.

Abstract: Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by providing a storage address configuration including gaps in valid addresses. Such a programming error is detected and an exception is thrown (that is, an addressing error is detected and indicated) responsive to an address reference to such a gap in valid addresses. Gaps are configured at complementary address ranges to facilitate detection of such aliasing errors.

Abstract: A memory region access management technique. More particularly, at least one embodiment of the invention relates to a technique to partition memory between two or more operating systems or other software running on one or more processors.

Abstract: The portion of a source block storage resource to be replicated, and the corresponding portion of the block storage resource being written to, are each divided into a predefined number of equal-sized spans. A digest calculation is then generated for each span in a corresponding pair and compared. If the digests do not match, those spans are divided into still smaller spans, and digests are calculated and compare iteratively, to identify smaller areas of discrepancies and reduce the number of blocks that are actually written.

Abstract: A data processing system (2) is provided including a local memory (4) and a main memory (6). The local memory (4) is accessed by a data engine (8) using local-memory physical addresses. The main memory (6) is accessed by a microprocessor (10) using main-memory addresses. A translation store (16) serves to store physical address TAGs indicating the mapping between data stored within the local memory (4) and corresponding data stored within the main memory (6). A coherency management mechanism (18) serves to use MESI coherency control data to manage the coherency between data values stored both in the local memory (4) and the main memory (6).

Abstract: One goal of consistency interval replication is to achieve a consistent copy of data generated by independent streams of writes from nodes in a clustered/distributed environment. Two writes to the same block from different nodes may arrive at a replication target in a different order from the order in which they were written to primary storage. A consistency interval coordinator may analyze a list of blocks modified during a consistency interval to determine conflict blocks written to by two different nodes during the same consistency interval. Conflict resolution may involve a node reading data for a conflict block from primary storage and forwarding it to the replication target or a node completing a suspended in-progress write for the conflict block. Once the conflicts have been resolved, the replication target may checkpoint the data modified during the interval and nodes may resume writes to the conflict blocks for the new interval.

Abstract: A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more stop indicators corresponding to any detected conflict between the memory addresses, where a given stop indicator indicates a memory hazard. Next, the processor executes the instructions for detecting the conflict between the memory addresses and generating the one or more stop indicators.

Abstract: A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when memory operations are performed in parallel using at least a portion of the vectors, and tracking positions in at least one of the vectors of any detected conflict between the memory addresses. Next, the processor executes the instructions for detecting the conflict between the memory addresses and tracking the positions.

Abstract: A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, where a given predicate value indicates elements in at least the portion of the vector that can be processed in parallel. Next, the processor executes the instructions for detecting the conflict between the memory addresses and generating the one or more predicate values.

Abstract: A heap management system for a database uses “sets” of pages to store database information. As memory for each successive set of pages is allocated, more memory is allocated for storing rows in each page of the set. Similarly, the maximum number of rows of information storable in each page of each set is greater for each successive set of pages. The number of computer instructions needed to resolve (or calculate) the memory address for a particular row is fixed. Given a target row number, (and the number of rows in the first page, and the width of the column or column group), only a fixed number of computer instructions need to be executed to resolve the starting memory address for the target row. In addition, information of the same type (i.e., one or more columns of a table) may be stored in different pages, and these pages may be located in discontiguous memory segments. This allows space for new rows to be allocated, without requiring all pre-existing rows to be moved to a different memory segment.

Abstract: A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.

Abstract: A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.

Abstract: A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.

Abstract: A control system enables a plurality of users to execute a single-user application simultaneously in a multi-user OS which causes address conflicts under simultaneous execution and save results for each user avoiding the address conflicts. The control system comprises a control unit 10 which changes write addresses of applications 51-53 which cause address conflicts under simultaneous execution in a multi-user OS from original addresses specific to each application to a mapped address in a subordinate directory of any of user profile directories 61, 62 specific to each user who runs the application(s) 51-53.

Abstract: A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning is virtualized to produce a first logical address range. A second physical address range allocated for system memory for the operating system is virtualized to produce a second logical address range. The first physical address range and the second physical address range are non-contiguous. Virtualization of the first and second physical address ranges is had such that the first logical address range and the second logical address range are contiguous. A memory mapped input/output physical address range that is intermediate the first physical address range and the second physical address range is virtualized to produce a third logical address range.

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Abstract: A technique coordinates access to shared data on a remote device from a local device having local physical memory. The technique involves observing a page table entry (PTE) on the remote device. The PTE is stored in a page table used for managing virtual to physical address translations and handling page faults between semiconductor memory and magnetic disk drive memory on the remote device. The technique further involves blocking access to the shared data from the local device when the PTE indicates that shared data corresponding to the PTE is in use on the remote device. The technique further involves moving the shared data into the local physical memory from the semiconductor memory of the remote device, and providing access to the shared data in the local physical memory when the PTE indicates that shared data corresponding to the PTE is not in use on the remote device.

Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.

Abstract: In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue.

Abstract: In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor (VMM) and attributes associated with entries in the shadow translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.

Abstract: The present invention may be used for determining a topology of a network in the presence of network address translation. From an active client behind a translating device, communications are initiated that effect the network address translation. The communications are monitored beyond the translating device to infer partitioning of servers into equivalence sets relative to the network topology induced by the network address translation. Active clients behind the translating device may include a respective actual sending address in a message sent to a server beyond the translating device. The server beyond the translating device distinguishes between communications affected by and not affected by network address translation, which may include comparing an apparent source address of a message against an actual address provided in the message by the active client behind the translation device. The external server may also distinguish between active and passive client messages.

Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

Abstract: This invention enables managing data consistency between different data volumes by managing I/O traffic in a data storage environment. A methodology for managing data consistency, in accordance with the principles of the invention, comprises the steps of arresting processing of I/O traffic during an administrative operation, queuing any I/O that follow the arresting step in a queuing data structure and processing each queued I/O until the I/O processing is completed. Certain implementations of the invention include a system, a computer program product, or an apparatus, wherein each embodiment is configured for carrying out the steps involved in the methodology.

Abstract: In one aspect of the invention, text data recorded on a CD conforming to the CD-TEXT format is displayed using a minimum amount of memory. Storage capacity to be used per data item is calculated by dividing the available storage capacity by the number of text data items to be displayed on a display section, and the text data is read from the CD and is stored in a memory by limiting the storage capacity per data item to the thus calculated storage capacity. In another aspect of the invention, text data is acquired in as many languages as possible by using a minimum amount of memory. A block selected based on a predetermined criterion, such as the starting block or a block recorded in a specific language, is acquired first, and then a further block or blocks are selected and acquired as the remaining memory capacity allows.

Abstract: Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of instructions. Younger instructions having potential dependencies on older instructions are suspended if the partial comparison yields a match. One or more subsequent comparisons are made for suspended instructions based on portions of the addresses referenced by the instructions that were not previously compared. If subsequent comparisons determine that the addresses of the instructions do not match, the suspended instructions are reinstated and execution of the suspended instructions is resumed. In one embodiment, data needed by suspended instructions is speculatively requested in case the instructions are reinstated.

Abstract: A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Abstract: A cache storage system and method are provided for saving storage space in a cache, the system and method for use in a data storage system having multiple storage devices and multiple virtual addresses, each virtual address having a data object associated therewith. Each data object is stored at a storage device location having a unique identifier. The cache storage system and method include a cache for storing a data object associated with at least one virtual address. For a first virtual address, the first virtual address data object is staged into the cache. For a second virtual address, a pointer is generated for use in pointing to the first virtual address data object staged in the cache when the storage device location identifier of the second virtual address data object matches the storage device location identifier of the first virtual address data object.

Abstract: A memory controller may be implemented using dynamic page conflict prediction to control the closure of memory pages. A memory controller may include a page history register configured to store a value indicating the pattern of page conflicts encountered by a memory device. The memory controller may include a global conflict predictor for storing probabilities of page conflicts associated with values of the page history register. In response to receiving a memory access request, a control unit may be configured to determine whether the memory access request causes a page conflict. The memory controller may be configured to update the global conflict predictor based on this determination. If a page conflict is predicted, the memory controller may automatically close the targeted page (e.g., by initiating the memory access in auto-precharge mode) upon completion of the memory access requested by the memory access request.

Abstract: In a disk-based data storage system, a controller configured to control a reference count regeneration operation, the controller includes a control register, an address register, a status register, a boundary register, and an embedded memory. The control register may be configured to set up and initiate program instructions that are executed by at least one processor. The address register may be configured as a cache address pointer and correspond to at least one of a sort output list pointer, a virtual track table input list pointer, a reference list pointer, a track number table pointer, and a reference count mis-compare list pointer. The status register may be configured to indicate status of a routine. The routine includes at least one of a radix sort, a reference list count, a combine counts, and a merger of the reference list count into the TNT to generate an updated TNT.

Abstract: The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cache line size, set associativity, address-to-cache-line mapping algorithm, and set replacement algorithm. The optimization parameters specify the minimum acceptable efficiency level. The application parameters include a list of object modules and functions within those modules. All possible orderings of the modules are stepped through to determine where the specified functions fall within the cache given the location of the function within the module. The function locations in each permutation of the orderings are analyzed to find a solution that matches or beats the optimization parameters. In an embodiment, a front-end analysis program (“tool”) and a back-end processing stage, usually related to a linker, are provided.

Abstract: Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

Abstract: In a data storage system in which there can be multiple references to a single instance of an object, a method for regenerating the number of references to each object instance. The method includes radix sorting the references to the objects to generate a reference list, counting the references to each unique object and merging the counts with the object descriptions, placing the count of the number of references to each object into the respective object description. The sorting, counting and merging techniques used by this method generate sequential memory access patterns that enable efficient use of low-cost memory and block-oriented memory access interconnect fabric protocols. Furthermore, multiple instances of the sorting, counting and merging processes can be used in parallel to reduce the time required to regenerate the reference counts for a large number of objects.

Abstract: In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.

Abstract: A method for identification of memory assignment conflicts in the assignment of memory location addresses to a set of buffers. Programs run in embedded processors using buffers in a fixed storage space need to be mapped to addresses which do not overlap or create conflicts. The process of assigning start and end addresses for buffers can be tedious and error prone if performed without automation. The present invention presents a tool that automates the task of mapping the memory buffers and heaps to physical space. The tool utilizes a memory buffer allocation table created by the programer. The table designates the locations, sizes and overlays of all the buffers and heaps. The tool checks the validity of the memory map specified. If it is found to be invalid, the user is notified of the error. Otherwise, a memory table is created which will serve as “hooks” for runtime buffer manipulation.