Abstract: An address translation apparatus comprises: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier which is composed of plural bits; comparison information storage means for storing comparison information which defines a method for comparing a process identifier possessed by a process that is currently executed, with the process identifier in each entry; process comparison means for comprising the process identifier possessed by the process that is currently executed, with the process identifier in the entry, on the basis of the comparison information; and entry retrieval means for retrieving, from the entry storage means, an entry including a virtual page number equal to a virtual page number supplied from the outside, and a process identifier which matches the process identifier of the currently executed process, according to the result of comparison by the process comparison means.

Abstract: A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield.

Abstract: The present invention relates to a system and a method for preventing address conflicts when establishing breakpoints and applying one or more patches to code residing on a read only memory (ROM) device. The system and method generally comprises identifying one or more program addresses which require patching, whereby one or more patch addresses are defined; evaluating address bits of the patch addresses and determining index bit positions, whereby address bits occupying the index bit positions define one or more unique tag indices; and storing the index bit positions in a tag programming memory.

Abstract: A computer system is presented implementing a system and method for properly ordering write operations. The system and method for properly ordering write operations aids in maintaining memory coherency within the computer system. The computer system includes multiple interconnected processing nodes. One or more of the processing nodes includes a central processing unit (CPU) and/or a cache memory, and one or more of the processing nodes includes a memory controller coupled to a memory. The CPU or cache generates a write command to store data within the memory. The memory controller receives the write command and responds to the write command by issuing a target done response to the CPU or cache after the memory controller: (i) properly orders the write command within the memory controller with respect to other commands pending within the memory controller, and (ii) determines that a coherency state with respect to the write command has been established within the computer system.

Abstract: A flexible address mapping method and mechanism allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.

Abstract: A cache memory system (e.g., a translation-lookaside buffer 100) utilizing a reduced overhead entry selection process for overwriting and updating entries. The disclosed embodiment of the present invention uses a match bit, a detection operation (such as a status probe operation), and an efficient control mechanism to identify a particular translation in a translation-lookaside buffer 100 to be updated or overwritten. Based on the results of the probe operation, the match bit is selectively set or cleared. Next, a control mechanism selects one of two possible indices 110 and 114 (locations) in the translation-lookaside buffer 100 to perform a write operation. The first index 110 corresponds to an existing entry, while the second index 114 corresponds to a random entry to be overwritten. The selection process is essentially completed in a single step via dedicated logic. In this manner, overhead associated with selecting an entry to be updated is minimized.

Abstract: A method of detecting peripheral components for a computer system to effectively start a driver of the peripheral component connected to the bus. By scanning all the buses orderly to detect the peripheral components connected to the buses, the peripheral components can be effectively used. The method can further be applied for the peripheral components connected to the PCI uses, the hierarchy structure formed by the PCI to PCI bridge to start the drivers of the peripheral components.

Abstract: A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique defines two logical-to-physical address mapping modes that may be simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing individual memory locations, as well as memory strings, within the memory resources. These addressing modes include a bank select mode and a stream mode.

Abstract: In a method for providing concurrent access to virtual memory data structures, a lock bit for locking a virtual page data structure is provided in a page table entry of a page table. The page table is configured to map virtual pages to physical pages. Then, a first thread specifying an operation on the virtual page data structure is received. The first thread is provided exclusive access to the virtual page data structure by setting the lock bit in the page table entry such that other threads are prevented from accessing the virtual page data structure. A wait bit also may be provided in the page table entry to indicate that one or more of the other threads are in a wait queue when the first thread has exclusive access to the data structure. When the first thread no longer needs exclusive access to the data structure, a second thread is selected from among the other threads and is provided with exclusive access to the data structure.

Abstract: A method of forming a hashing code includes the steps of: first selecting a first linear feedback transform generator that is perfect over a first range. A maximum key length is determined next. When the maximum key length is greater than the first range for a transform, it is determined if a no collisions allowed condition exists. When the no collisions allowed condition exists, it is determined if the maximum key length is less than double the first range. When the maximum key length is less than double the first range, a first transform for a first part of a key is determined. A second transform for the key is then calculated. Next, a first-second combined transform is formed by concatenating the first transform and the second transform, wherein a first portion of the first-second combined transform is an address and a second portion of the first-second combined transform is a confirmer.

Abstract: A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address aliasing are provided through a physical address CAM, page size mask compares and a column copy tag function. Also supported are address aliasing that invalidates aliased lines, address aliasing with TLB entries with the same page sizes, and address aliasing the TLB entries of different sizes. Multiple page sizes are supported with extensions to the prevalidated cache tag design by adding page size mask RAMs and virtual and physical address RAMs.

Abstract: A conflict detection method for a disk drive controller is used to handle a conflict potentially occurring if the execution sequence of queued commands sent from a host to a controller is reordered to optimize disk drive transfers. The conflict detection method determines if there is an address range overlap between two queued commands. If an overlap exists, a conflict flag is set. The controller microprocessor utilizes this flag to restrict command reordering and prevent a conflict from producing erroneous data. Conflict detection and command reordering restriction are facilitated by a queued command RAM and a command FIFO. The queued command RAM stores command parameters indexed by command tag values. These parameters include command direction (read or write), LBA, block count, a valid flag and a conflict flag. The conflict detection method compares the address range of a new command with the address range of valid commands in the command RAM to determine range overlaps.

Abstract: A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.

Abstract: In one embodiment of the invention, each data value which is provided to a non-tagged, n-way cache is hashed with a number of bits which correspond to the data value, thereby producing a hashed data value. Preferably, the bits which are hashed with the data value are address bits. The hashed data value is then written into one or more ways of the cache using index hashing. A cache hit signal is produced using index hashing and voting. In a cache where data values assume only a few different values, or in a cache where many data values which are written to the cache tend to assume a small number of data values, data hashing helps to reduce false hits by insuring that the same data values will produce different hashed data values when the same data values are associated with different addresses. In another embodiment of the invention, data values which are provided to a non-tagged, n-way cache are written into the cache in a non-count form.

Abstract: A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.

Abstract: A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Abstract: A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit.

Abstract: A memory translation system which includes an “address cache” (addrcache). This address cache contains translation information of recently referenced addresses, and is accessed before the conventional two-level address translation process. If a hit is made in the address cache, which does not require protection checking, the conventional address translation process is bypassed. The address cache stores its memory addresses according to the protection status of each address, so that protection checking is not performed as a separate step.

Abstract: A flexible memory overlaying apparatus and method stores repeatedly referenced information, e.g, common global variables, common code segments, interrupt service routines, and/or any other user or system definable information, in spare addressable circuits accessed by a memory aliasing or overlaying module. The memory aliasing module monitors (or snoops) memory access by a processor to redirect access to certain appropriate addressable circuits to provide faster access to the information than would be available in an access made from main memory. The memory overlaying apparatus and method provides an efficient context switching, e.g., during an interrupt, enables a reduction in the size of instruction code requirements, and helps avoid the occurrences of cache misses, and/or thrashing between cached pages.

Abstract: A register interference state where a register which is updated by a preceding instruction is used by a succeeding instruction, for example, for the generation of an operand address, is detected. When a register interference state is detected, the execution of a succeedingly fetched instruction is started by storing an operand address generated when the succeeding instruction is executed in association with the address of the succeeding instruction. The operand address is estimated which corresponds to the address of the succeedingly fetched instruction and is retrieved from the stored contents.

Abstract: A memory system has a plurality of memory banks, performs interleaving between the memory banks, and structures a memory by dividing into a plurality of memory blocks which are independently operable. The memory system includes a first address conversion table and a second address conversion table. The first address conversion table is referred by an Operating System and is controllable by dividing an absolute address space into each unit memory capacity. The second address conversion table designates the memory bank and the memory block so that the memory bank and the memory block are commonly used between memory units which forms the interleaving to each other on the basis of an output value of the first address conversion table and the number of the interleaving.

Abstract: A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e.g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e.g. floating point, integer, flags, etc.), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource).

Abstract: Data transfers involving accesses of multiple banks of a DRAM having a shared sense amplifier architecture can be performed while also avoiding bank conflicts and associated data bus latency. Groups of DRAM banks which can be sequentially accessed during a given data transfer without conflicting with one another are identified and utilized for data transfers. Each data transfer sequentially accesses the banks of one of the groups. The sequence in which the banks of a given group will be accessed during a data transfer can advantageously be reordered in order to prevent conflicts with banks that have been or will be accessed during prior or subsequent data transfers. In this manner, consecutive data transfers, each involving accesses to multiple banks of a DRAM having a shared sense amplifier architecture, can be performed without any data bus latency between or within the transfers.

Abstract: A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction.

Abstract: The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system configuration to increase system operation flexibility and to isolate errors. A cell controller indexes into an address resolution table using the high-order part of a processor-specified address. A write protection flag specifies whether to permit write access from other cells. An attempt to write-access a cell inhibited for write access causes a logical circuit to output an access exception signal.

Abstract: A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked list and having neighboring nodes notify each other of changes in TLB entries.

Abstract: In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.

Abstract: When there are write accesses to user pages in a data processing system that are marked as write-protected in a translation memory, the method checks, after an interrupt request, a corresponding page table entry and also whether there is an access with system authorization. If there is an access with system authorization, the write-protection is temporarily dropped until an operating mode changes from the system to a user. In order for the write-protection to be subsequently restored, control bits are used as indicators that are used to declare entries in the translation memory affected by the system accesses to be declared invalid.

Abstract: The memory management system (20) includes a transform generator (22) capable of generating an address (28) and a confirmer (30) from a key. A controller (24) is connected to the transform generator (22) and sends the key to the transform generator (22) and receives the address (28) and the confirmer (30). A store (26) is connected to the controller (24) and has a plurality of addresses (28), each of the plurality of addresses (28) has a confirmer location (30), a forward pointer location (34), a primary flag (36), an allocated flag (38) and an association location (32).

Abstract: Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.

Abstract: A data buffer apparatus stores first data objects containing a plurality of first data items and second data objects containing one or more second data items in a number of different ways depending upon a mode of operation. The apparatus includes an encoder (1290) for rearranging the order of the first data items within the first data objects in accordance with first arranging mode, prior to storing in the buffer (1293). The apparatus also includes a decoder (1291) for rearranging the order of a plurality first data items read from the buffer, in accordance with a second arranging mode.

Abstract: A method of accessing information in a cache of a multithreaded system comprises providing a virtual address of an instruction to be accessed by a thread. Upon a cache miss, the physical address of the information is compared with the physical address of an instruction stored in the cache, and if they match, the instruction is accessed from the cache. Alternatively, the cache is searched for an entry having a virtual address which matches the instruction's virtual address, and having some indication of being associated with the accessing thread. Upon finding such an entry, the instruction is accessed from the cache. In addition, the instruction may be accessed from the cache upon finding a cache entry whose virtual address matches the instruction's virtual address, and which either has an address space matching the address space of the thread, or has an indication that the entry matches all address spaces.

Abstract: One embodiment of the present invention provides an apparatus that preserves ordering of memory requests distributed across multiple memory controllers. The apparatus includes a first memory controller containing a receiving circuit that is configured to receive a memory request that includes a source tag indicating a source from which the memory request originated. (For example, a source tag may identify a processor or a graphics accelerator.) The apparatus also includes a comparison circuit that compares the source tag with source tags for pending memory requests in a second memory controller to determine if the second memory controller contains any pending memory requests from the same source. Note that the source tags for the second memory controller are contained within a storage area in the first memory controller.

Abstract: One embodiment of the present invention provides a method for preserving ordering of memory requests distributed across multiple memory controllers. This method operates within a system that receives a memory request at a first memory controller. This memory request includes a source tag indicating a source from which the memory request originated. (For example, a source tag may identify a processor or a graphics accelerator.) Next, the system compares the source tag with source tags for pending memory requests in a second memory controller to determine if the second memory controller contains any pending memory requests from the same source. Note that the source tags for the second memory controller are stored within the first memory controller.

Abstract: A translation lookaside buffer for detecting and preventing conflicting virtual addresses from being stored therein is disclosed. Each entry in the buffer is associated with a switch which can be set and reset to enable and disable, respectively, a buffer entry. A switch associated with an existing entry will be reset if such entry conflicts with a new buffer entry.

Abstract: A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e.g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e.g. floating point, integer, flags, etc.), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource).

Abstract: One embodiment of the present invention provides a method for accessing a computer memory that bypasses decoding delays for memory type information within a memory controller. This method operates by receiving a current address, which specifies a location in the computer memory, and determining whether the current address falls within a previously accessed memory module. If so, the method receives characteristics of the previously accessed memory module from a prior decoding of a previous address to the previously accessed memory module. These characteristics may include information on size, type and speed of the modules in the computer memory. The method uses these characteristics to generate a memory access to the current address. In a variation on this embodiment, if the current address does not fall within the previously accessed memory module, the method decodes the current address to look up characteristics of a current memory module for the current address.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: In processor with multiple execution units and at least one instruction buffer the dispatch of instructions to available units is prioritised for multiple paths following a conditional branch. For example, instructions in the instruction buffer relating to a predicted path following a conditional branch can be dispatched to available execution units in preference to instructions relating to any other path, the instructions relating to any other paths being dispatched to any execution units remaining available. Compared to a processor with conventional predictive branch execution, prioritised dispatch of instructions in accordance with prediction priorities enables optimisation of the use of available execution units. There is a gain in efficiency where a non-predicted path proves to be the correct path without impacting efficiency where the predicted path proves to be the correct path. This net gain in efficiency can be achieved with a minimum of additional resources.

Abstract: A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The data store comprises a plurality of data blocks for holding data. The tag array comprises a plurality of tag entries corresponding to the data blocks, and both the data store and tag array are addressed with the cache index. The tag array provides a plurality of physical address tags corresponding to physical addresses of data resident within corresponding data blocks in the data store addressed by the cache index. The page translator translates a tag portion of the virtual address to a corresponding physical address tag.

Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

Abstract: A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.

Abstract: Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.

Abstract: A method and apparatus for detecting address range overlaps. According to one embodiment, a first mask is generated for a first address range and a second mask is generated for a second address range. A first AND operation is performed on the first address range and the second mask to output a first temporary value. A second AND operation is performed on the second address range and the first mask to output a second temporary value. The first temporary value is then compared to the second temporary value to detect an overlap between the first address range and the second address range. According to an alternate embodiment, a first mask is generated for a first address range and a second mask is generated for a second address range. The first mask is then compared to the second mask to detect an overlap between the first address range and the second address range.

Abstract: An apparatus is disclosed which supports memory updates within a data processing system including a number of processors. The apparatus includes a memory hierarchy including one or more upper levels of memory. Each upper level within the memory hierarchy includes one or more memory units which each store a subset of all data stored within an associated memory unit at a lower level of the memory hierarchy. Each memory unit at the highest level within the memory hierarchy is associated with a selected processor. In addition, the apparatus includes a reservation indicator associated with each memory unit within the memory hierarchy. For memory units at the highest level within the memory hierarchy, the reservation indicator specifies an address for which the processor associated with that memory unit holds a reservation. At each lower level within the memory hierarchy, the reservation indicator specifies addresses for which associated memory units at higher levels within the memory hierarchy hold a reservation.

Abstract: A novel processor for manipulating packed data. The packed data includes a first data element D1 and a second data element D2. Each of said data elements has a predetermined number of bits. The processor comprises a decoder, a register, and a circuit. The decoder is for decoding a control signal responsive to receiving the control signal. The register is coupled to the decoder. The register is for storing the packed data. The circuit is coupled to the decoder. The circuit is for generating a first result data element R1 and a second data element R2. The circuit is further for generating R1 to represent a total number bits set in D1, and the circuit is further for generating R2 to represent a total number bits set in D2.

Abstract: Apparatus for supporting virtual address aliasing is disclosed in which addresses to a virtual cache are first intercepted. It is determined whether the these addresses are aliased, i.e., more than one virtual address exists for the same location in memory. If not aliased, the addresses are simply passed to the virtual cache. In the case where there is aliasing, however, dealiasing is performed. New addresses are generated and passed to the virtual cache so that the aliased addresses are directed to the same locations in the virtual cache. In this way, an operating system can be supported that uses virtual address aliasing since the CPU can transparently issue aliased virtual addresses. These addresses, however, are directed to the same locations in the virtual cache so that the addresses are not aliased from the perspective of the cache, thus avoiding the need for other hardware to compensate for the aliasing. The modification, however, does not substantially impact latency.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.