Abstract: First firmware metadata and second firmware metadata are based on nonvolatile metadata stored in the nonvolatile memory device. A normal operation including a first management operation resulting in a change of the first firmware metadata and an access operation in which the nonvolatile memory device is accessed may be performed. A virtual operation is performed including a second management operation resulting in a change of the second firmware metadata and in which the access operation is not performed. Whether an error has occurred in the first firmware metadata is determined by comparing the change of the first firmware metadata resulting from the first management operation and the change of the second firmware metadata resulting from the second management operation. An error in the metadata may be monitored through the redundant performance of the management operation that results in the change of the metadata without a corresponding access to the nonvolatile memory device.

Abstract: Methods, apparatus, and processor-readable storage media for machine learning-based anomaly detection using time series decomposition are provided herein. An example computer-implemented method includes processing, via machine learning techniques pertaining to time series decomposition functions, a first set of historical time series data derived from multiple systems within an enterprise; generating, based on the processed data, one or more pairs of upper bounds and lower bounds directed to system metrics; identifying system anomalies attributed to one or more of the multiple systems within the enterprise by comparing a second set of historical time series data derived from the one or more systems against the one or more pairs of upper bounds and lower bounds; prioritizing, via machine learning techniques pertaining to weighting functions, the system anomalies; and outputting, in accordance with the prioritization, the system anomalies to a user within the enterprise.

Abstract: Various implementations described herein relate to systems and methods for managing selective erasure in a Solid-State Drive (SSD) including receiving a selective erase command corresponding to erasing valid and invalid data mapped to a logical address and in response to receiving the selective erase command, erasing blocks in which one or more pages mapped to the logical address are located based on a mapping table that maps the logical address to the one or more pages. Both valid data and invalid data may be physically stored in one or more pages.

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

Abstract: A process control system includes first type and second type controllers having different hardware architectures coupled together by a redundancy network for providing a controller pool. Primary application modules (AMs) are coupled to the controller platforms by a plant-wide network. The controller platforms are coupled by an input/output (I/O) mesh network to I/O devices to provide an I/O pool coupled to field devices coupled to processing equipment. A translating device translates states and values from one of the primary AMs running on a first type controller to generate a backup AM having an instruction set compatible with the second type controller. A controller application module orchestrator (CAMO) extends synchronization to the second type controller, makes the backup AM available to the second type controller, and then switches to utilize the second type controller as an active controller running the process.

Abstract: A boot Read-Only Memory (ROM) update method and a boot-up method of an embedded system are provided. The boot Read-Only Memory (ROM) update method of an embedded system including a memory and a ROM. The memory includes a user data area and a boot ROM area that includes a first area and a second area. The ROM copies a first boot code from the boot ROM area during boot-up. The boot ROM update method includes writing a second boot code to the second area in response to a first ROM update command. The second boot code includes a second boot ROM image and a second signature for the second boot ROM image. The method also includes verifying validity of the second signature and, if the second signature is valid, swapping the first area and the second area. The first boot code is disposed in the first area and includes a first boot ROM image and a first signature for the first boot ROM image.

Abstract: A method, computer program product, and computer system for setting a preferred alignment value to a size of an address space mapped by one or more root pages. An allocation request may be received for the address space. A binary buddy allocation scheme may be executed to allocate an extent for the allocation request based upon, at least in part, the preferred alignment value.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple logical units and a memory controller. The memory controller accesses the memory device and updates content of an activated count table in response to a command issued by a host device. One or more sub-regions to be activated are identified in the command. The activated count table includes a plurality of fields each recording an activated count associated with one sub-region. The memory controller updates content of the activated count table by increasing one or more activated counts associated with the one or more sub-regions identified in the command. The memory controller further selects at least one sub-region according to the content of the activated count table and performs a data rearrangement procedure to move data of the selected at least one sub-region to a first memory space having continuous physical addresses.

Abstract: Methods, systems, and devices for exclusion regions for host-side memory address translation are described. In some examples, a host system may be configured to identify regions of logical addresses to be excluded from operating according to logical-to-physical (L2P) address mapping by the host system (e.g., for access commands), including such techniques that may be associated a host performance boosting (HPB) functionality. The host system may signal an indication for a memory system to inhibit communication of L2P mapping table information to the host system for the identified regions, which may inhibit, suppress, or exclude HPB functionality for those identified regions. In some examples, the memory system may continue to support HPB functionality by communicating L2P mapping table information for other regions, such as regions of logical addresses that may be read relatively frequently or may otherwise benefit from address translation at the host system.

Abstract: A method for encrypting and decrypting data, that includes using an encryption key and an address associated with a memory device or a software instance. The method for encrypting and decrypting data may be performed by a hypervisor or by a configured processor. The method may include receiving a read or write request specifying an address; performing a first lookup, in an address mapping table, to identify a memory module address of a memory module associated with the address; performing a second lookup to identify an encryption key associated with the read or write request; generating a decryption or encryption request that includes the memory module address; and the encryption key; and sending the decryption or encryption request to the memory module.

Abstract: A method for offloading a lookup operation to a NAND offload apparatus, including receiving, by the NAND offload apparatus, a NAND read command from a key-value solid-state drive (KV SSD) NAND interface, wherein the NAND offload apparatus is connected between the KV SSD NAND interface and a NAND device using a NAND bus; determining whether the NAND read command includes an information element indicating an indirect read operation; based on the NAND read command including the information element, performing the indirect read operation by the NAND offload apparatus; and based on the NAND read command not including the information element: passing, by the NAND offload apparatus, the NAND read command to the NAND device through the NAND bus, and configuring, by the NAND offload apparatus, a switch an output gate to pass a response message from the NAND device to the KV SSD NAND interface.

Abstract: A technique for managing a metadata transaction log consolidates multiple mapping pointer changes that affect a single metadata block in a single transaction entry. The technique creates a data structure that identifies the mapping pointers in the metadata block that are changing, and stores the data structure in the transaction entry along with records that describe the individual mapping pointer changes.

Abstract: A multi-path input-output (MPIO) driver in a host server reduces host-copy migration data transmission rate based on decrease in foreground IO response time. A baseline foreground IO response time measured before commencement of the host-copy migration is compared with a reference foreground IO response time measured after commencement of the host-copy migration. Increase in the foreground IO response time, expressed as a percentage or time value, that satisfies a predetermined limit will trigger reduction of the host-copy migration data transmission rate. The reference foreground IO response time is repeatedly measured and updated each time the host-copy migration data transmission rate is decreased.

Abstract: A climate data intercomparison and analytics service application programming interface (CDIAS-API) includes a set of basic utilities configured to map calls from client applications to single service-side methods operating on one or more disparate climate reanalysis datasets by the climate data intercomparison and analytics service, a set of extended utilities comprising scripts that call on one or more of a set of canonical operations, and one or more basic utilities, and a collections reference model configured to provide semantic alignment of variable names, method alignment of statistical operations, and output data format consistency for operations across the one or more disparate climate reanalysis datasets.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller accesses the memory device and updates content of a read count table in response to a read command with at least one designated logical address issued by a host device. Each field of the read count table records a read count associated with one sub-region and the content of the read count table is updated by increasing the read count associated with the sub-region that the designated logical address belongs to. The memory controller selects at least one sub-region to be rearranged according to the content of the read count table and performs a data rearrangement procedure to move data of logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.

Abstract: A memory system having multiple address tables to translate logical addresses to physical addresses at different granularity levels is disclosed. For example, a first address table is associated with a first block size of translating logical addresses for accessing system files and application files; and a second address table is associated with a second block size of translating logical addresses for storing and/or retrieving data from an image sensor of a surveillance camera. A user interface can be used to access a configuration option to specify the second block size; and a user may indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size and thus configure the second address table for a partition to record the image or video files.

Abstract: Embodiments presented herein techniques for balancing a multidimensional set of resources of different types within a distributed resources system. Each host computer providing the resources publishes a status on current resource usage by guest clients. Upon identifying a local imbalance, the host computer determines a source workload to migrate to or from the resources container to minimize the variance in resource usage. Additionally, when placing a new resource workload, the host computer selects a resources container that minimizes the variance to further balance resource usage.

Abstract: A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

Abstract: An apparatus comprises address translation circuitry (70) to perform a translation of a virtual address (80) comprising a virtual tag portion (88) and a virtual address portion (86) into a physical address (82) comprising a physical tag portion (92) and a physical address portion (90). The address translation circuitry comprises address tag translation circuitry (72) to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.

Abstract: Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: Technologies and techniques for use by a data storage controller or similar device for throttling the delivery of completion entries pertaining to the execution of commands by a nonvolatile memory (NVM) device are provided. In an illustrative example, the data storage controller selectively throttles the delivery of completion entries to a host device using uniform delivery intervals to provide for stable delivery of completion entries to the host. In some examples, the throttling is achieved by storing new completion entries in a completion queue of the host while initially setting corresponding indicator bits within the completion entries (e.g. phase tags) to cause the host to ignore the new completion entries as though the new entries were old entries. Later, after a throttling delay interval, the indicator bits are inverted to allow the host to recognize and process the new completion entries. NVMe examples are provided.

Abstract: A data storage system includes a logical space having logical block addresses (LBAs) divided into non-overlapping LBA ranges, and a physical space having pairs of physical bands. The system also includes a map in which first successive alternate LBAs of each different one of the non-overlapping LBA ranges are mapped to successive adjacent physical blocks of a first physical band of each different pair of the pairs of physical bands, and second successive alternate LBAs of each different one of the non-overlapping LBA ranges are mapped to successive adjacent physical blocks of a second physical band of each different pair of the pairs of physical bands. A controller employs the map to concurrently read data from a first physical block of the first physical band of one pair of physical bands and from a first physical block of the second physical band of the same pair of physical bands.

Abstract: The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to generate a first prefetch request and a second prefetch request based on the demand access stream, to output the first prefetch request to a first translation lookaside buffer (TLB), and to output the second prefetch request to a second TLB that is different from the first TLB. The processor performs a first TLB lookup in the first TLB based on one of the demand access stream or the first prefetch request, and performs a second TLB lookup in the second TLB based on the second prefetch request.

Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.

Abstract: A computer-implemented method according to one embodiment includes identifying a first data set to be backed up, where the first data set is stored on a first storage volume; removing empty data tracks from the first data set to create an intermediary data set; storing the intermediary data set at a plurality of secondary storage volumes different from the first storage volume; and creating a backup data set for the first data set, utilizing the intermediary data set.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller updates content of a read count table in response to a read command with a transfer length greater than 1 for designating more than one logical address to be read. The read count table includes multiple fields recording a read count associated with one sub-region and content of the read count table is updated by increasing the read count(s) associated with the sub-region(s) that logical addresses designated in the read command belong to. The memory controller selects at least one sub-region according to the content of the read count table and performs a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.

Abstract: Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

Abstract: A method begins by a storage unit of a dispersed storage network (DSN) receiving access requests which include a logical DSN address and a storage function. The method continues with a first processing module of the storage unit performing logical to physical address conversions of logical DSN addresses of the access requests to physical addresses of a plurality of main memories. For a first access request of the access requests, the method continues with the first processing module identifying a first main memory based on the physical address resulting from the physical address conversion. The method continues with the first processing module identifying a first processing thread of a plurality of processing threads based on allocation of the plurality of processing threads to the plurality of main memories. The method continues with the first processing thread executing tasks of the first access request to fulfill the first access request.

Abstract: Storage can be allocated to workspaces in a ZFS-based environment. Workspaces can be associated with a workspace weightage. When a workspace is deployed on a client computing device, its workspace weightage can be used to determine an initial quota for a dataset to be created in a zpool for the workspace. The initial quota can be used to determine the size of the dataset. The workspace weightage may also be used to determine an expansion quota and a contraction quota that can be used to calculate the size of an expansion or contraction respectively. The use of workspace weightages and their associated quotas can ensure that the zpool is fairly shared by the various datasets that may be created therein for workspaces deployed on the client computing device.

Abstract: A number of data access operations is tracked where the data access operations are associated with each of a plurality of portions of a translation map. The translation map maps a plurality of logical block addresses to a plurality of physical block addresses of the memory device. A criterion to perform a garbage collection operation is determined to be satisfied. The garbage collection operation is to be performed on a block of the memory component. The block for performing the garbage collection operation is identified based on the number of data access operations associated with each of the plurality of portions of the translation map. The garbage collection operation is performed on the identified block.

Abstract: An indication is received from a storage device that an attempt to read a portion of data from a block of the storage device has failed. A command is transmitted to the storage device to perform a scan on data stored at the block comprising the portion of data to acquire failure information associated with a plurality of subsets of the data stored at the block. The failure information associated with the plurality of subsets of the data stored at the block is received from the storage device.

Abstract: An electronic device includes a peripheral device, a processor, an interrupt controller configured to manage interrupts generated by the peripheral device and the processor on the basis of a register, and a virtualizer, wherein the virtualizer may be configured to virtualize a portion of the processor and a portion of the at least one peripheral device to generate a first partition, generate first interrupt information corresponding to an interrupt usable in the first partition, generate first processor information corresponding to a portion of the processor usable in the first partition, check whether a configuration of the register is related to at least one of the first interrupt information and the first processor information when the register is configured by the first partition, and allow the configuration of the register when the configuration of the register is related to the at least one information.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may monitor, in a state in which an address mapping information corresponding to a target device capable of inputting and outputting data corresponding to a specific address is first address mapping information, a first performance pattern which is an performance pattern for the target device, input information on the first performance pattern to an artificial intelligence engine which analyzes the performance pattern based on an artificial intelligence model and outputs address mapping information for the target device, and remaps a second address mapping information, which is the address mapping information output by the artificial intelligence engine, into address mapping information corresponding to the target device.

Abstract: A method performed by a block-storage server, of storing data is described. The method includes (1) receiving, from a remote file server, data blocks to be written to persistent block storage managed by the block-storage server; (2) receiving, from the remote file server, metadata describing files to which the data blocks belong in a set of filesystems managed by the remote file server; and (3) selectively applying data reduction when storing the data blocks in the persistent block storage based, at least in part, on the received metadata. An apparatus, system, and computer program product for performing a similar method are also provided.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: Systems and methods for connection virtualization in data storage device arrays are described. A host connection identifier may be determined for a storage connection request. A target storage device and corresponding completion connection identifier may be determined for a storage command including the host connection identifier. A command tracker may be stored that associates the storage command with the host connection identifier and the completion connection identifier and the storage command may be sent to the processing queue associated with the completion connection identifier.

Abstract: Apparatuses for address expansion and methods of address expansion are disclosed. Memory region definitions are stored, each comprising attribute data relevant to a respective memory region. In response to reception of a first address a region identifier indicative of a memory region to which the first address belongs is provided. Cache storage stores data in association with an address tag and in response to a cache miss a data retrieval request is generated. Address expansion circuitry is responsive to the data retrieval request to initiate a lookup for attribute data relevant to the memory region to which the first address belongs. The address expansion circuitry expands the first address in dependence on a base address forming part of the attribute data to generate an expanded second address, wherein the expanded second address is part of greater address space than the first address.

Abstract: The subject technology receives a query plan corresponding to a query. The subject technology executes the query based at least in part on the query plan, the executing including: filtering a first set of files that are to be modified by a merge statement, performing a split operation to send information related to a second set of files to a scan set builder operation in a first portion of the query plan and scan back operation in a second portion of the query plan, performing the scan set builder operation to remove the second set of files from the first set of files, performing a table scan operation based on a third set of files, and performing a first union all operation to combine the first set of data with a second set of data as a first set of combined data.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set.

Abstract: A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

Abstract: Systems and methods enabling garbage collection operations and normal system operations concurrently. Concurrent operations are performed by configuring a similarity group to permit garbage collection and normal operations. This may include creating a new subgroup in a similarity group for write and deduplication purposes such that an impacted subgroup can be cleaned.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.

Abstract: A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to determine that a first allocation unit has a first portion occupying a first plurality of erase blocks and a second portion sharing a second erase block with a portion of a second allocation unit. The processing device is further to relocate data of the portion of the second allocation unit sharing the second erase block with the second portion of the first allocation unit to another erase block and in response to relocating the data of the portion of the second allocation unit, reclaim the first plurality of erase blocks and the second erase block.