Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
  • Patent number: 10725746
    Abstract: The disclosure describes methods and apparatus for quickly prototyping of a solution developed using one or more sensing devices (e.g., sensors), functional blocks, algorithm libraries, and customized logic. The methods produce firmware executable by a processor (e.g., a microcontroller) on an embedded device such as a development board, expansion board, or the like. By performing these methods on the apparatus described, a user is able to create a function prototype without having deep knowledge of the particular sensing device or any particular programming language. Prototypes developed as described herein enable the user to rapidly test ideas and develop sensing device proofs-of-concept. The solutions produced by the methods and apparatus improve the functioning of the sensor being prototyped and the operation of the embedded device where the sensor is integrated.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 28, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.
    Inventors: Mahesh Chowdhary, Miroslav Batek, Marian Louda
  • Patent number: 10712941
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving an access request for data in a first block of storage space in memory, and returning the data in the first block of storage space in response to the access request. An identifier at an end of the data in the first block of storage space is also located, and pointers included in a trailer appended to the identifier are used to identify additional blocks of storage space which include data having temporal locality with the data in the first block of storage space. The data in each of the identified additional blocks of storage space is further prepared for use.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gregory T. Kishi, Daniel I. Tan, Itzhack Goldberg, Shazad Naviwala
  • Patent number: 10700954
    Abstract: A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 30, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Douglas Benson Hunt, Jay Fleischman
  • Patent number: 10698835
    Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
  • Patent number: 10698814
    Abstract: A data storage device includes a memory device and a memory controller. The memory controller is coupled to the memory device and configured to access the memory device and establish a physical to logical address mapping table and a logical address section table. The logical address section table records statuses of a plurality of logical address sections. Each status is utilized to indicate whether the physical to logical address mapping table records any logical address that belongs to the corresponding logical address section. The logical address section table includes a plurality of section bits in a plurality of dimensions. When the memory controller receives a write command to write data of a first predetermined logical address, the memory controller determines the section bit of each dimension corresponding to the first predetermined logical address, and accordingly sets a corresponding digital value for each section bit.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: June 30, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Hsuan-Ping Lin, Chia-Chi Liang
  • Patent number: 10684600
    Abstract: A method for operating a controller is provided. Program code having internal controller functions is stored on the controller, the program code being equipped with at least one service function. A service configuration for the at least one service function is provided on the controller. The method includes; detecting, in the controller, the service configuration; and executing a service functionality in accordance with the service configuration when the at least one service function is invoked. The service configuration denotes at least one internal controller function which is executed as a service functionality of the corresponding at least one service function. The at least one service function, via the service configuration, provides at least one value for at least one argument of the at least one internal controller function in the controller and/or receives at least one return value of the at least one internal controller function.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 16, 2020
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventor: Thorsten Hufnagel
  • Patent number: 10678635
    Abstract: A system for managing memory resources related to boot, including a memory; a boot configuration circuit, configured to designate one or more memory regions as a first type or a second type, the first type requiring scrubbing before beginning system operation, and the second type permitting scrubbing after beginning system operation; one or more processors, configured to scrub the memory regions of the first type; define a first caching policy of one or more memory regions of the second type; and begin system operation before scrubbing memory regions of the second type.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 9, 2020
    Assignee: INTEL CORPORATION
    Inventors: Amit Aneja, Jorge Serratos Hernandez, Bruno Achauer
  • Patent number: 10671543
    Abstract: Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer, Stefanos Kaxiras
  • Patent number: 10631321
    Abstract: A user equipment (UE) receives downlink data using resource blocks in a wireless mobile communication system. The UE receives downlink control information including resource allocation information and downlink data mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the UE. A resource block pair includes a first resource block associated with a first time slot and a second resource block associated with a second time slot adjacent to the first time slot. The first and second resource blocks are allocated to the same frequency indices. A mapping between VRB pairs and PRB pairs exists such that frequency consecutive VRB pairs are mapped to non-frequency consecutive PRB pairs and that each resource block pair is split so there is a frequency gap between the first and second parts of the resource block pair.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 21, 2020
    Assignee: Optis Cellular Technology, LLC
    Inventors: Dong Youn Seo, Eun Sun Kim, Bong Hoe Kim, Joon Kui Ahn
  • Patent number: 10614433
    Abstract: A hybrid digital rights management (DRM) system includes a hybrid digital rights management server (RMS server) connected to first and second RMS servers and a client computer. The hybrid RMS server stores a policy mapping table that maps its DRM policies to remote DRM policies on the first or second RMS servers, and can also create policies that satisfy the schema requirements of the first or second RMS server using policies stored in the hybrid RMS server. When the hybrid RMS server receives a document protection request from the client computer, it extracts the filename extension for the document to be protected, and uses the filename extension to select one of the first and second RMS servers as a target RMS server. The document is protected by the target RMS server, and also added to a protected document database on the hybrid RMS server.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 7, 2020
    Assignee: KONICA MINOLTA LABORATORY U.S.A., INC.
    Inventors: Rabindra Pathak, Kyohei Shiraishi
  • Patent number: 10606488
    Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 31, 2020
    Assignee: INTEL CORPORATION
    Inventor: Sanjeev N. Trika
  • Patent number: 10592426
    Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 17, 2020
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventor: Wen-Cheng Chen
  • Patent number: 10579543
    Abstract: The present disclosure provides a method and electronic device for processing information. The method is applied in a solid state storage apparatus which is connected to an electronic device. The solid state storage apparatus supports N logical-address-to-physical-address mapping tables different from each other simultaneously, wherein N is an integer greater than or equal to 1. The method comprises: receiving identity information for a user from the electronic device; determining a first logical-address-to-physical-address mapping table corresponding to the user based on the identity information; and assigning the first logical-address-to-physical-address mapping table to the user.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 3, 2020
    Assignee: LENOVO (BEIJING) LIMITED
    Inventors: Jianwei Lu, Qi Guo
  • Patent number: 10581751
    Abstract: Embodiments are directed to a method of regulating client agent backup jobs in a backup server by defining a server parallelism value specifying a maximum number of active backup jobs that can be simultaneously performed by the backup server, maintaining a plurality of queues in memory and including an active queue storing active backup jobs comprising a number of current backup jobs not exceeding the server parallelism value, and one or more overflow queues storing backup jobs exceeding the server parallelism value, receiving backup job requests from a plurality of clients and processing the received backup job requests through the plurality of queues, and transmitting a hold command to the plurality of clients if the plurality of queues are full. The overflow queues may comprise a wait queue and a sleep queue.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 3, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sathayamoorthy Viswanathan, Ajith Gopinath, Gururaj Kulkarni
  • Patent number: 10581674
    Abstract: A method for expanding a high-availability server cluster is disclosed. The method includes configuring at least two nodes comprised in a server cluster to be expanded as one or more server units, each server unit consisting of at least two nodes; configuring a newly added node into the server cluster, and configuring the newly added node as at least one newly added server unit in the server cluster; and broadcasting routing information of the newly added server unit. The method realizes an expansion of a server cluster by adding a newly added server unit to the server cluster, i.e., increasing the number of server units in the server cluster, so that the number of sessions and processing performance of the expanded server cluster can be improved, with a relatively low expansion cost.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 3, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Xiaoping Zhu
  • Patent number: 10552270
    Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Eric J. DeHaemer, Arijit Biswas, Reid J. Riedlinger, Ian M. Steiner
  • Patent number: 10547683
    Abstract: Embodiments describe Object-based Storage Device (OSD) targets that utilize Remote Direct Memory Access (RDMA) to allow the OSD target to directly transfer objects requested by a host system to the memory of host system, thereby bypassing an OSD interface of the host system. One embodiment comprises an OSD target that includes an OSD manager, an RDMA manager, and a non-volatile storage device that stores an object. The OSD manager communicatively couples with an OSD interface of a first host system. The RDMA manager communicatively couples with at least one of a first RDMA interface of the first host system and a second RDMA interface of a second host system. The OSD manager receives an OSD command to retrieve the object from the OSD interface, locates the object at the non-volatile storage device, and provides the object to the RDMA manager. The RDMA manager provides the object to at least one of the first RDMA interface of the first host system and the second RDMA interface of the second host system.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 28, 2020
    Inventor: Christopher Squires
  • Patent number: 10545800
    Abstract: A technique for facilitating direct doorbell rings in a virtualized system is provided. A first device is configured to “ring” a “doorbell” of a second device, where both the first and second devices are not a host processor such as a central processing unit and are coupled to an interconnect fabric such as peripheral component interconnect express (“PCIe”). The first device is configured to ring the doorbell of the second device by writing to a doorbell address in a guest physical address space. For security reasons, a check block checks an offset portion of the doorbell address against a set of allowed doorbell addresses for doorbells specified in the guest physical address space, allowing the doorbell to be written if the doorbell is included in the set of allowed doorbell addresses.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 28, 2020
    Assignee: ATI Technologies ULC
    Inventors: Anthony Asaro, Gongxian Jeffrey Cheng
  • Patent number: 10545671
    Abstract: A method, computer program product, and computer system for receiving, at a computing device, an I/O request directed to a compressed data portion of a storage system. It may be determined whether the I/O request includes one of a first portion of information and a second portion of information. An address of the compressed data portion may be obtained via downward mapping if the I/O request includes the first portion of information. The address of the compressed data portion may be obtained via upward mapping if the I/O request includes the second portion of information. The I/O request may be executed at the compressed data portion.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 28, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Xiaohua Fan, Yaming Kuang, Walter Forrester
  • Patent number: 10540276
    Abstract: A data storage device includes a memory device, an SRAM and a controller. The memory device includes a first buffer configured to store data of a plurality of consecutive logical pages. The SRAM stores a first mapping table. The first mapping table records which logical page the data stored in each physical page of the first buffer directs to. The controller is coupled to the memory device and the SRAM. When the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished. The predetermined number (M) is a positive integer greater than 1.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Wen-Sheng Lin
  • Patent number: 10540175
    Abstract: A system, method, and computer program product is provided for migrating an application from a source computing environment having a source Operating System (OS) to a target computing environment, the target computing environment having a target OS. The method may include discovering applications and resources on the source computing environment; preparing a migration computing environment having the target OS based on the discovered applications and resources; instantiating a virtual migration sandbox in the migration computing environment; instantiating the application within the virtual migration sandbox; and, capturing in-process and out-of-process calls made by the application during execution; updating the migration computing environment based on the captured in-process and out-of-process calls.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 21, 2020
    Assignee: AppZero Software Corp.
    Inventors: Mark Woodward, Chuanbao (Robert) Wang, Mohammed Ahmed-Muhsin
  • Patent number: 10509602
    Abstract: A data storage device includes a nonvolatile memory device including a main map table, the main map table including a plurality of map segments; and a controller comprising a sub map table including only some of the plurality of map segments of the main map table, the controller is suitable for updating access frequencies for the respective map segments of the main map table; and for determining whether to erase a map segment of the sub map table based on the updated access frequencies for the respective map segments.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwang Jong Song
  • Patent number: 10503649
    Abstract: An integrated circuit (IC) is provided. The IC includes a cache memory and an address decoder. The cache memory is divided into a plurality of groups. The address decoder provides a physical address according to an access address. When the access address corresponds to a specific group of the groups of the cache memory, the address decoder changes the access address to provide the physical address, and when the access address corresponds to one of the groups other than the specific group in the cache memory, the address decoder assigns the access address as the physical address.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10504604
    Abstract: A memory device includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; a plurality of row circuits respectively arranged along the plurality of rows; a plurality of column circuits respectively arranged along the plurality of columns; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Jonathan Tsung-Yung Chang
  • Patent number: 10496474
    Abstract: A semiconductor storage device and a memory system having the same. The semiconductor storage device includes a memory array, an error checking/correction (ECC) element, and a setting element. The ECC element stores generated error correction codes to a storage area. The setting element can set the storage area from the external.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 3, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Takehiro Kaminaga
  • Patent number: 10474585
    Abstract: A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-min Lee
  • Patent number: 10459715
    Abstract: A semiconductor system comprises a nonvolatile memory storing a patch code, the patch code comprising a unique identifier (ID). An internal read only memory (IROM) stores a boot code, the boot code comprising a patch code execution function for executing the patch code and a linked register (LR) address for specifying a storage location where the patch code is to be executed. A static random access memory (SRAM) stores a copy of the patch code at the storage location, the copy of the patch code including the unique ID. A processor executes the copy of the patch code from the storage location. The processor executes the copy of the patch code stored at the storage location in the SRAM according to the comparison result.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Uk Park, Bong Chun Kang, Cheong Woo Lee, Hee Dong Shin
  • Patent number: 10452604
    Abstract: Embodiments of the present disclosure provide a method and bus for accessing a dynamic random access memory (DRAM). The embodiments include receiving an access instruction, where the access instruction includes an access address, the access address includes a physical address, and a first field and a second field that are additionally set, the first field is used to indicate an interleaving mode, the interleaving mode indicates a manner of selecting an access channel, the second field is used to indicate an interleaving granularity, and the interleaving granularity indicates a capacity of an address space corresponding to the access channel; determining, according to the first field and the second field, the access channel and an address corresponding to the access channel; and accessing the DRAM according to the access channel and the address corresponding to the access channel.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 22, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Liang, Hu Liu, Zhiqiang Zhang
  • Patent number: 10452575
    Abstract: A system, apparatus and method for ordering a sequence of processing transactions for a plurality of peripheral units. The sequence of transactions is accomplished by mapping an incoming address to a target endpoint. The ordering of the transactions is agnostic to the type of endpoint being targeted and only considers an identifier of the transaction for ordering purposes.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 22, 2019
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Mark David Werkheiser, Glenn Allan Canto, Ashok Kumar Tummala, Devi Sravanthi Yalamarthy
  • Patent number: 10445243
    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 15, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Cameron Buschardt, Sherry Cheung, James Leroy Deming, Samuel H. Duncan, Lucien Dunning, Robert George, Arvind Gopalakrishnan, Mark Hairgrove, Chenghuan Jia, John Mashey
  • Patent number: 10430189
    Abstract: An apparatus to facilitate register allocation is disclosed. The apparatus includes an execution unit (EU) to execute processing threads. The EU includes a plurality of registers and register allocation logic to map the plurality of registers into logical register banks and allocate the processing threads to one or more of the logical register banks.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Tomasz Janczak, Travis Schluessler, Subramaniam Maiyuran
  • Patent number: 10409763
    Abstract: Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Polychronis Xekalakis, Joshua B. Fryman, Allan D. Knies, Naveen Neelakantam, Gregor Stellpflug, John H. Kelm, Mirem Hyuseinova Seidahmedova, Demos Pavlou, Jaroslaw Topp
  • Patent number: 10402339
    Abstract: A method for managing metadata in a scale out storage system is disclosed. The system includes a plurality of nodes, a storage pool, first metadata that maps logical addresses of logical data blocks to corresponding content identifiers, and second metadata that maps content identifiers to corresponding physical addresses of physical data blocks in the storage pool and maintains a reference count. During an add-a-node operation, the processors are configured to move from the existing nodes to the new node some of its physical data blocks, their content identifiers and reference counts in the second metadata without accessing or altering the first metadata. A method is also disclosed to move a logical device from one node to another by de-activating the logical device's first metadata on the first node and activating and retrieving the logical device's first metadata on the second node.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: September 3, 2019
    Assignee: CACHEIO, LLC
    Inventors: Arthur James Beaverson, Bang Chang
  • Patent number: 10402317
    Abstract: A mapping information rebuilding technique for a flash memory is introduced. Mapping information of data that has been stored in the flash memory is recorded in a plurality of logically-grouped tables. System information blocks are provided to store the mapping information by using the logically-grouped table as a management unit. A grouping list is stored in at least one pre-defined physical address of each system information block to list logical group numbers of the logically-grouped tables stored in the physical pages of the corresponding system information blocks. In each system information block, more physical pages are used in storing the logically-grouped tables than are used in storing the grouping list.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 3, 2019
    Assignee: SILICON MOTION, INC.
    Inventor: Tao-En Tang
  • Patent number: 10394548
    Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 27, 2019
    Inventor: Zohar Fox
  • Patent number: 10379972
    Abstract: Systems and methods are disclosed for minimizing reads for reallocated sectors of a data storage medium. An apparatus may be configured to selectively skip over reallocated sectors in an LBA range without interrupting a read, via generating a skip mask or by beginning the read after the reallocated sector and reading the entire track up to the reallocated sector. When a number of sectors not read from the LBA range during the read operation is less than an amount of sectors that can be recovered based on an error correction capability, the data of the reallocated sector may be reconstructed using error correction data rather than by performing a read at the reallocated sector.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 13, 2019
    Assignee: Seagate Technology LLC
    Inventors: Deepak Sridhara, Ara Patapoutian, Prafulla B Reddy
  • Patent number: 10379958
    Abstract: Methods, storage facilities and computer software products implement embodiments of the present invention that include mapping, by a storage system including one or more storage devices, a set of storage blocks on a given storage device to a redo log file configured to store transactions performed by a transaction processing system. An archiving condition is specified, and upon the transaction processing system completing a given transaction a copy of the given transaction is stored to the redo log file. Upon the archiving condition being met, the storage system can remap the set of storage blocks to an archive log file.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 13, 2019
    Assignee: AXXANA (ISRAEL) LTD.
    Inventor: Alex Winokur
  • Patent number: 10353825
    Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
  • Patent number: 10353814
    Abstract: The present disclosure relates to a method and system for optimizing garbage collection in a storage device. In an embodiment, number of free pages, number of valid pages and number of invalid pages in each of one or more memory blocks in the storage device is determined by a memory management system. Further, at least one target memory block having minimum number of free pages, minimum number of valid pages and maximum number of invalid pages is identified among the one or more memory blocks. The step of determining the number of valid pages is iteratively repeated until the number of valid pages is less than or equal to the number of free pages in at least one of the one or more memory blocks. Finally, the at least one target memory block is recycled by the memory management system, thereby optimizing the garbage collection in the storage device.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: July 16, 2019
    Assignee: Wipro Limited
    Inventor: Manasa Ranjan Boitei
  • Patent number: 10353822
    Abstract: The described technology is directed towards efficiently invalidating cached data (e.g., expired data) in a hash-mapped cache, e.g., on a timed basis. As a result, data is able returned from the cache without checking for whether that data is expired, (if desired and acceptable), because if expired, the data is only briefly expired since the last invalidation run. To this end, a data structure such as a linked list is maintained to track information representative of hash-mapped cache locations of a hash-mapped cache, in which the information tracks a sequential order of entering data into each hash-mapped cache location. An invalidation run is performed on part of the hash mapped cache, including using the tracking information to invalidate a sequence of one or more cache locations, e.g., only the sequence of those locations that contain expired data.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 16, 2019
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Sata Busayarat
  • Patent number: 10346042
    Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 9, 2019
    Assignee: KOVE IP, LLC
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, John Overton, Andrew S. Poling, Jesse I. Taylor
  • Patent number: 10346095
    Abstract: A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES, LLC
    Inventors: Vikram Joshi, David Flynn, Yang Luan, Michael F. Brown
  • Patent number: 10318416
    Abstract: A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventor: Adam Jerome White
  • Patent number: 10318448
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Tidal Systems, Inc.
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Patent number: 10306006
    Abstract: A bio-inspired algorithm based P2P content caching method and system for mesh networks is provided. The bio-inspired algorithm based P2P content caching method for mesh networks includes the steps of checking a request of a content of a user in a mesh router, and searching the content from the mesh router, which is requested for the content, based on a bio-inspired algorithm.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: May 28, 2019
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jun Kyun Choi, Seung Hyun Jeon, Man Sun Park
  • Patent number: 10303619
    Abstract: A method and an apparatus for determining a physical address are disclosed. According to the present disclosure, a page size is obtained according to the higher-order N bits of a linear address, where N is greater than 0 and less than a quantity of bits of the linear address; an index number of a translation lookaside buffer TLB is obtained according to the page size; a mask is obtained according to the page size and a supported minimum page size; a label of the TLB is obtained according to the mask; the higher-order MAC1 bits of a physical address corresponding to the linear address are obtained by searching the TLB according to the index number and the label; and the physical address is obtained according to the mask, the supported minimum page, and the higher-order MAC1 bits of the physical address.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 28, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lixin Zhang, Ke Zhang, Yi Zhang, Lele Zhang
  • Patent number: 10303389
    Abstract: A device includes a data memory managed by a filing system configured to store data in respect of one or more clusters or blocks within the data memory. The device (10) is configured to assemble data content objects into a virtual container; store the virtual container and associated data content objects into one or more of the one or more clusters or blocks, wherein the data content objects are memory-aligned within the one or more clusters or blocks; and arrange for the data content objects to be individually accessible in their virtual container.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: May 28, 2019
    Assignee: GURULOGIC MICROSYSTEMS OY
    Inventors: Tuomas Kärkkäinen, Ossi Kalevo
  • Patent number: 10303616
    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 28, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Chenghuan Jia, John Mashey, Cameron Buschardt, Sherry Cheung, James Leroy Deming, Samuel H. Duncan, Lucien Dunning, Robert George, Arvind Gopalakrishnan, Mark Hairgrove
  • Patent number: 10303398
    Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 28, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Wuu, Michael K. Ciraula, Russell Schreiber, Samuel Naffziger
  • Patent number: 10261703
    Abstract: Sharing read-only data among virtual machines (VM) using an attached coherent accelerator processor interface (CAPI) enabled flash storage (CeFS) is provided. The method includes mapping a file, by a virtual machine monitor, from the CeFS into a range of common memory in the virtual machine monitor. The VM shares the mapped file with at least one other VM at a range of common memory in their address spaces. A redirect-on-write filesystem (RoWFS) is created on the VM and the at least one other VM, whereby the RoWFS includes a read-only copy and a private copy of a linear memory map of the mapped file. A data page is read using the copy of the linear memory map, and the data page is modified using the private copy of the linear memory map.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Anil Kumar K. Damodaran, Douglas Griffith, Amarendar N. Sulu