Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
  • Patent number: 11068258
    Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: July 20, 2021
    Assignee: Aurora Labs Ltd.
    Inventor: Zohar Fox
  • Patent number: 11061827
    Abstract: An aspect includes providing a metadata structure having a logical level that points to a virtual level and a physical level to which the virtual level points. The method also includes storing, at the virtual level, a reference counter for each of a plurality of virtual-level type storage address entries in the metadata structure, and providing a pointer in the metadata structure between each pair of a number of pairs of virtual level address entries in which corresponding pages share a set of common sectors. The reference counter tracks a number of instances in which a corresponding pointer points to a corresponding virtual level address entry. An aspect further includes storing a single instance of the common sectors at the physical level.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 13, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Alex Soukhman
  • Patent number: 11055216
    Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a request analyzer, a storage, and a garbage collection controller. The request analyzer generates invalid data information, based on an erase request received from a host. The storage stores a garbage collection reference table representing memory blocks excluded from selection as a victim block on which a garbage collection operation is to be performed, based on the invalid data information. The garbage collection controller controls the garbage collection operation on the semiconductor memory device, based on exclusion block information generated according to the garbage collection reference table.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Se Hyun Kim, Hui Jae Yu
  • Patent number: 11050436
    Abstract: A method, a system, and a computer program product for executing a database compression. A compressed string dictionary having a block size and a front coding bucket size is generated from a dataset. Front coding is applied to one or more buckets of strings in the dictionary having the front coding bucket size to generate one or more front coded buckets of strings. One or more portions of the generated front coded buckets of strings are concatenated to form one or more blocks having the block size. Each block is compressed. A set of compressed blocks is stored. The set of the compressed blocks stores all strings in the dataset.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 29, 2021
    Assignee: SAP SE
    Inventors: Robert Lasch, Ismail Oukid, Norman May
  • Patent number: 11016688
    Abstract: Disclosed is a distributed storage system and methods for providing real-time localized data access from different storage nodes of the distributed storage system. Providing the localized data access may include tracking access frequencies with which a file is directly accessed from the different storage nodes, storing a source copy of the file at the first storage node in response to the access frequency at the first storage node being greater than the access frequency at the other storage nodes, caching the file at a second storage node, transferring control over the source copy from the first storage node to a third storage node based on a change to the access frequencies, and validating the cached copy of the file at the second storage node against the source copy at the third storage node prior to responding to a request for the file from the second storage node.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 25, 2021
    Assignee: Open Drives LLC
    Inventors: Scot Gray, Sean Lee
  • Patent number: 11003524
    Abstract: A method of repairing an indirect addressing structure of a file system damaged by corruption of a virtual data block (VDB) mapping data stored in corresponding physical data blocks (PDBs) includes scanning PDB descriptors to identify PDBs storing data mapped by the corrupted VDB, where each identified PDB includes a set of PDB entries each having a backward pointer identifying a corresponding VDB entry of a corresponding VDB. The identified PDBs are scanned to identify PDB entries whose backward pointers refer to VDB entries of the corrupted VDB, then a replacement VDB is created by (1) for each of the identified PDB entries, recreating a corresponding VDB entry including a forward pointer to the identified PDB entry, and (2) incorporating the recreated VDB entries into the replacement VDB. The replacement VDB is then incorporated into the indirect addressing structure in place of the corrupted VDB.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 11, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Alexander S. Mathews, Rohit K. Chawla, Dixitkumar Patel, Soumyadeep Sen, Kumari Bijayalaxmi Nanda
  • Patent number: 11003588
    Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 11, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Sonu Arora, Paul Blinzer, Philip Ng, Nippon Harshadk Raval
  • Patent number: 10997199
    Abstract: Computer-implemented methods and systems are provided for managing databases. Consistent with disclosed embodiments, a database system can serve configuration requests received from administration systems using an active cluster of at least two geographically separated computing clusters. Serving configuration request can include updating an active configuration database of the active cluster based on the configuration request. The system can also serve search requests received from user devices that specify a search criterion using a closest one of the geographically separated computing clusters by retrieving items satisfying the search criterion from local copies of a cache replicated across the geographically separated computing clusters. Furthermore, the system can serve transaction requests received from the user devices using the active cluster by updating an active local copy of the cache replicated in the active cluster.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 4, 2021
    Assignee: Amadeus S.A.S.
    Inventor: Thibaud Nicolas Castaing
  • Patent number: 10997083
    Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 4, 2021
    Assignee: ARM Limited
    Inventors: Geoffrey Wyman Blake, Prakash S. Ramrakhyani, Andreas Lars Sandberg
  • Patent number: 10997093
    Abstract: A Non-Volatile Memory Express (NVMe) data reading/writing method and an NVMe device, where in the method, a transceiver receives an NVMe command from a host into a submission queue (SQ), an SQ control circuit sends the NVMe command in the SQ to an solid state drive (SSD) controller when detecting that the SQ in an SQ cache changes, the SSD controller executes the NVMe command, writes a generated NVMe command response into a completion queue (CQ) using a CQ control circuit, and instructs, by triggering an interrupt, the host to read the CQ such that the host processes the NVMe command response in the CQ. Because both the SQ and the CQ are located in the NVMe device, a central processing unit (CPU) can directly read the NVMe command response in the CQ or directly write the NVMe command into the SQ, thereby further reducing consumption of CPU resources.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 4, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Sheng Chang
  • Patent number: 10997085
    Abstract: A device compresses a mapping table in a flash translation layer of a SSD. The mapping table includes mappings between Logical Page Numbers (LPNs) and Physical Page Numbers (PPNs). A base PPN table stores at least one entry including a base PPN common to multiple LPNs. A PPN offset table stores an offset for each mapping. A set of hash functions are duplicated for each entry in the base PPN table. A bit extension unit adds bits to the respective offset in the PPN offset table to provide an extended offset bit. A hash calculator calculates a hash value using the base PPN and one of the hash functions corresponding to the base PPN. An exclusive OR unit outputs a new PNN for each of different LPNs, including the multiple LPNs, by applying an exclusive OR operation to the hash value and the extended offset bit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eri Ogawa, Takanori Ueda
  • Patent number: 10990384
    Abstract: In one embodiment, an apparatus includes: a control circuit to enable a comparison circuit based on a dynamic update to a hook table and a patch table; and the comparison circuit coupled to the control circuit to compare an address of a program counter to at least one address stored in the hook table, and in response to a match between the address of the program counter and the at least one address stored in the hook table, cause a jump from code stored in a read only memory to patch code stored in a patch storage. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 27, 2021
    Assignee: INTEL CORPORATION
    Inventors: Phani Kumar Nyshadham, Carsten Bendixen, Peter Kroon
  • Patent number: 10990524
    Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 27, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh
  • Patent number: 10992658
    Abstract: Techniques are disclosed for session control of a client-side native application that utilizes a browser for an authentication process. A login request from the browser is received in a proxy service, which scans the request for a URL redirecting back to the native application. The URL is modified to redirect the login request to a policy endpoint to determine if the request is allowed based on policy applied to the native application and browser. If the request is allowed, the policy endpoint restores the URL redirecting to the native application and bypasses the request to resume normal authentication flow. If the request is prohibited, a failure message is sent to the browser. Some implementations may include injection of browser detection code into the browser to determine which variant of the browser is used and sending the browser data regarding the variant to the policy endpoint for consideration in applying policy.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 27, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Itamar Azulay, Yossi Haber
  • Patent number: 10977186
    Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh, Michael G. Miller, Xiaoxiao Zhang, Jung Sheng Hoei
  • Patent number: 10977038
    Abstract: A processing apparatus supporting register renaming is provided with checkpoint circuitry to capture register mapping checkpoints indicative of speculative register mappings between logical registers and physical registers at a given point of speculative execution, and register group tracking circuitry to maintain tracking information for groups of logical registers. The tracking information for a given group indicates whether the given group is a changed group comprising at least one logical register for which a corresponding speculative register mapping has changed since a last checkpoint was captured, or an unchanged group for which none of the logical registers in that group have had their speculative register mappings changed since the last checkpoint was captured. When capturing a new register mapping checkpoint, unchanged groups of logical registers are excluded from the new register mapping checkpoint. This can save power in a register mapping checkpointing scheme.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 13, 2021
    Assignee: Arm Limited
    Inventor: William Elton Burky
  • Patent number: 10970001
    Abstract: A memory controller controls an operation of a memory device including a plurality of planes, based on a request from a host. The memory controller includes a request storage unit and a request controller. The request storage unit stores a plurality of read requests received from the host. The request controller controls the request storage unit to perform a processing operation for a read request that has been map-cache-hit, more preferentially than a pairing operation for multi-plane reading, based on whether the plurality of read requests have been map-cache-hit.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10956332
    Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William L. Walker, Michael L. Golden, Marius Evers
  • Patent number: 10942848
    Abstract: A memory system includes a memory device including plural memory blocks storing plural pieces of data classified by a first attribute and a second attribute different from the first attribute, and a controller configured to determine whether each data stored in each page in a first part of a target memory block for garbage collection in the memory device has either the first attribute or the second attribute, to determine that all data stored in a second part of the memory block has one of the first attribute and the second attribute, based on a first attribute page count of the memory block and the number of pages storing data of the first attribute in the first part of the memory block, and to migrate data having one of the first attribute and the second attribute to another memory block.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10929123
    Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: February 23, 2021
    Assignee: Aurora Labs Ltd.
    Inventor: Zohar Fox
  • Patent number: 10922027
    Abstract: There is disclosed techniques for use in managing data storage in storage systems. For example, in one embodiment, there is disclosed a method comprising receiving a request to store data of a data object in a storage system. The method also comprising determining that at least a portion of the data is to be stored in an uncompressed format in the storage system in response to receiving the request. The method also comprising storing at least a portion of the data in the uncompressed format in an allocation unit of a segment in the storage system such that the stored data in the uncompressed format emulates stored data in a compressed format based on the said determination.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: February 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Ivan Bassov, John Didier, Ajay Karri
  • Patent number: 10915467
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Patent number: 10917906
    Abstract: A user equipment (UE) receives downlink data using resource blocks in a wireless mobile communication system. The UE receives downlink control information including resource allocation information and downlink data mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the UE. Indexes of the PRBs to which the downlink data are mapped are determined based on a mapping relationship between virtual resource blocks (VRBs) and the PRBs. The mapping relationship is defined based on indexes of the VRBs which are mapped to the indexes of the PRBs for a first slot of a subframe and a second slot of the subframe. The indexes of the PRBs for the second slot are shifted with respect to the indexes of the PRBs for the first slot based on a predetermined gap. The mapping relationship includes a transformation of VRB indexes based on a matrix.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 9, 2021
    Assignee: Optis Cellular Technology, LLC
    Inventors: Dong Youn Seo, Eun Sun Kim, Bong Hoe Kim, Joon Kui Ahn
  • Patent number: 10909066
    Abstract: Distributed computing systems, devices, and associated methods of virtual RDMA switching are disclosed herein. In one embodiment, a method includes intercepting a command from an application in a container to establish an RDMA connection with a remote container on a virtual network. In response to the intercepted command, an RDMA endpoint at a physical NIC of a server is created. The method can also include intercepting another command to pair with a remote RDMA endpoint corresponding to the remote container. The intercepted another command contains data representing a routable network address of the remote RDMA endpoint in the RDMA computer network. Then, the RDMA endpoint created at the physical NIC of the server can be paired with the remote RDMA endpoint using the routable network address of the remote RDMA endpoint.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yibo Zhu, Jitendra D. Padhye, Hongqiang Liu
  • Patent number: 10896125
    Abstract: Methods and systems are provided for performing a garbage collection scheme for hybrid address mapping. A controller of a memory system receives data and a logical address for the data from a host device, writes the data in a page of an open log block and performs a garbage collection on a log block and under a certain condition, one or more data blocks, when the open log block is full.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Yu Cai, Fan Zhang
  • Patent number: 10891184
    Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 12, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ken-Hui Chen, Kuen-Long Chang, Yi-Fan Chang
  • Patent number: 10891201
    Abstract: Automated Tiered Storage (ATS) has become widely accepted technique in IT industry. Since IO data has different data densities on storage systems, higher storage capacity and improved performance can be achieved by combining two or more storage device tiers having different performance and cost characteristics. These multiple different storage device tiers can be combined into one automated storage pool, which automatically chooses optimal data placement for achieving both the highest performance and the lowest cost. When the storage device tier information can be stored as metadata for each of the data chunks. When there is a system failure and data needs to recovered, the device tier information metadata can be used to restore data to the predetermined optimum storage device tier of the ATS system which shortens the post-recovery warm-up time.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vitaly Kozlovsky, Alexander Shadrin, Denis Serov, Inga Petryaevskaya
  • Patent number: 10884752
    Abstract: A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Gregory W. Alexander, Dung Q. Nguyen
  • Patent number: 10877687
    Abstract: A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fulvio Rori, Giuseppe Cariello
  • Patent number: 10877900
    Abstract: A method and memory apparatus that operate to minimize and limit memory initialization time when powering up after an unexpected shutdown. Instead of relying only on a cached log table that is lost when memory powers down unexpectedly, the method and apparatus disclosed herein preserve the information needed to rebuild the log table within predefined memory locations. These predefined locations are optimized such that parallel sensing will capture initialization information for a certain number of word lines across all dies and planes within the memory structure during a single read operation at power up.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 29, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Ramanathan Muthiah
  • Patent number: 10871976
    Abstract: The present disclosure provide a method and an apparatus for identifying hotspot intermediate code.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 22, 2020
    Assignee: HUAWEI TECHNOLOGIES CO, LTD.
    Inventors: Mingliang Yi, Long Chen
  • Patent number: 10866746
    Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 15, 2020
    Assignee: SILICON MOTION INC.
    Inventor: Chao-Kuei Hsieh
  • Patent number: 10866930
    Abstract: Systems and methods for migrating locking data for a file system object within a distributed file system. An example method may comprise: initiating a transfer of locking data from a first node of a distributed file system to a second node of the distributed file system, wherein the locking data is associated with a file system object and comprises a connection identifier indicating a connection between a client requesting a lock and the first node; constructing a modified connection identifier that indicates a connection between the client and the second node; and updating the second node to include the locking data with the modified connection identifier.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 15, 2020
    Assignee: Red Hat, Inc.
    Inventors: Raghavendra Gowdappa, Pranith Kumar Karampuri
  • Patent number: 10866903
    Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 15, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Jiyun-Wei Lin
  • Patent number: 10866742
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for archiving storage volume snapshots. An archive module determines at least one snapshot or point in time copy of data. A metadata module determines metadata for restoring a snapshot or point in time copy. A storage module replicates a snapshot or point in time copy and stores the replicated snapshot or point in time copy and metadata to a target storage location, such as one or more data files in a file system of one or more storage devices from a different vendor than a storage device from which the data was copied. In another embodiment, both the ability to archive a storage volume snapshot and restore a previously archived storage volume snapshot is provided.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: December 15, 2020
    Assignee: NEXGEN STORAGE, INC.
    Inventors: John A. Patterson, Sebastian P. Sobolewski
  • Patent number: 10853325
    Abstract: Techniques for determining data reduction options may include: receiving first data reduction information regarding compression and deduplication of chunks of a data set; determining, in accordance with the first data reduction information for the data set, first settings denoting whether compression and deduplication are enabled or disabled for the data set; receiving, during a first time period when the first settings are effective, writes directed to the data set; receiving second data reduction information regarding compression and deduplication of chunks of the data set modified by writes during the first time period; and determining, in accordance with the second plurality of data reduction statistics for the data set, second settings denoting whether compression and deduplication are enabled or disabled for the data set.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: December 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sorin Faibish, Ronald A. Miller, II, James M. Pedone, Jr., Ivan Bassov
  • Patent number: 10853323
    Abstract: A client identifies a first data unit to be shared from a first file to a second file and sends an operation to copy that indicates the first data unit to be shared. The operation to copy the first data unit from the first file to the second file is received. In response to receiving the operation to copy the first data unit from the first file to the second file, it is determined whether the first data unit can be shared with the second file. In response to determining that the first data unit cannot be shared with the second file, the first data unit is copied to the second file. In response to determining that the first data unit can be shared with the second file, the first data unit is shared between the first file and the second file.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 1, 2020
    Assignee: NetApp Inc.
    Inventors: Sisir Shekhar, Akshatha Gangadharaiah, Saravana Selvarai
  • Patent number: 10853265
    Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 1, 2020
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, James Tringali
  • Patent number: 10838777
    Abstract: This application discloses a resource allocation method, an allocation node, and an access node. The method includes: receiving a service request message sent by an access node, the service request message from the access node indicating a to-be-processed service in the access node, and obtaining work queue status information of a resource node. The method further includes allocating, according to the service request message and the work queue status information, the to-be-processed service to a resource node; receiving allocation, by the access node, of a resource node for the to-be-processed service and generating an allocation result; and sending the allocation result to the access node. The access node further sends a task request to the allocated resource node according to the allocation result.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 17, 2020
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Kezhou Yan, Yaqing Li
  • Patent number: 10839090
    Abstract: A method, apparatus, computer-readable medium, and/or system described herein may be used to efficiently store, move, and/or process data across a plurality of computing clusters. For example, a computing device may receive an indication of one or more data storage locations within a first cluster of servers and/or an indication of one or more data storage locations within a second cluster of servers. The computing device may generate a data file comprising the indication of the one or more data storage locations within the first cluster of servers and/or the indication of one or more data storage locations within the second cluster of servers. Based on the generated data file, the computing device may generate a job to move data stored at the one or more data storage locations within the first cluster of servers to the one or more data storage locations within the second cluster of servers. Based on the job, the computing device may transmit, e.g.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 17, 2020
    Assignee: Bank of America Corporation
    Inventors: Sitaram C. Yarlagadda, Vijaya M. Anusuri
  • Patent number: 10838860
    Abstract: Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Michael V. DeBole, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10831655
    Abstract: Methods, devices and systems for a compressor and a decompressor for encoding and decoding data in the cache/memory/data transferring subsystem in a computer system or in a communication network are described herein. Example variable-length compressors and decompressors are able to: compress more densely when specific values occur in specific positions in a data block; to improve compression and decompression latency when specific values that appear frequently occur in a data block; to also improve decompression latency by recording the lengths of variable-length encoded values of a compressed data block. The compressor and decompressor are able to support compression and decompression of common compression scenarios that are used in combination with variable-length compression to improve compressibility in the cache/memory/data transferring subsystem in a computer system or in a communication network.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 10, 2020
    Assignee: ZEROPOINT TECHNOLOGIES AB
    Inventors: Angelos Arelakis, Per Stenström
  • Patent number: 10831672
    Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc
    Inventor: Dean A. Klein
  • Patent number: 10831669
    Abstract: Systems, methods and computer program products using multi-tag storage to enable efficient data compression in caches without increasing a tag/data area overhead. One method can comprise storing compressed versions of data elements in a data array of a cache, with tags for the compressed versions respectively appended to the compressed versions as stored in the data array, and storing hashed versions of the tags in a tag array of the cache, wherein the hashed versions of the tags respectively have fewer bits than the tags. A tag block may store hashed versions of tags corresponding to first and second compressed data elements stored in a cacheline of the cache. Hashed tag entries may be compared with full versions of the tags appended to compressed versions of data elements stored in the data array to prevent false positive cache reads. A compressed identifier (CID) may be stored with the hashed versions of tags in the tag array.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prashant Jayaprakash Nair, Seokin Hong, Alper Buyuktosunoglu, Michael B. Healy, Bulent Abali
  • Patent number: 10824512
    Abstract: A storage system in one embodiment comprises a storage controller and a plurality of storage devices comprising a plurality of memory portions. The storage controller is configured to monitor a plurality of servers for a failure event. The servers store a plurality of copies of the memory portions. The storage controller is further configured to mark as invalid a copy of a memory portion on a failed server, search for and identify a location on an operational server for storing a new version of the copy, and communicate the copy invalidity and the identified location to a client device using the memory portion. The client device is configured to generate the new version of the copy for storage on the operational server, and the storage controller receives a notification from the client device regarding whether the new version of the copy was generated and stored on the operational server.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 3, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Inna Resnik, Zvi Schneider, Dani Shemesh
  • Patent number: 10817206
    Abstract: A method, computer program product, and computing system for identifying one or more first layer metadata blocks that map to one or more second layer metadata blocks. A subset of the second layer metadata blocks that map to another second layer metadata block from the one or more second layer metadata blocks may be identified, thus defining one or more redirecting second layer metadata blocks. For each first layer metadata block of the one or more first layer metadata blocks: One or more first layer metadata blocks that map to the one or more redirecting second layer metadata blocks may be determined and the one or more first layer metadata blocks that map to the one or more redirecting second layer metadata blocks may be remapped to map to a target second layer metadata block.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 27, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Alex Soukhman, Vladimir Shveidel, Uri Shabi, Ronen Gazit
  • Patent number: 10817332
    Abstract: The present invention provides a method for managing dynamic memory between a host operating system and a guest operating system in an electronic device for executing a multi-operating system. A method for managing dynamic memory enables, with respect to the available memory state of a host operating system and a guest operating system, direct determination of transmission of guest operating system memory to the host operating system by the guest operating system and recovery of the transmitted memory to the guest operating system and enables a request for execution to the host operating system. Moreover, with respect to memory availability state information of the guest operating system, memory information of the host operating system can be collected at a designated collecting interval by means of a request to the host operating system. Also, the host operating system can allocate dynamic memory of the guest operating system with respect to a request from the guest operating system.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bok-deuk Jeong, Sung-min Lee
  • Patent number: 10810030
    Abstract: In one embodiment, a system includes host machines that form elements of the virtualization environment, and that include a hypervisor, a user virtual machine (UVM), a connection agent, and an I/O controller. The system further includes a virtual disk comprising a plurality of storage devices, the virtual disk being accessible by all of the I/O controllers. At least one of host machines receives a request associated with one of the elements using an application programming interface (API), and including a context-specific identifier. The host machine determines, using reflection, a type of the context-specific identifier and processes the request based on a mapping, according to the determined type, from the context-specific identifier to a unique identifier associated with the element.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 20, 2020
    Assignee: NUTANIX, INC.
    Inventors: Akshay Deodhar, Binny Sher Gill, Venkata Vamsi Krishna Kothuri
  • Patent number: 10809932
    Abstract: A method is used in managing data relocations in storage systems. A request is received to relocate a file system block of a file of a file system. The file includes a set of file system blocks. A determination is made as to whether the file system block has been identified for performing an operation on the file system block. The operation impacts the determination of whether to skip relocating of the file system block. Based on the determination, updating mapping information of the file system block is avoided upon relocation of the file system block.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Feng Zhang, Alexander S. Mathews
  • Patent number: 10809939
    Abstract: Embodiments of the present disclosure relate to a system, a computer program product and a method for synchronizing data between a source disk and a target disk in a cluster by performing synchronization between a source disk and a target disk, the synchronization being performed while a plurality of application I/Os on a plurality of nodes in a cluster are configured to access the source disk; and wherein a coordinator and a plurality of workers in the cluster are configured to manage copying data from the source disk to the target disk.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vadim Agarkov, Sergey Storozhevjkh, Maksim Vazhenin, Ilya Volzhev, Michael E. Bappe