Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
  • Patent number: 10353825
    Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
  • Patent number: 10353814
    Abstract: The present disclosure relates to a method and system for optimizing garbage collection in a storage device. In an embodiment, number of free pages, number of valid pages and number of invalid pages in each of one or more memory blocks in the storage device is determined by a memory management system. Further, at least one target memory block having minimum number of free pages, minimum number of valid pages and maximum number of invalid pages is identified among the one or more memory blocks. The step of determining the number of valid pages is iteratively repeated until the number of valid pages is less than or equal to the number of free pages in at least one of the one or more memory blocks. Finally, the at least one target memory block is recycled by the memory management system, thereby optimizing the garbage collection in the storage device.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: July 16, 2019
    Assignee: Wipro Limited
    Inventor: Manasa Ranjan Boitei
  • Patent number: 10353822
    Abstract: The described technology is directed towards efficiently invalidating cached data (e.g., expired data) in a hash-mapped cache, e.g., on a timed basis. As a result, data is able returned from the cache without checking for whether that data is expired, (if desired and acceptable), because if expired, the data is only briefly expired since the last invalidation run. To this end, a data structure such as a linked list is maintained to track information representative of hash-mapped cache locations of a hash-mapped cache, in which the information tracks a sequential order of entering data into each hash-mapped cache location. An invalidation run is performed on part of the hash mapped cache, including using the tracking information to invalidate a sequence of one or more cache locations, e.g., only the sequence of those locations that contain expired data.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 16, 2019
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Sata Busayarat
  • Patent number: 10346095
    Abstract: A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES, LLC
    Inventors: Vikram Joshi, David Flynn, Yang Luan, Michael F. Brown
  • Patent number: 10346042
    Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 9, 2019
    Assignee: KOVE IP, LLC
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, John Overton, Andrew S. Poling, Jesse I. Taylor
  • Patent number: 10318416
    Abstract: A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventor: Adam Jerome White
  • Patent number: 10318448
    Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Tidal Systems, Inc.
    Inventors: Michael Ou, Jerry Wang, Meng Kun Lee
  • Patent number: 10303398
    Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 28, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Wuu, Michael K. Ciraula, Russell Schreiber, Samuel Naffziger
  • Patent number: 10303616
    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 28, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Chenghuan Jia, John Mashey, Cameron Buschardt, Sherry Cheung, James Leroy Deming, Samuel H. Duncan, Lucien Dunning, Robert George, Arvind Gopalakrishnan, Mark Hairgrove
  • Patent number: 10303389
    Abstract: A device includes a data memory managed by a filing system configured to store data in respect of one or more clusters or blocks within the data memory. The device (10) is configured to assemble data content objects into a virtual container; store the virtual container and associated data content objects into one or more of the one or more clusters or blocks, wherein the data content objects are memory-aligned within the one or more clusters or blocks; and arrange for the data content objects to be individually accessible in their virtual container.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: May 28, 2019
    Assignee: GURULOGIC MICROSYSTEMS OY
    Inventors: Tuomas Kärkkäinen, Ossi Kalevo
  • Patent number: 10306006
    Abstract: A bio-inspired algorithm based P2P content caching method and system for mesh networks is provided. The bio-inspired algorithm based P2P content caching method for mesh networks includes the steps of checking a request of a content of a user in a mesh router, and searching the content from the mesh router, which is requested for the content, based on a bio-inspired algorithm.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: May 28, 2019
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jun Kyun Choi, Seung Hyun Jeon, Man Sun Park
  • Patent number: 10303619
    Abstract: A method and an apparatus for determining a physical address are disclosed. According to the present disclosure, a page size is obtained according to the higher-order N bits of a linear address, where N is greater than 0 and less than a quantity of bits of the linear address; an index number of a translation lookaside buffer TLB is obtained according to the page size; a mask is obtained according to the page size and a supported minimum page size; a label of the TLB is obtained according to the mask; the higher-order MAC1 bits of a physical address corresponding to the linear address are obtained by searching the TLB according to the index number and the label; and the physical address is obtained according to the mask, the supported minimum page, and the higher-order MAC1 bits of the physical address.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 28, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lixin Zhang, Ke Zhang, Yi Zhang, Lele Zhang
  • Patent number: 10261703
    Abstract: Sharing read-only data among virtual machines (VM) using an attached coherent accelerator processor interface (CAPI) enabled flash storage (CeFS) is provided. The method includes mapping a file, by a virtual machine monitor, from the CeFS into a range of common memory in the virtual machine monitor. The VM shares the mapped file with at least one other VM at a range of common memory in their address spaces. A redirect-on-write filesystem (RoWFS) is created on the VM and the at least one other VM, whereby the RoWFS includes a read-only copy and a private copy of a linear memory map of the mapped file. A data page is read using the copy of the linear memory map, and the data page is modified using the private copy of the linear memory map.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Anil Kumar K. Damodaran, Douglas Griffith, Amarendar N. Sulu
  • Patent number: 10261820
    Abstract: Methods, systems, and computer program products are included for de-duplicating one or more memory pages. A method includes receiving, by a hypervisor, a list of read-only memory page hints from a guest running on a virtual machine. The list of read-only memory page hints specifies a first memory page marked as writeable. The method also includes determining whether the first memory page matches a second memory page. In response to a determination that the first memory page matches the second memory page, the hypervisor may deduplicate the first and second memory pages.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 16, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Uri Lublin
  • Patent number: 10230684
    Abstract: A method, an apparatus, and an edge node controller for selecting an edge node. The edge node controller receives a service request message including a subscriber identifier; obtains the subscriber identifier in the service request message; queries a first mapping relationship between the subscriber identifier and an edge node address according to the subscriber identifier to obtain an edge node address corresponding to the subscriber identifier; and returns a service response message including the edge node address. A subscriber identifier carried in a service request message is used to query a first mapping relationship to obtain an edge node address, and a service response message carrying an address of an edge node selected for a subscriber is delivered, thereby reducing a processing process of identifying different edge nodes by an external server, improving the processing efficiency, and reducing the implementation complexity.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 12, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Ruobin Zheng
  • Patent number: 10228991
    Abstract: Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems is disclosed. In this regard, in one aspect, a memory system provides a memory management unit (MMU) and multiple hierarchical page tables, each comprising multiple page table entries comprising corresponding translation preference indicators. The memory system further includes a TLB comprising multiple TLB entries each configured to cache a page table entry. The MMU determines whether a TLB conflict exists between a first TLB entry caching a first page table entry comprising a translation preference indicator that is set and a second TLB entry caching a second page table entry comprising a translation preference indicator that is not set. If so, the MMU selects the first TLB entry for use in a virtual-to-physical address translation operation, based on the translation preference indicator of the first page table entry cached by the first TLB entry being set.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 12, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Samar Asbe, Thomas Philip Speier
  • Patent number: 10223111
    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Seth Abraham, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Zeev Sperber, Amit Gradstein
  • Patent number: 10223214
    Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Timothy J. Slegel
  • Patent number: 10216641
    Abstract: Aspects include a computer-implemented method for managing alias devices across logical control units. Aspects include establishing one or more alias management groups associated with a set of one or more logical control units. Aspects also include responsive to one or more changes to the set of network paths of a first logical control unit in the set of logical control units performing a method comprising: marking a first alias management group associated with the first logical control unit as invalid for alias borrowing. Then, performing a first synchronized CPU enablement operation that ensures each of the plurality of CPUs has enabled. Aspects include determining whether a second alias management group exists having a second set of control units that matches the set of paths of the first control unit and associating the first control unit with the second alias management group.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS SYSTEMS CORPORATION
    Inventors: Scott B. Compton, Tri M. Hoang, Stephen M. Kocik, Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10216578
    Abstract: A data storage device includes a nonvolatile memory arranged in drives and stripes, a buffer storing state information for each of the stripes, and a memory controller including a redundant array of independent disks (RAID) controller that operates in a spare region mode and performs data recovery using garbage collection based on the state information. The state information includes a first state indicating that none of the drives has malfunctioned, a second state indicating one of the drives has malfunctioned, and a third state indicating that data/parity stored in a malfunctioning drive has been recovered.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju Pyung Lee
  • Patent number: 10203893
    Abstract: Technologies are disclosed herein that allow for utilization of memory channel storage (“MCS”) devices in a computing system. The MCS device may be detected during a boot phase of the computing system, and the address data for the MCS device may be detected through repeated manipulation of a logical offset. The address data may then be stored for later use in memory allocation.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 12, 2019
    Assignee: American Megatrends, Inc.
    Inventors: Senthamizhsey Subramanian, Bejean David Mosher
  • Patent number: 10180909
    Abstract: A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes resetting the one or more indicators to indicate that the block of memory is no longer being used by the guest control program to back the address translation structure.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind
  • Patent number: 10168943
    Abstract: A computer-implemented method for determining correct devices to use in a mass volume migration environment includes reading an I/O configuration definition for a plurality of devices in the mass volume migration environment and definition of a second set of the plurality of devices, wherein the plurality of devices comprise a first set of the plurality of devices. The method includes executing a migration and annotating the first set and the second set with status identifiers. The method also includes responsive to completing a migration of a device in the first set to the associated corresponding device in the second set, updating the annotation of the migrated device in the first set and the corresponding device in the second set and swapping the migrated device in the first set with the corresponding device in the second set, and continuing the migration of devices of the first set to the second set.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Scott B. Compton, Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10152430
    Abstract: A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: David M. Durham, Baiju Patel
  • Patent number: 10152258
    Abstract: Disclosed herein are system, method, and computer program product embodiments for of big block allocation of persistent main memory. An embodiment operates by receiving an allocation request for memory of a requested size. A free memory block, that exceeds the requested size by a remainder and is available for allocation, is determined. A size of the free memory block is updated to indicate that the size of the free memory block is equal to the remainder size. A new block of the requested size is inserted with an indication that the new block is allocated. A memory address corresponding to the new block is returned.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 11, 2018
    Assignee: SAP SE
    Inventors: Ismail Oukid, Daniel Booss
  • Patent number: 10146699
    Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 4, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Mark David Lillibridge, Paolo Faraboschi
  • Patent number: 10133647
    Abstract: A method of operating a computer system in an operating system test mode. The computer system comprises a processor system, a physical memory system, and a secondary storage memory system. In response to a request to access a memory address, it is determined if the memory page associated with the memory address is available in the physical memory system, and if the memory page associated with the memory address is not pinned in the virtual memory area. In response to the memory page being available in the physical memory system but not pinned in the virtual memory area, an interrupt is generated.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventor: Jose Pina Coelho
  • Patent number: 10133666
    Abstract: A file storage method includes: splitting each of multiple files into one or more file block objects with different sizes; and writing the file block objects obtained from file splitting into corresponding large object storage files, wherein a preset number of large object storage files are pre-created in a storage apparatus, and storage spaces occupied by the preset number of large object storage files in the storage apparatus are continuous.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingchang Wei, Wei Zhang
  • Patent number: 10129244
    Abstract: Various examples are directed to systems and methods for providing access to computing resources. A resource system may receive an access request from a first user. The access request may comprise resource data describing a computing resource and function data describing a requested function to be performed on the computing resource. The resource system may determine that credential data provided by the first user is valid. The resource system may identify secondary data for the access request and generate an access object based at least in part on access object fragment data and the secondary data. The resource system may execute the access object to enable performance of the requested function on the computing resource.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 13, 2018
    Assignee: Princeton SciTech, LLC
    Inventors: Richard Garfinkle, Norton Garfinkle
  • Patent number: 10114763
    Abstract: Methods and systems are provided for fork-safe memory allocation from memory-mapped files. A child process may be provided a memory mapping at a same virtual address as a parent process, but the memory mapping may map the virtual address to a different location within a file than for the parent process.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 30, 2018
    Assignee: KOVE IP, LLC
    Inventors: Timothy A. Stabrawa, Andrew S. Poling, Zachary A. Cornelius, Jesse I. Taylor, John Overton
  • Patent number: 10104684
    Abstract: A user equipment (UE) receives downlink data using resource blocks in a wireless mobile communication system. The UE receives downlink control information including resource allocation information and downlink data mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the UE. A resource block pair includes a first resource block associated with a first time slot and a second resource block associated with a second time slot adjacent to the first time slot. The first and second resource blocks are allocated to the same frequency indices. A mapping between VRB pairs and PRB pairs exists such that frequency consecutive VRB pairs are mapped to non-frequency consecutive PRB pairs and that each resource block pair is split so there is a frequency gap between the first and second parts of the resource block pair.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 16, 2018
    Assignee: Optis Cellular Technology, LLC
    Inventors: Dong Youn Seo, Eun Sun Kim, Bong Hoe Kim, Joon Kui Ahn
  • Patent number: 10089242
    Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 10073621
    Abstract: A method is used in managing storage device mappings in storage systems. A set of mappings is created in a distributed storage system. The distributed storage system stores data in a redundant manner at more than one location on a set of storage devices by using a set of stripes. Each stripe of the set of stripes indicates a data slice stored on a storage device. Each mapping of the set of mappings identifies information regarding location of data on a storage device for a stripe. The mapping is stored on the set of storage devices.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 11, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Robert P. Foley, Peter Puhov
  • Patent number: 10068656
    Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 4, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Deepanshu Dutta, Sarath Puthenthermadam, Chris Yip
  • Patent number: 10067811
    Abstract: A method, computer program product, and computer system for maintaining, at a computing device, one or more tuples in a software-level queue. The one or more tuples may be transported as a batch of the one or more tuples from the software-level queue to a first queue for processing at a hardware accelerator. After processing the one or more tuples, the one or more tuples may be transported from the first queue to a second queue at the hardware accelerator. The one or more tuples may be transported from the second queue to a next location.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, Jonathan L. Kaus, David M. Koster, John M. Santosuosso
  • Patent number: 10067809
    Abstract: A method, computer program product, and computer system for maintaining, at a computing device, one or more tuples in a software-level queue. The one or more tuples may be transported as a batch of the one or more tuples from the software-level queue to a first queue for processing at a hardware accelerator. After processing the one or more tuples, the one or more tuples may be transported from the first queue to a second queue at the hardware accelerator. The one or more tuples may be transported from the second queue to a next location.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, Jonathan L. Kaus, David M. Koster, John M. Santosuosso
  • Patent number: 10061536
    Abstract: Embodiments of the present disclosure relate to a system, a computer program product and a method for synchronizing data between a source disk and a target disk in a cluster by performing synchronization between a source disk and a target disk, the synchronization being performed while a plurality of application I/Os on a plurality of nodes in a cluster are configured to access the source disk; and wherein a coordinator and a plurality of workers in the cluster are configured to manage copying data from the source disk to the target disk.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 28, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Vadim Agarkov, Sergey Storozhevykh, Maksim Vazhenin, Ilya Volzhev, Michael E. Bappe
  • Patent number: 10061696
    Abstract: A method for managing garbage collection of memory locations in an DSD having a plurality of dies each having a plurality of memory blocks includes: selecting a physical region of memory to be garbage collected, the selected physical region being a subset of a block management region; and garbage collecting the selected physical region. The garbage collecting includes: determining one or more journals corresponding to the selected physical region, the journal comprising transaction entries indicating what logical data are written to memory locations in the selected physical region; determining whether the memory locations within the physical region contain valid data based on a comparison of information in the journal and a mapping table; and if valid data exists, copying valid data into memory locations in memory regions other than the selected physical region of memory. The selected physical region of memory is erased when the block management region is erased.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Justin Jones, Andrew J. Tomlin, Paul Sweazey, Johnny A. Lam, Rodney N. Mullendore
  • Patent number: 10055363
    Abstract: A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 21, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Jochen Sauer, Robert Leinfellner, Matthias Klemm, Thorsten Brehm, Robert Polnau, Matthias Schmitz
  • Patent number: 10055343
    Abstract: A memory device comprises a first plurality of addressable memory locations associated with a first data storage window and a second plurality of addressable memory locations associated with a second data storage window. The memory device includes a controller that receives requests from a host device to identify the first data storage window and the second data storage window. The controller receives requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window. The controller receives memory commands from the host device that indicate the first window index value and at least one address. The controller accesses, based at least on the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: August 21, 2018
    Assignee: Memory Technologies LLC
    Inventors: Kimmo J. Mylly, Jani Hyvonen
  • Patent number: 10049042
    Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: August 14, 2018
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Atsushi Kawamura, Akifumi Suzuki, Hideyuki Koseki
  • Patent number: 10042775
    Abstract: Embodiments relate to a virtualized storage environment with one or more virtual machines operating on a host and sharing host resources. Each virtual machine has a virtual disk in communication with a persistent storage device. The virtual machine(s) may be misaligned with the persistent storage device so that a virtual block address does not correspond with a persistent storage block address. A relationship between the virtual disk(s) and the persistent storage device is established, and more specifically, an alignment delta between the devices is established. The delta is employed to translate the virtual address to the persistent address so that the virtual and persistent storage blocks are aligned to satisfy a read or write operation.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Nathan D. Fontenot, Robert C. Jennings, Jr., Joel H. Schopp, Michael T. Strosaker
  • Patent number: 10032025
    Abstract: An anti-malware application detects, stops, and quarantines ransomware. The anti-malware application monitors threads executing on a computing device and detects behaviors that conform to a predefined set of behaviors indicative of ransomware. Responsive to detecting these behaviors, indicators are stored to a log in a storage device. Each of the indicators in the log is associated with respective scores. A running score for each thread is generated by combining the respective scores of the indicators in the log. Responsive to determining that the running score exceeds a predefined threshold score, execution of the thread is terminated. The source ransomware file is then identified and quarantined.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: July 24, 2018
    Assignee: Malwarebytes Inc.
    Inventors: Mark William Patton, Ares Lopez Ituiño
  • Patent number: 10032019
    Abstract: Discrete events that take place with respect to a hard disk drive or other I/O device or port are indicated to logic that implements Self-Monitoring Analysis and Reporting Technology (SMART) or similar technology. These events are communicated to SMART as event data. Examples of such discrete events include power on, power off, spindle start, and spindle stop, positioning of the actuator, and the time at which such events occur. SMART then compiles event data to create compiled activity data. Compiled activity data represents summary statistical information that is created by considering some or all of the event data. Examples of compiled activity data include the Time Powered On and Power Cycle Count. Collection logic then writes the compiled activity data to a memory medium. An analyst can then read data from log file(s).
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 24, 2018
    Assignee: Stroz Friedberg, Inc.
    Inventors: Donald E. Allison, Kenneth A. Mendelson
  • Patent number: 10025281
    Abstract: A control device capable of appropriately switching operating modes when multitasking is being performed is provided. A CPU unit is provided with a task executing unit for executing a plurality of tasks in parallel, and for executing each task in cycles based on each task; and a mode switching unit for switching operating modes. The task executing unit is configured in such a manner that when in operation mode, a user program is executed for each task, and when in program mode, a user program is not executed for each task.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: July 17, 2018
    Assignee: OMRON CORPORATION
    Inventors: Osamu Hamasaki, Shigeyuki Eguchi, Akiro Kobayashi, Yukio Iname, Koji Yaoita
  • Patent number: 10025533
    Abstract: A logical block address space of a storage compute device is reserved for use in executing commands from a host. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 17, 2018
    Assignee: Seagate Technology LLC
    Inventors: Richard Esten Bohn, Peng Li, David Tetzlaff
  • Patent number: 10025615
    Abstract: An example method of updating a virtual machine (VM) identifier (ID) stored in a memory buffer allocated from guest memory includes supplying firmware to a guest running on a VM that is executable on a host machine. The firmware includes instructions to allocate a memory buffer. The method also includes obtaining a buffer address of the memory buffer. The memory buffer is in guest memory and stores a VM ID that identifies a first instance of the VM. The method further includes storing the buffer address into hypervisor memory. The method also includes receiving an indication that the VM ID has been updated. The method further includes using the buffer address stored in hypervisor memory to update the VM ID.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: July 17, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Gal Hammer
  • Patent number: 10019198
    Abstract: Provided are an apparatus and method for processing sequential writes portions of an addressable unit memory dies to store data. A write to a first portion of an addressable unit is received and the write is written to the first portion of the addressable unit. A next write is received to a next portion of the addressable unit following a previous write to a previous portion of the addressable unit. The next write is written to the next portion of the addressable unit sequentially following the previous portion in response to the next write being sequential with respect to the previous write. Data other than the next write is written to the addressable unit following the previous portion in response to the next write not being sequential with respect to the previous write.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 10, 2018
    Assignee: INTEL CORPORATION
    Inventor: Frank T. Hady
  • Patent number: 10019583
    Abstract: A Protected Walk-based Shadow Paging (PWSP) method includes storing a multiple level first stage (S1) page tables structure in second stage (S2) page tables. The method includes: when an S1 page table in an S2 page table entry is marked with a writable attribute: (i) permitting an operating system (OS) to write to the S1 page table, (ii) blocking a memory management unit (MMU) from reading the S1 page table for translation, and (iii) in response, verifying the S1 page table for translation and changing the marking of the S1 page table in the S2 page table entry to a read-only attribute, enabling the MMU to subsequently read the S1 page table.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kirk R. Swidowski, Ahmed M. Azab
  • Patent number: 10013358
    Abstract: A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource is allocated; and a cache state management mechanism that manages a cache state of the virtual computer. The virtualization mechanism provides a first virtual computer and a second virtual computer. The cache state management mechanism manages the cache state of each of the first virtual computer and the second virtual computer. When the cache state management mechanism detects transition of the cache state in a state where a memory area allocated to a cache of the first virtual computer and a memory area allocated to a cache of the second virtual computer include duplicated areas storing same data, the virtualization mechanism releases the duplicated area in one of the first virtual computer and the second virtual computer.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: July 3, 2018
    Assignee: HITACHI, LTD.
    Inventors: Sachie Tajima, Tadashi Takeuchi