Abstract: A vehicle ECU receives an ECU update package from a remote source. The ECU verifies a first timestamp included with the ECU update package postdates a second timestamp stored onboard the vehicle in conjunction with a last-successful update of the ECU and obtains a unique vehicle identifier from the vehicle bus. The ECU obtains secure configuration data for the ECU included in a payload of the update package and calculates a first hash value using at least the unique vehicle identifier and the secure configuration data. Also, the ECU validates the update package based on comparison of the first hash value matching a second hash value included in the update package and, responsive to the first timestamp post-dating the second timestamp and validation of the update package, modifies the ECU through use of the secure configuration data.

Abstract: The present disclosure provides a one-way air inlet valve for a cushioning airbag device and the cushioning airbag device. The one-way air inlet valve includes an air outlet member being in air communication with the at least one airbag; an air inlet member clamped into the air outlet member and being in air communication with the air outlet member; and a block movably arranged between the air outlet member and the air inlet member, the block comprising an engagement surface. Wherein the one-way air inlet performs one-way intake by a movement of the block, and when the block moves to the one of the air outlet member and the air inlet member, the engagement surface of the block tightly abuts against an inner surface of the one of the air outlet member and the air inlet member.

Abstract: A wireless transmit/receive unit (WTRU) may receive a downlink communication from a network over a first interface transmitted to one or more WTRUs in a group of WTRUs. The WTRU may determine an access class of the WTRU based on a packet loss percentage of the downlink communication. The access class may be associated with a contention window for accessing a second interface. The WTRU may transmit packet loss information to the one or more WTRUs over the second interface in the contention window. The WTRU may receive packet loss feedback from the one or more WTRUs over the second interface. The WTRU may determine that the access class of the WTRU is a highest class of the one or more WTRUs. The WTRU may transmit a single groupcast negative acknowledgement (gNACK) to the network on behalf of the one or more WTRUs over the first interface.

Abstract: A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

Abstract: A storage command is received from a client computer. The storage command includes a key associated with a content object that is to be written to two or more storage nodes in response to the command. A virtual address space is used to indicate a storage location of the content object. A virtual address of the virtual address space is assigned to the content object. The content object is redundantly stored the two or more storage nodes at respective two or more device addresses of the respective two or more storage nodes. The two or more device addresses are mapped to the virtual address, and the virtual address is returned to the client computer as a hint.

Abstract: As general matrix multiply (GEMM) bottlenecks are ameliorated by tensor parallelism that is distributed to several processors, layer normalization (LN) surfaces as a latent bottleneck as it is not amenable to distribution. LN performance is linear to embedding size, which is extremely large in some AI models. Moreover, aggressive tiling prevents the use of internal pipelining. The disclosed implementation addresses this issue, composing LN from simpler operations and this composition is amenable to pipelining, facilitating efficient implementation of large AI models (e.g., GPTs). In both forward and backward propagation, the pipeline is stretched longer with improved balance across stages. This strategy improves throughput for larger batch-sizes as the workload benefits from pipelining operations for better performance. Furthermore, avoiding stochastic rounding further improves performance. In addition, LayerNorm checkpoints facilitate efficient computation of gradients during backward propagation.

Abstract: A system includes a plurality of interconnected hardware platforms, wherein the plurality of hardware platforms are configured to run a software defined network, a plurality of virtual machines configured to be instantiated on the software defined network, and a plurality of floating management layers, each of the floating management layers associated with one of the plurality of virtual machines. Each floating management layer includes coupling the associated virtual machine to one of the plurality of hardware platforms, monitoring performance of the associated virtual machine, detecting a trigger, based on the trigger, determining whether to move the virtual machine to a second of the plurality of hardware platforms, and moving the virtual machine.

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: generate mapping data defining mapping, from logical block addresses in namespaces configured on the non-volatile storage media, to logical block addresses in a capacity of the non-volatile storage media; maintain an active copy of the mapping data; generate cached copies of the mapping data from the active copy; generate a shadow copy from the active copy; implement changes in the shadow copy; after the changes are made in the shadow copy, activate the shadow copy and simultaneously deactivate the previously active copy; and update the cached copies according to the newly activated copy, as a response to the change in active copy identification.

Abstract: A vehicle that is an automatic driving vehicle acquires a control program for an ECU from a control center by wireless communication. A server includes a keyboard and mouse to accept handling by an operation manager that manages operation of the vehicle from outside of the vehicle, a display to present information to the operation manager, a communication IF configured to communicate with the control center, and a processor. The processor controls the display such that the display presents an update condition of the control program to the operation manager, when the control program is updatable. The processor control the communication IF such that the communication IF gives a notice of approval of update of the control program to the control center, when the keyboard and the mouse have accepted an operation manager's handling for approving the update of the control program.

Abstract: A modular surgical system for use in a surgical procedure is disclosed. The modular surgical system includes a header module, a first surgical module, a second surgical module, a first backplane connector configured to detachably connect the header module to the first surgical module, and a second backplane connector configured to detachably connect the first surgical module to the second surgical module. The first surgical module is arrangeable in a stack configuration with the header module and the second surgical module. The first backplane connector is configured to yield a first bit pattern identifying the first surgical module in the stack configuration. The second backplane connector is configured to yield a second bit pattern identifying the second surgical module in the stack configuration. The first bit pattern is different than the second bit pattern.

Abstract: A method of applying an address space to data storage in a non-volatile solid-state storage is provided. The method includes receiving a plurality of portions of user data for storage in the non-volatile solid-state storage and assigning to each successive one of the plurality of portions of user data one of a plurality of sequential, nonrepeating addresses of an address space. The address range of the address space exceeds a maximum number of addresses expected to be applied during a lifespan of the non-volatile solid-state storage. The method includes writing each of the plurality of portions of user data to the non-volatile solid-state storage such that each of the plurality of portions of user data is identified and locatable for reading via the one of the plurality of sequential, nonrepeating addresses of the address space.

Abstract: A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.

Abstract: An apparatus comprises a processing device configured to select, from a first storage virtualization appliance, virtual volumes to migrate to a second storage virtualization appliance. The processing device is also configured to determine a configuration of first storage elements of the first storage virtualization appliance utilized to implement the selected virtual volumes, and to provision second storage elements for implementing the selected virtual volumes on the second storage virtualization appliance, the second storage elements being provisioned in an inactive state.

Abstract: A memory device includes a Non-Volatile Memory (NVM) comprising a plurality of sectors, and a memory access circuit. The memory access circuit is configured to receive, from a host, a logical address of a block of data, to compute a mapping of the logical address to a data physical address comprising a selected sector among the plurality of sectors and a selected data offset within the same selected sector, to compute a metadata physical address that comprises the selected sector and a metadata offset in the selected sector, and to access the block of data at the data physical address, and the metadata at the metadata physical address.

Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.

Abstract: Disclosed is an operating method of a storage device which includes a plurality of nonvolatile memory chips. The method includes providing, at the storage device, information of a capacity of each of the plurality of nonvolatile memory chips to an external host device, receiving, at the storage device, information of a plurality of groups from the external host device, performing a reset after receiving the information of the plurality of groups, mapping, at the storage device, the plurality of nonvolatile memory chips with the plurality of groups, and configuring the plurality of nonvolatile memory chips so as to correspond to the plurality of groups, after performing the reset.

Abstract: A method for execution by a computing device of a storage unit of a storage network includes receiving a digest list request from a storage network entity regarding integrity data for a set of encoded data slices where the storage unit stores a plurality of encoded data slices of the set of encoded data slices and corresponding integrity data, where the digest list request is for integrity data of the plurality of encoded data slices. The method continues with the storage unit collecting integrity data, transmitting the collected integrity data to the storage network entity. The method continues with the storage unit receiving an indication that an inconsistency exists in the collected integrity data as compared to integrity data received from one or more other storage units storing a second plurality of encoded data slices of the set of encoded data slices.

Abstract: A plurality of functions to configure a unit of a storage volume is maintained, wherein each of the plurality of functions, in response to being applied to the unit of the storage volume, configures the unit of the storage volume differently. Statistics are computed on growth rate of data and access characteristics of the data stored in the unit of the storage volume. A determination is made as to which of the plurality of functions to apply to the unit of the storage volume, based on the computed statistics.

Abstract: A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.

Abstract: The present disclosure generally relates to determining host device read patterns and then matching autonomous defragmentation to the read pattern to reduce latency impact and avoid unnecessary write amplification (WA). Host devices tend to read data in similar sized chunks. Additionally, host devices tend to read certain data sequentially. Based upon the typical chunk size and data read, the data can be defragmented in sizes to match the typical host device read chunks, and the data defragmented can then be read sequentially within a same plane even if the defragmented data is on different dies. The data is defragmented without relying upon a host command to be presented. Background operation time is used to move updated data such that a future sequential read is supported.

Abstract: Techniques are disclosed relating to restarting a database node. A database node may allocate memory segments that include a restart segment for storing data records. The database node may spawn processes to read a log and replay log records of the log to update the restart segment to store data records. The database node may determine to perform a restart operation to transition from a first mode to a second mode. Performing the restart operation may include ceasing reading the log at a stop position and storing, based on the stop position, database state information that enables the processes to resume reading the log from the stop position. The database node may further deallocate the memory segments except for the restart segment and terminate the processes. After performing the restart operation, the database node may spawn the processes, which may resume reading the log based on the database state information.

Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

Abstract: A direct memory access (DMA) controller comprises template storage circuitry to store at least one DMA template indicative of a DMA data access pattern. Each DMA template comprises enable indications settable to an enable state or a disable state. In response to a DMA command associated with a source address, a destination address, a source DMA template, and a destination DMA template, DMA control circuitry generates a set of DMA memory access requests to copy data from source memory system locations to destination memory system locations. The source/destination memory system locations are selected to have addresses which are offset relative to the source/destination address by offset amounts corresponding to positions of enable indications set to the enable state within the source/destination DMA template. The source/destination DMA templates allow irregular patterns of DMA accesses to be controlled in fewer DMA commands.

Abstract: Techniques for rebuilding space accounting counters in mapping layers of storage appliances. The techniques include uniquely associating top levels of a mapping layer of a storage appliance with respective storage objects. The techniques further include determining amounts of logical storage space consumed by the respective storage objects from mappings of LBAs of the respective storage objects to virtual blocks of a virtual layer of the storage appliance. The techniques further include determining amounts of physical storage space consumed by the respective storage objects from logged information pertaining to each leaf pointer of a leaf level of the mapping layer that points to a virtual block in the virtual layer, each virtual block being mapped to a physical block in a physical layer of the storage appliance. The techniques further include using multi-threading to determine amounts of logical storage space consumed by dynamically adjustable ranges of the respective storage objects.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a method and an apparatus for determining an address mapping relationship, and a storage medium. The method for determining an address mapping relationship includes: obtaining a mapping relationship table between preset addresses and DRAM physical addresses under a preset condition; and analyzing values of bit addresses in the DRAM physical address according to a first preset rule, to determine an attribute of each bit address in the DRAM physical address, where the attribute is used for representing an address field of the DRAM physical address.

Abstract: Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value, and generate a second GPA range based on the expanded emulated memory width value. The example apparatus also includes an EPT generator to generate root paging structures of a first type of EPT with respective addresses within the first GPA range, and generate root paging structures of a second type of EPT with respective addresses within (a) the first GPA range and (b) the second GPA range.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: Systems, methods, and devices securely boot processors and nonvolatile memories. Methods include implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value. Methods also include retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor, and implementing a comparison operation of the validation value and the pre-computed validation value. Methods further include generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation.

Abstract: Distributed computing systems, devices, and associated methods of virtual RDMA switching are disclosed herein. In one embodiment, a method includes intercepting a command from an application in a container to establish an RDMA connection with a remote container on a virtual network. In response to the intercepted command, an RDMA endpoint at a physical NIC of a server is created. The method can also include intercepting another command to pair with a remote RDMA endpoint corresponding to the remote container. The intercepted another command contains data representing a routable network address of the remote RDMA endpoint in the RDMA computer network. Then, the RDMA endpoint created at the physical NIC of the server can be paired with the remote RDMA endpoint using the routable network address of the remote RDMA endpoint.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for hardware-level encryption. An example method includes receiving an instance of information/data by processing circuitry; and disassembling, by the processing circuitry, the instance of information/data into a plurality of sections. The processing circuitry assigns each section of the plurality of sections a location in an allocated portion of memory. The locations are determined based at least in part on a quantum obfuscation map (QOM). The QOM is generated based on one or more quantum obfuscation elements (QOEs) corresponding to a quantum state of a quantum particle. The processing circuitry then causes each of the plurality of sections to be stored at the corresponding assigned location in the allocated portion of the memory.

Abstract: A method for managing a data record in a computer system comprises: at least one computing server for hosting a computer session running with an operating system having a deduplication index and managing access to a session storage space; a shared storage space; an administration server for administering the shared storage space, executing a data management program; the computer session executing an interception program implementing the following steps: intercepting a read call to read at least one data record transmitted in the session; accessing the deduplication index and determining whether the data record is recorded in the shared storage space; if so, reading, from the deduplication index, the address of the data record in the shared storage space and redirecting the read call to this address; if not, overlooking the read call so that it is processed by the operating system.

Abstract: A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A data processing system is configured to pre-process data for a machine learning classifier. The data processing system includes an input port that receives one or more data items, an extraction engine that extracts a plurality of data signatures and structure data, a logical rule set generation engine configured to generate a data structure, select a particular data signature of the data structure, identify each instance of the particular data signature in the data structure, segment the data structure around instances of the particular data signature, identify one or more sequences of data signatures connected to the particular data signature, and generate a logical ruleset. A classification engine executes one or more classifiers against the logical ruleset to classify the one or more data items received by the input port.

Abstract: A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the first structure. A first portion of tag bits of the memory address may be matched with the first set of entries. A cache status may be determined based on matching the first portion of tag bits of the memory address with the first set of entries.

Abstract: A memory system includes a memory device including a plurality of memory dies that store data, and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for generating and managing map data in which a logical address of a host is corresponding to a physical address of the memory device, wherein, when logical information on two or more consecutive logical addresses requested to be accessed and physical information on two or more consecutive physical addresses corresponding to the two or more consecutive logical addresses are inputted from the host, the controller sequentially performs access operations on the physical addresses corresponding to the received physical information.

Abstract: A memory system includes: a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method, and a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method, wherein the controller is further configured to read the first or second memory blocks according to a number of free blocks included in the first memory blocks, when the read request for the second memory block is received after the specific amount of time.

Abstract: One example method includes receiving, at a node of a data confidence fabric (DCF), a DCF backbone, installing the DCF backbone at the node, receiving a config file at the node, and the config file includes configuration information concerning the node, and receiving and installing a trust insertion component specified in the configuration information, where operation of the trust insertion component is enabled by the DCF backbone, and the trust insertion component is operable to associate trust metadata with data received by the node.

Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

Abstract: First firmware metadata and second firmware metadata are based on nonvolatile metadata stored in the nonvolatile memory device. A normal operation including a first management operation resulting in a change of the first firmware metadata and an access operation in which the nonvolatile memory device is accessed may be performed. A virtual operation is performed including a second management operation resulting in a change of the second firmware metadata and in which the access operation is not performed. Whether an error has occurred in the first firmware metadata is determined by comparing the change of the first firmware metadata resulting from the first management operation and the change of the second firmware metadata resulting from the second management operation. An error in the metadata may be monitored through the redundant performance of the management operation that results in the change of the metadata without a corresponding access to the nonvolatile memory device.

Abstract: Methods, apparatus, and processor-readable storage media for machine learning-based anomaly detection using time series decomposition are provided herein. An example computer-implemented method includes processing, via machine learning techniques pertaining to time series decomposition functions, a first set of historical time series data derived from multiple systems within an enterprise; generating, based on the processed data, one or more pairs of upper bounds and lower bounds directed to system metrics; identifying system anomalies attributed to one or more of the multiple systems within the enterprise by comparing a second set of historical time series data derived from the one or more systems against the one or more pairs of upper bounds and lower bounds; prioritizing, via machine learning techniques pertaining to weighting functions, the system anomalies; and outputting, in accordance with the prioritization, the system anomalies to a user within the enterprise.

Abstract: Various implementations described herein relate to systems and methods for managing selective erasure in a Solid-State Drive (SSD) including receiving a selective erase command corresponding to erasing valid and invalid data mapped to a logical address and in response to receiving the selective erase command, erasing blocks in which one or more pages mapped to the logical address are located based on a mapping table that maps the logical address to the one or more pages. Both valid data and invalid data may be physically stored in one or more pages.

Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.

Abstract: A process control system includes first type and second type controllers having different hardware architectures coupled together by a redundancy network for providing a controller pool. Primary application modules (AMs) are coupled to the controller platforms by a plant-wide network. The controller platforms are coupled by an input/output (I/O) mesh network to I/O devices to provide an I/O pool coupled to field devices coupled to processing equipment. A translating device translates states and values from one of the primary AMs running on a first type controller to generate a backup AM having an instruction set compatible with the second type controller. A controller application module orchestrator (CAMO) extends synchronization to the second type controller, makes the backup AM available to the second type controller, and then switches to utilize the second type controller as an active controller running the process.

Abstract: A boot Read-Only Memory (ROM) update method and a boot-up method of an embedded system are provided. The boot Read-Only Memory (ROM) update method of an embedded system including a memory and a ROM. The memory includes a user data area and a boot ROM area that includes a first area and a second area. The ROM copies a first boot code from the boot ROM area during boot-up. The boot ROM update method includes writing a second boot code to the second area in response to a first ROM update command. The second boot code includes a second boot ROM image and a second signature for the second boot ROM image. The method also includes verifying validity of the second signature and, if the second signature is valid, swapping the first area and the second area. The first boot code is disposed in the first area and includes a first boot ROM image and a first signature for the first boot ROM image.

Abstract: A method, computer program product, and computer system for setting a preferred alignment value to a size of an address space mapped by one or more root pages. An allocation request may be received for the address space. A binary buddy allocation scheme may be executed to allocate an extent for the allocation request based upon, at least in part, the preferred alignment value.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple logical units and a memory controller. The memory controller accesses the memory device and updates content of an activated count table in response to a command issued by a host device. One or more sub-regions to be activated are identified in the command. The activated count table includes a plurality of fields each recording an activated count associated with one sub-region. The memory controller updates content of the activated count table by increasing one or more activated counts associated with the one or more sub-regions identified in the command. The memory controller further selects at least one sub-region according to the content of the activated count table and performs a data rearrangement procedure to move data of the selected at least one sub-region to a first memory space having continuous physical addresses.

Abstract: Methods, systems, and devices for exclusion regions for host-side memory address translation are described. In some examples, a host system may be configured to identify regions of logical addresses to be excluded from operating according to logical-to-physical (L2P) address mapping by the host system (e.g., for access commands), including such techniques that may be associated a host performance boosting (HPB) functionality. The host system may signal an indication for a memory system to inhibit communication of L2P mapping table information to the host system for the identified regions, which may inhibit, suppress, or exclude HPB functionality for those identified regions. In some examples, the memory system may continue to support HPB functionality by communicating L2P mapping table information for other regions, such as regions of logical addresses that may be read relatively frequently or may otherwise benefit from address translation at the host system.

Abstract: A method for encrypting and decrypting data, that includes using an encryption key and an address associated with a memory device or a software instance. The method for encrypting and decrypting data may be performed by a hypervisor or by a configured processor. The method may include receiving a read or write request specifying an address; performing a first lookup, in an address mapping table, to identify a memory module address of a memory module associated with the address; performing a second lookup to identify an encryption key associated with the read or write request; generating a decryption or encryption request that includes the memory module address; and the encryption key; and sending the decryption or encryption request to the memory module.