Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
  • Patent number: 11397671
    Abstract: A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Byung-Soo Jung
  • Patent number: 11379378
    Abstract: A memory system includes a plurality of memory dies configured to store data; and a controller coupled with the plurality of memory dies through a plurality of channels, wherein the controller decides whether to perform a pairing operation, by comparing the number of pieces of read data to be outputted to an external device, which are included in a first buffer, with an output count reference value, and wherein, in the case where the number of pieces of read data stored in the first buffer is greater than or equal to the output count reference value, the controller gathers other read requests and logical addresses corresponding thereto in a second buffer, and performs the pairing operation.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11372802
    Abstract: Distributed computing systems, devices, and associated methods of virtual RDMA switching are disclosed herein. In one embodiment, a method includes intercepting a command from an application in a container to establish an RDMA connection with a remote container on a virtual network. In response to the intercepted command, an RDMA endpoint at a physical NIC of a server is created. The method can also include intercepting another command to pair with a remote RDMA endpoint corresponding to the remote container. The intercepted another command contains data representing a routable network address of the remote RDMA endpoint in the RDMA computer network. Then, the RDMA endpoint created at the physical NIC of the server can be paired with the remote RDMA endpoint using the routable network address of the remote RDMA endpoint.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: June 28, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yibo Zhu, Jitendra D. Padhye, Hongqiang Liu
  • Patent number: 11366668
    Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Arm Limited
    Inventors: Vladimir Vasekin, David Michael Bull, Sanghyun Park, Alexei Fedorov
  • Patent number: 11354135
    Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: June 7, 2022
    Assignee: INTEL CORPORATION
    Inventors: Zhiqiang Qin, Tao Xu, Qing Huang
  • Patent number: 11341058
    Abstract: The present disclosure relates to handling page faults in a constant time. In particular, a data structure of a fixed height is used to store the page tables, allowing for a constant look up time for a particular page. Further, a virtual address descriptor corresponding to the page is used to obtain and load the data into the corresponding instruction data into the page. The virtual address descriptor is directly accessible from the page obtained from walking the page table. This allows page faults to be handled more efficiently in constant time.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 24, 2022
    Assignee: VMware Inc.
    Inventor: Adrian Drzewiecki
  • Patent number: 11321243
    Abstract: A data storage device includes a memory device including a normal data region and a mapping data region, the normal data region being configured to store normal data, the mapping data region being configured to store mapping data; a host request managing device configured to manage a read/write request from a host; a mapping managing device configured to cache a part of the mapping data and to manage mapping information according to a request from the host request managing device; and a memory controller configured to manage an operation of the memory device according to a request from at least one of the host request managing device and the mapping managing device.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 3, 2022
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Yeong Jae Woo, Sang Lyul Min
  • Patent number: 11307796
    Abstract: A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Anshuman Khandual, Saravanan Sethuraman, Venkata K. Tavva, Anand Haridass
  • Patent number: 11307991
    Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 19, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Jiyun-Wei Lin
  • Patent number: 11288238
    Abstract: A method for storing transaction records includes receiving, by a transaction log manager, a first commit request for a first transaction record from a first core, copying, based on the first commit request, the first transaction record to a first region of memory, making a first determination that the first region surpasses a space threshold, and copying, based on the first determination, a first plurality of transaction records from the first region to storage, wherein the first plurality of transaction records comprises the first transaction record.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Marc A. De Souter
  • Patent number: 11281608
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Patent number: 11275697
    Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 15, 2022
    Assignee: Apple Inc.
    Inventors: Kutty Banerjee, Pratik Chandresh Shah, Tatsuya Iwamoto, David E. Roberts
  • Patent number: 11269903
    Abstract: A system for storing and retrieving configuration data causes time-based and content-based indexes to be stored on a storage service. The system receives a request to identify the value of a property during a time period indicated by the request. The system retrieves, from the storage service, a time-based index associated with the time period. The retrieved time-based index is searched to identify a content index associated with the time period. The system retrieves the content index from the storage service, and searches the content index to identify a value, of the property, that is associated with the time period. The system generates a response to the request based on the results of the search of the content index.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Veeraraghavan Vijayaraj, Akram Malkawe, Pinwen Su, John Russell Lane
  • Patent number: 11256500
    Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 22, 2022
    Assignee: Aurora Labs Ltd.
    Inventor: Zohar Fox
  • Patent number: 11249968
    Abstract: A method, computer program product and system are provided. The method, computer program product and system execute a process for storing an object in an object container that is stored in a persistency of a disk storage. The object container has size criteria whereby objects meeting the size criteria of the object container can be assigned to the object container. The object container can facilitate storing multiple objects to optimize disk storage usage by facilitating the assigning of multiple objects to the same disk storage page.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 15, 2022
    Assignee: SAP SE
    Inventors: Thorsten Glebe, Martin Heidel, Michael Muehle, Felix Knittel, Reza Sherkat
  • Patent number: 11232043
    Abstract: An apparatus includes a processing device configured to generate log records each representing a pointer from a leaf page in a logical address space of a storage system to a virtual block address and comprising a leaf page address of the leaf page. The processing device is also configured to identifying a subset of the log records representing pointers to a given virtual block address to determine a first reference count, and to determine whether the first reference count is different than a second reference count obtained from a given virtual entry of a given virtual block structure that corresponds to the given virtual block address. The processing device is further configured, responsive to determining that the first and second reference counts are different, to modify pointers to the given virtual block address in leaf pages with associated leaf page addresses in the identified subset of the log records.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Dixitkumar Vishnubhai Patel, Rohit K. Chawla, Soumyadeep Sen
  • Patent number: 11210226
    Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 28, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Jui-Lin Yen, Sheng-Hsun Lin, Jian-Wei Sun
  • Patent number: 11188638
    Abstract: A data processing system can use a method of fine-grained address space layout randomization to mitigate the system's vulnerability to return oriented programming security exploits. The randomization can occur at the sub-segment level by randomizing clumps of virtual memory pages. The randomized virtual memory can be presented to processes executing on the system. The mapping between memory spaces can be obfuscated using several obfuscation techniques to prevent the reverse engineering of the shuffled virtual memory mapping.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: November 30, 2021
    Assignee: Apple Inc.
    Inventors: Jacques A. Vidrine, Nicholas C. Allegra, Simon P. Cooper, Gregory D. Hughes
  • Patent number: 11176065
    Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Allan Porterfield
  • Patent number: 11176048
    Abstract: A data storage device may include a storage that store data in a plurality of physical storage spaces to which physical addresses are assigned, respectively, and a controller that control the storage, wherein the controller includes a mapping table of the physical addresses corresponding to logical addresses managed by a host, and wherein the controller is further configured to read data, in a primary read operation, from a physical storage space of a physical address corresponding to a logical address requested to be read by the host among the plurality of physical storage spaces according to the mapping table, obtain a normal physical address corresponding to the logical address requested to be read through the mapping table when the data read in the primary read operation is erased data; and read data, in a secondary read operation, from a physical storage space of the normal physical address.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Tae Kyu Ryu
  • Patent number: 11163730
    Abstract: Methods, systems, and computer storage media for providing data operations using hard links (hard link operations) for files in a file system are provided. Accessing files using hard link operations is based on File_Name-to-File_ID mappings and File_ID-to-File_Object mappings stored in hard link data structures. In operation, a file name for file content is received to perform a data operation. The file content is accessed using the file name. The file name is associated with a hard link data structure having a File_Name-to-File_ID mapping and a File_ID-to-File_Object mapping. The file name is also associated with an alternate file name for the file content. The alternate file name is associated with an alternate hard link data structure having an alternate File_Name-to-File mapping and the File_ID-to-File_Object mapping. The alternate file name is received. The file content is accessed using the alternate file name to perform an alternate data operation on the file content.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rajsekhar Das, Omar Carey
  • Patent number: 11157276
    Abstract: A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Maarten J. Boersma, Niels Fricke, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 11157185
    Abstract: A method, computer program product, and computer system for identifying, by a computing device, a plurality of blocks. A maximum number of blocks of the plurality of blocks capable of being copied to a new block may be identified. Data from the maximum number of blocks of the plurality of blocks may be copied to the new block.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 26, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Alex Soukhman, Uri Shabi
  • Patent number: 11150994
    Abstract: Provided are a computer program product, system, and method for creating a restore copy from a copy of source data in a repository having source data at different point-in-times. All the source data as of an initial point-in-time is copied to a repository. In response to completing point-in-time copies following the initial point-in-time, change information is transmitted to the repository indicating changed data in the source data that changed between the point-in-time of the point-in-time copy and a subsequent point-in-time. For each point-in-time copy, copying changed source data comprising source data indicated in the change information for the point-in-time copy as changed to the repository. A restore request is received to restore the source data as of a restore point-in-time. The source data in the repository as of the restore point-in-time is copied from the repository to a restore copy.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glen A. Jaquette, Gregory T. Kishi
  • Patent number: 11153986
    Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventor: Ian David Judd
  • Patent number: 11151048
    Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory, with the processing device being configured to maintain a content-based signature cache for a plurality of data pages. For each of a plurality of read operations to be directed to a distributed content addressable storage (CAS) system, the processing device determines if a data page targeted by the read operation has a corresponding content-based signature in the content-based signature cache. Responsive to the data page having a content-based signature in the content-based signature cache, the processing device identifies a particular storage node that stores the data page in the distributed CAS system, and directs the read operation to the identified storage node using the content-based signature to specify the data page targeted by the read operation. The processing device illustratively comprises a host device coupled to the CAS system over a network.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: October 19, 2021
    Assignee: Dell Products L.P.
    Inventors: Lior Kamran, Amitai Alkalay
  • Patent number: 11138129
    Abstract: An aspect of implementing globally optimized partial deduplication of storage objects includes gathering pages that share a common feature, dividing the pages into groups based on commonality with corresponding representative pages, where each is assigned as a representative dedupe page for the corresponding groups. For each group in the groups of pages, an aspect also includes writing the pages to a corresponding physical container.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: October 5, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Uri Shabi, Ronen Gazit
  • Patent number: 11132256
    Abstract: Example redundant array of independent disks (RAID) storage systems and methods provide rebuild of logical data groups. Storage devices are configured as a storage array for storing logical data groups distributed among the storage devices. The logical data groups are written in a configuration of RAID stripes in the storage devices. A failed storage device may be rebuilt using the RAID stripes and completed rebuilds of logical blocks may be tracked during the device rebuild process. A logical group rebuild status may be determined by comparing the completed rebuilds of logical blocks to a logical group map. The logical group rebuild status for each logical data group may be provided as complete in response to all logical blocks in the logical data group having been rebuilt. In the event the array rebuild fails, the logical groups that did complete rebuild may be brought online as a partially completed rebuild to prevent the loss of the entire array.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Adam Roberts
  • Patent number: 11126552
    Abstract: Disclosed are a memory system, a memory controller and a method for operating a memory controller. The memory controller manages statuses of respective pages by referring to a first memory and a second memory, the first memory stores a valid page table which includes valid page checking information of the respective pages, and the second memory caches a cache table which includes information for updating a part of the valid page table and has a size smaller than the valid page table, whereby it is possible to improve write performance through effective management of page status information.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Min-O Song
  • Patent number: 11119937
    Abstract: A data storage system includes a logical space having logical block addresses (LBAs) divided into non-overlapping LBA ranges, and a physical space having pairs of physical bands. The system also includes a map in which first successive alternate LBAs of each different one of the non-overlapping LBA ranges are mapped to successive adjacent physical blocks of a first physical band of each different pair of the pairs of physical bands, and second successive alternate LBAs of each different one of the non-overlapping LBA ranges are mapped to successive adjacent physical blocks of a second physical band of each different pair of the pairs of physical bands. A controller employs the map to concurrently read data from a first physical block of the first physical band of one pair of physical bands and from a first physical block of the second physical band of the same pair of physical bands.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, Li Hong Zhang
  • Patent number: 11122095
    Abstract: Methods, non-transitory machine readable media, and computing devices that provide improved dictionary-based compression are disclosed. With this technology, a first portion of an input data stream is compressed using a first dictionary. A second dictionary is trained when the first dictionary is determined to be stale. The dictionary can be determined to be stale based on a size of the input data stream compressed using the first dictionary or a compression ratio decreasing by a threshold, for example. The first dictionary can be stored with metadata associated with the compressed first portion of the input data stream. Accordingly, this technology improves compression ratios, eliminates the need for reference counting, and facilitates improved reclamation of orphan dictionaries, among other advantages.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 14, 2021
    Assignee: NETAPP, INC.
    Inventor: Xing Lin
  • Patent number: 11113094
    Abstract: Virtual computer systems (virtual machines) have become increasingly common with the evolution of virtualization technology, cloud computing, etc. However, as a virtual machine and its associated guest operating system seek to execute and/or access a page of memory through synchronous processes execution of the virtual processor associated with the virtual processing is blocked until the page of memory is locked and available. Accordingly, time is wasted on calls waiting for physical page availability thereby reducing utilization of the host machine and virtual machine respectively. To address this an asynchronous virtual machine environment is established allowing the virtual machine or physical machine to handle additional operations whilst waiting for physical page availability.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 7, 2021
    Assignee: Parallels International GmbH
    Inventors: Alexey Koryakin, Nikolay Dobrovolskiy
  • Patent number: 11106374
    Abstract: A method is used in managing inline data de-duplication in storage systems. The method receives a request to write data at a logical address of a file in a file system of a storage system. The method determines whether the data can be de-duplicated to matching data residing on the storage system in a compressed format. Based on the determination, the method uses a block mapping pointer associated with the matching data to de-duplicate the data. The block mapping pointer includes a block mapping of a set of compressed data extents and information regarding location of the matching data within the set of compressed data extents.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Christopher Seibel, Bruce Caram, Alexei Karaban
  • Patent number: 11106593
    Abstract: The described technology is directed towards efficiently invalidating cached data (e.g., expired data) in a hash-mapped cache, e.g., on a timed basis. As a result, data is able returned from the cache without checking for whether that data is expired, (if desired and acceptable), because if expired, the data is only briefly expired since the last invalidation run. To this end, a data structure such as a linked list is maintained to track information representative of hash-mapped cache locations of a hash-mapped cache, in which the information tracks a sequential order of entering data into each hash-mapped cache location. An invalidation run is performed on part of the hash mapped cache, including using the tracking information to invalidate a sequence of one or more cache locations, e.g., only the sequence of those locations that contain expired data.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 31, 2021
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Sata Busayarat
  • Patent number: 11102120
    Abstract: A network device determines, based on a size of a lookup value, that the lookup value is to be stored across a set of two or more memory banks including a first memory bank and a second memory bank of a database. A first hash function is for determining locations for storing lookup values entirely in the first memory bank, whereas a second hash function is for determining locations for storing lookup values entirely in the second memory bank. A hash operation is performed on the lookup value using the first hash function to determine a memory location for storing the lookup value. A first segment of the lookup value is stored in the first memory bank at the memory location determined using the first hash function, and a second segment of the lookup value is stored in the second memory bank at the memory location determined using the first hash function.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 24, 2021
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Gil Levy, Carmi Arad
  • Patent number: 11100996
    Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Eric Kwok Fung Yuen, Gerard J. Perdaems
  • Patent number: 11100044
    Abstract: A request is received to retrieve at least a portion of a file from a compressed data archived image stored in a backup storage device. The compressed data archived image comprises a backup of a file system having a number of directories and a number of files. The compressed data archived image comprises a file that includes a compression of the number of files. An address of the at least the portion of the file within the compressed data archived image is determined. The at least the portion of the file is retrieved at the address in the compressed data archived image, without decompressing the compressed data archived image.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: August 24, 2021
    Assignee: NetApp, Inc.
    Inventors: Sisir Shekhar, Rakesh Bhargava M R, Krishna Murthy Chandraiah setty Narasingarayanapeta
  • Patent number: 11086789
    Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: August 10, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
  • Patent number: 11089710
    Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventor: Ian David Judd
  • Patent number: 11080189
    Abstract: The present disclosure provides techniques for managing a cache of a computer system using a cache management data structure. The cache management data structure includes a cold queue, a ghost queue, and a hot queue. The techniques herein improve the functioning of the computer because management of the cache management data structure can be performed in parallel with multiple cores or multiple processors, because a sequential scan will only pollute (i.e., add unimportant memory pages) cold queue, and to an extent, ghost queue, but not hot queue, and also because the cache management data structure has lower memory requirements and lower CPU overhead on cache hit than some prior art algorithms.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 3, 2021
    Assignee: VMware, Inc.
    Inventors: Wenguang Wang, Christoph Klee, Adrian Drzewiecki, Christos Karamanolis, Richard P. Spillane, Maxime Austruy
  • Patent number: 11068258
    Abstract: Disclosed embodiments relate to perform operations for receiving and integrating a delta file in a vehicle. Operations may include receiving, at an Electronic Control Unit (ECU) in the vehicle, a delta file, the delta file comprising a plurality of deltas corresponding to a software update for software on the ECU and startup code for executing the delta file in the ECU; executing the delta file, based on the startup code, in the ECU; and updating memory addresses in the ECU to correspond to the plurality of deltas from the delta file.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: July 20, 2021
    Assignee: Aurora Labs Ltd.
    Inventor: Zohar Fox
  • Patent number: 11061827
    Abstract: An aspect includes providing a metadata structure having a logical level that points to a virtual level and a physical level to which the virtual level points. The method also includes storing, at the virtual level, a reference counter for each of a plurality of virtual-level type storage address entries in the metadata structure, and providing a pointer in the metadata structure between each pair of a number of pairs of virtual level address entries in which corresponding pages share a set of common sectors. The reference counter tracks a number of instances in which a corresponding pointer points to a corresponding virtual level address entry. An aspect further includes storing a single instance of the common sectors at the physical level.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 13, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Alex Soukhman
  • Patent number: 11055216
    Abstract: A controller controls an operation of a semiconductor memory device. The controller includes a request analyzer, a storage, and a garbage collection controller. The request analyzer generates invalid data information, based on an erase request received from a host. The storage stores a garbage collection reference table representing memory blocks excluded from selection as a victim block on which a garbage collection operation is to be performed, based on the invalid data information. The garbage collection controller controls the garbage collection operation on the semiconductor memory device, based on exclusion block information generated according to the garbage collection reference table.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Se Hyun Kim, Hui Jae Yu
  • Patent number: 11050436
    Abstract: A method, a system, and a computer program product for executing a database compression. A compressed string dictionary having a block size and a front coding bucket size is generated from a dataset. Front coding is applied to one or more buckets of strings in the dictionary having the front coding bucket size to generate one or more front coded buckets of strings. One or more portions of the generated front coded buckets of strings are concatenated to form one or more blocks having the block size. Each block is compressed. A set of compressed blocks is stored. The set of the compressed blocks stores all strings in the dataset.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 29, 2021
    Assignee: SAP SE
    Inventors: Robert Lasch, Ismail Oukid, Norman May
  • Patent number: 11016688
    Abstract: Disclosed is a distributed storage system and methods for providing real-time localized data access from different storage nodes of the distributed storage system. Providing the localized data access may include tracking access frequencies with which a file is directly accessed from the different storage nodes, storing a source copy of the file at the first storage node in response to the access frequency at the first storage node being greater than the access frequency at the other storage nodes, caching the file at a second storage node, transferring control over the source copy from the first storage node to a third storage node based on a change to the access frequencies, and validating the cached copy of the file at the second storage node against the source copy at the third storage node prior to responding to a request for the file from the second storage node.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 25, 2021
    Assignee: Open Drives LLC
    Inventors: Scot Gray, Sean Lee
  • Patent number: 11003588
    Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 11, 2021
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Sonu Arora, Paul Blinzer, Philip Ng, Nippon Harshadk Raval
  • Patent number: 11003524
    Abstract: A method of repairing an indirect addressing structure of a file system damaged by corruption of a virtual data block (VDB) mapping data stored in corresponding physical data blocks (PDBs) includes scanning PDB descriptors to identify PDBs storing data mapped by the corrupted VDB, where each identified PDB includes a set of PDB entries each having a backward pointer identifying a corresponding VDB entry of a corresponding VDB. The identified PDBs are scanned to identify PDB entries whose backward pointers refer to VDB entries of the corrupted VDB, then a replacement VDB is created by (1) for each of the identified PDB entries, recreating a corresponding VDB entry including a forward pointer to the identified PDB entry, and (2) incorporating the recreated VDB entries into the replacement VDB. The replacement VDB is then incorporated into the indirect addressing structure in place of the corrupted VDB.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 11, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Alexander S. Mathews, Rohit K. Chawla, Dixitkumar Patel, Soumyadeep Sen, Kumari Bijayalaxmi Nanda
  • Patent number: 10997085
    Abstract: A device compresses a mapping table in a flash translation layer of a SSD. The mapping table includes mappings between Logical Page Numbers (LPNs) and Physical Page Numbers (PPNs). A base PPN table stores at least one entry including a base PPN common to multiple LPNs. A PPN offset table stores an offset for each mapping. A set of hash functions are duplicated for each entry in the base PPN table. A bit extension unit adds bits to the respective offset in the PPN offset table to provide an extended offset bit. A hash calculator calculates a hash value using the base PPN and one of the hash functions corresponding to the base PPN. An exclusive OR unit outputs a new PNN for each of different LPNs, including the multiple LPNs, by applying an exclusive OR operation to the hash value and the extended offset bit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eri Ogawa, Takanori Ueda
  • Patent number: 10997083
    Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 4, 2021
    Assignee: ARM Limited
    Inventors: Geoffrey Wyman Blake, Prakash S. Ramrakhyani, Andreas Lars Sandberg
  • Patent number: 10997199
    Abstract: Computer-implemented methods and systems are provided for managing databases. Consistent with disclosed embodiments, a database system can serve configuration requests received from administration systems using an active cluster of at least two geographically separated computing clusters. Serving configuration request can include updating an active configuration database of the active cluster based on the configuration request. The system can also serve search requests received from user devices that specify a search criterion using a closest one of the geographically separated computing clusters by retrieving items satisfying the search criterion from local copies of a cache replicated across the geographically separated computing clusters. Furthermore, the system can serve transaction requests received from the user devices using the active cluster by updating an active local copy of the cache replicated in the active cluster.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 4, 2021
    Assignee: Amadeus S.A.S.
    Inventor: Thibaud Nicolas Castaing