Incrementing, Decrementing, Or Shifting Circuitry Patents (Class 711/219)
  • Patent number: 11372649
    Abstract: Described herein is a system and method of performing flow control for multi-threaded access to contentious resource(s) (e.g., shared memory). A request to enter a critical section of code by a particular thread of a plurality of concurrent threads is received. A determination is made as to whether or not to allow the particular thread to enter the critical section of code based, at least in part, upon a CPU core associated with the particular thread, a state associated with the particular thread, and/or a processing rate in the critical session of code associated with the particular thread. When it is determined to allow the particular thread to enter the critical section of code, the particular thread is allowed to enter the critical section of code.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: June 28, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Stanislav A Oks, Wonseok Kim
  • Patent number: 11367504
    Abstract: A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Lae Oh
  • Patent number: 11061677
    Abstract: A register mapping circuit for recovering a register mapping state associated with a flushed instruction by traversing ROB entries from a snapshot of another register mapping state. The register mapping circuit includes a ROB control circuit, a snapshot circuit, and a register rename recovery circuit (RRRC). The ROB control circuit allocates ROB entries to instructions entering a processor pipeline, including a target ROB entry allocated to a target instruction and other ROB entries allocated to other instructions. The snapshot circuit captures snapshots of logical register-to-physical register mapping states in the rename map table in association with a subset of instructions that could be flushed. If the target instruction is flushed, the RRRC restores the rename map table register mapping state corresponding to the target instruction based on a snapshot in a ROB entry allocated to another instruction, and traverses register mapping updates in the intervening ROB entries.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: July 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kiran Ravi Seth, Yusuf Cagatay Tekmen, Rodney Wayne Smith, Shivam Priyadarshi, Vignyan Reddy Kothinti Naresh
  • Patent number: 10862736
    Abstract: In an example, a system includes network nodes implementing an object store. The system may determine reference count updates for objects stored on the object store, and delay persisting the reference count updates to a persistent storage. The system may cancel reference count updates that increments and decrement between the determined reference count update and another reference count update received during the delay in persisting the reference count update to the persistent storage to minimize writing to the object record.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Glenn S. Watkins, John Michael Czerkowicz, Sumit Narayan, George A. Klarakis
  • Patent number: 10852999
    Abstract: A storage system comprises a plurality of storage devices and an associated storage controller. The storage controller is configured to receive a request to copy a first range of logical addresses to a second range of logical addresses, determine at least one physical block of the storage devices to which the first range of logical addresses is mapped, map the second range of logical addresses to the determined at least one physical block, and add at least one content-based signature associated with the determined at least one physical block to a pending increment data structure that includes content-based signatures corresponding to physical blocks for which an increment of an associated reference count is pending. The storage controller is further configured to execute a pending increment of a reference count associated with a given physical block corresponding to at least one of the content-based signatures in the pending increment data structure.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Uri Shabi
  • Patent number: 10649686
    Abstract: A system includes a memory with a ring buffer having a plurality of slots and a producer and consumer processor in communication with the memory. The producer processor is configured to receive a new memory entry and detect a failure to produce the new memory entry to a slot in the ring buffer. Each memory entry in the ring buffer has an entry structure to maintain a list of extra entries. The producer processor is also configured to determine a location of an entry pointer for a last produced memory entry in the ring and add the new entry to the list of extra entries in the respective slot in the ring. Responsive to consuming the last produced memory entry, the consumer processor is configured to check whether the last produced memory entry includes any other memory entries in the list of extra entries and consume the new memory entry.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: May 12, 2020
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10587454
    Abstract: In an example, a system includes network nodes implementing an object store. The system may determine reference count updates for objects stored on the object store, and delay persisting the reference count updates to a persistent storage. The system may cancel reference count updates that increments and decrement between the determined reference count update and another reference count update received during the delay in persisting the reference count update to the persistent storage to minimize writing to the object record.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 10, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Glenn S. Watkins, John Michael Czerkowicz
  • Patent number: 9990160
    Abstract: One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a group read port for the bank group. Another embodiment relates to a port emulation circuit module. The port emulation circuit module includes a port emulation control circuit that receives control signals including a first address for a group read/write port and a second address for a group read port, a first data path circuit for the group read/write port, and a second data path circuit for the group read port, wherein the second data path circuit outputs a second read data. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 5, 2018
    Assignee: Altera Corporation
    Inventor: Chee Hak Teh
  • Patent number: 9729630
    Abstract: A network media delivery system includes client devices and a host device. Each client device has a network interface, an engine for processing media data, and a media interface. The host device, which can be a computer, establishes network communication links with the client devices, which can be networked media stations, and sends media data to the client devices. The media data can be sent wirelessly as packets of media data transmitted at intervals to each client device. In one embodiment, the host device controls processing of media data such that processed media is delivered in a synchronized manner at each of the client devices. In another embodiment, the host device controls processing of media data such that processed media is delivered in a synchronized manner at the host device and at least one client device.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: August 8, 2017
    Assignee: APPLE INC.
    Inventors: Bob Bradley, Robert Dale Newberry, Jr.
  • Patent number: 9632793
    Abstract: Current tasks being executed in a set of modules of a signal processing system managed via an interface block are aborted so as to permit the execution of new tasks by pipelining eliminating transactions of said current tasks and executing transactions of the new tasks. Upon arrival of a signal to abort the current tasks, data and/or memory accesses present in said interface block are discarded.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 25, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventor: Daniele Mangano
  • Patent number: 9575889
    Abstract: A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: February 21, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jichuan Chang, Parthasarathy Ranganathan, Kevin T. Lim
  • Patent number: 9557993
    Abstract: The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 31, 2017
    Assignee: Analog Devices Global
    Inventors: Kaushal Sanghai, Michael G. Perkins, Andrew J. Higham
  • Patent number: 9448922
    Abstract: A memory storage system that includes at least a storage controller, a first non-volatile, solid-state memory and a second non-volatile, solid-state memory. The storage controller has an interface to receive commands from a host system. The first non-volatile, solid-state memory device is coupled with the storage controller to at least store data received from the host system. The second non-volatile, solid-state memory is coupled with the storage controller to store context information corresponding to the data stored in the first non-volatile, solid-state memory device.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 20, 2016
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Knut S. Grimsrud
  • Patent number: 9313127
    Abstract: In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Patrick W. Bosshart
  • Patent number: 9152400
    Abstract: The disclosure is related to optimizing generation of intermediate representation (IR) for a script code by eliminating redundant reference count code from the IR. The reference count code includes code that manages a reference count of an object, e.g., code that increments a reference count of the object (“incref code”) and an observer code which consumes or the execution of which depends on the reference count of the object. The IR is analyzed to identify redundant reference count code. Counters associated with the object are evaluated and upon satisfying the optimization criterion, the incref code is moved closer to the observer code. The incref code and the observer code that are adjacent to each other are identified as redundant code pair and the code pair is eliminated from the IR to generate an optimized IR. The optimized IR is further converted to an executable code.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: October 6, 2015
    Assignee: Facebook, Inc.
    Inventors: Guilherme de Lima Ottoni, Brett Hain Simmers, Bertrand Allen Maher, Edwin Thur Gideon Smith
  • Patent number: 9129069
    Abstract: A digital rack interface pod (DRIP) that is able to establish a communications link between a remote access appliance and a server having a USB port and a video port, to facilitate a keyboard/video/mouse (KVM) session between the server and the appliance. The DRIP is also able to establish a communications link between the appliance and an Ethernet port of the server that is associated with a service processor (SP) of the server. In this manner the DRIP is able to route data from the SP of the server to the appliance as well as communications from the appliance to the SP Ethernet port of the server. The DRIP is able to intelligently determine which packets of information received from the appliance are intended for the SP Ethernet port of the server and routes those packets to the SP Ethernet port of the server.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 8, 2015
    Assignee: AVOCENT HUNTSVILLE CORP.
    Inventors: Lawrence Lo, Karl Mills, Adam W. Lew, Mehmood Nurmohamed
  • Patent number: 9009441
    Abstract: In general, this disclosure describes techniques for selecting a memory channel in a multi-channel memory system for storing data, so that usage of the memory channels is well-balanced. A request to write data to a logical memory address of a memory system may be received. The logical memory address may include a logical page number and a page offset, where the logical page number maps to a physical page number and the logical memory address maps to a physical memory address. A memory unit out of a plurality of memory units in the memory system may be determined by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number. The data may be written to a physical memory address in the determined memory unit in the memory system.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Lin Chen, Long Chen
  • Patent number: 8943297
    Abstract: A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, a plurality of memory tables, a combinational logic circuit, and a decoder. Each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. The combinational logic circuit receives lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Teleputers, LLC
    Inventors: Ruby Lee, Yu-Yuan Chen
  • Patent number: 8914612
    Abstract: Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: December 16, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Nagi N. Mekhiel
  • Patent number: 8880796
    Abstract: An apparatus and associated methodology providing a data storage system including a memory having a first addressable storage space and a second differently addressable storage space. A controller selectively accesses stored instructions that when executed store a first amount of a user data set to the first addressable storage space and store a different second amount of the user data set to the second addressable storage space. The controller subsequently calculates an address increment between the stored first and second amounts, and then shifts one of the stored first and second amounts by the address increment.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 4, 2014
    Assignee: Spectra Logic, Corporation
    Inventors: Joshua Daniel Carter, Burkhard Eichberger, Matthew Thomas Starr
  • Patent number: 8880815
    Abstract: An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nimrod Alexandron, Alexander Rabinovitch, Leonid Dubrovin
  • Patent number: 8880808
    Abstract: A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: November 4, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Rami Rahim, Pradeep Sindhu, Raymond Marcelino Manese Lim, Sreeram Veeragandham, David Skinner
  • Patent number: 8812819
    Abstract: Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: August 19, 2014
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Kellie Marks
  • Patent number: 8762686
    Abstract: A multimode accessible storage facility (10) is described that allows block access in a block access mode and row access in a row access mode. The facility comprises—a memory unit (20) comprising a plurality of memory banks (20.0, . . . , 20.F) each having a respective bank index (0, . . . , F), —an address generator (30) for generating for each of said memory banks a rotated bank address as a function of an input address and a shift parameter, —an input vector data rotator (40) for rotating an input vector and for providing vector elements of the rotated input vector to a respective bank of the memory unit, and—an output vector rotator (50) for inverse rotating a vector comprising vector elements retrieved from respective banks of the memory unit and for providing the rotated output vector.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Nikhil Kumar Sharma, Carlos Antonio Alba Pinto
  • Publication number: 20140136814
    Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple threshold values (TVs) from memory. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The multiple TVs define multiple lookup key ranges. The TM determines which lookup key range includes the LKV. A RV is selected based upon the lookup key range determined to include the LKV. The lookup key range is determined by a lookup key range identifier circuit. The selected RV is selected by a result value selection circuit.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 8688761
    Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 1, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Muhammad Ahmed, Ajay Anant Ingle, Sujat Jamil
  • Patent number: 8671261
    Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: March 11, 2014
    Assignee: Microsoft Corporation
    Inventors: Gregory J. Colombo, Hari Pulapaka, Arun U. Kishan, Stephen L. Hufnagel, Garrett Trent Leischner, Evan Lincoln Tice, Matthew R. Miller
  • Patent number: 8635426
    Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: January 21, 2014
    Inventor: Daniel Robert Shepard
  • Patent number: 8527802
    Abstract: A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: September 3, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Thinh Tran, Joseph Tzou
  • Patent number: 8510503
    Abstract: Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kiyoto Yagihashi
  • Patent number: 8473693
    Abstract: The present invention provides techniques for managing ownership (i.e., control) of one or more memory buffer (mbuf) data structures within a network subsystem and a storage subsystem of a storage operating system implemented in a storage system. When the storage system receives data to be written to a storage medium, the network subsystem stores the received data in one or more variable-length chains of mbufs. Unlike conventional approaches, the received data is not subsequently copied out of the mbufs into fixed-sized data buffers for use by the storage subsystem. Instead, the storage subsystem can directly manipulate the received data stored in the mbufs. By eliminating the steps of copying data out of the mbufs and into fixed-sized data buffers, the invention reduces the amount of time and system resources consumed by the storage system when writing blocks of received data to disk storage.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: June 25, 2013
    Assignee: NetApp, Inc.
    Inventors: Nitin Muppalaneni, Edward R. Zayas, Douglas Santry
  • Patent number: 8364930
    Abstract: According to one embodiment, an information processing apparatus includes an information processing apparatus main body and a storage drive which is accommodated in the information processing apparatus body. The information processing apparatus main body includes a main control module which controls power activation of the storage drive based on a power activation operation by a power operation section. The storage drive includes a storage memory including a plurality of storage areas to and from which information can be written and read, a counter in which a count is incremented upon power activation, and a memory control module which stores a content of an access request in a storage area of the storage memory determined based on the count of the counter when the access request to the storage memory is made.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takehiko Kurashige
  • Patent number: 8352708
    Abstract: A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: January 8, 2013
    Assignee: Teleputers, LLC
    Inventors: Ruby B. Lee, Yu-Yuan Chen
  • Patent number: 8321649
    Abstract: A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 27, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hemant Nautiyal, Dhruv Satsangi
  • Patent number: 8275934
    Abstract: A nonvolatile memory device includes first and second registers configured to store parameters received via an input/output (IO) unit, a microcontroller configured to control an operation of the nonvolatile memory device according to the parameter stored in the first register, and a control logic unit configured to, when a parameter is received via the IO unit while the microcontroller performs an internal operation, store the received parameter in the second register.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Myung Su Kim
  • Patent number: 8255668
    Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: August 28, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinya Ohhashi, Satoshi Takashima, Akihiro Miki
  • Patent number: 8254204
    Abstract: A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-young Park, Jae-young Choi, Hyoung-soon Km
  • Patent number: 8239658
    Abstract: An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: August 7, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Stefan-Cristian Rezeanu
  • Patent number: 8233780
    Abstract: A reproducing apparatus and method includes a reproducing unit to reproduce mainstream data and sub audio data separately added in the mainstream data, wherein the reproducing unit comprises a counter used in reproducing the sub audio data. Accordingly, it is possible to more naturally reproduce still image data, such as a browsable slide show, to which sub audio data is additionally included, thus preventing an interruption in reproduction of the sub audio data even during a forward or reverse play.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-soo Jung, Seong-jin Moon
  • Patent number: 8195919
    Abstract: Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: June 5, 2012
    Assignee: Oracle America, Inc.
    Inventors: Christopher H. Olson, Robert T. Golla, Manish Shah, Jeffrey S. Brooks
  • Patent number: 8171258
    Abstract: In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: May 1, 2012
    Assignee: Apple Inc.
    Inventors: Rajat Goel, Chen-Ju Hsieh
  • Patent number: 8166278
    Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: April 24, 2012
    Assignee: Intellectual Ventures I LLC
    Inventor: Laurence H. Cooke
  • Publication number: 20120042149
    Abstract: A multimode accessible storage facility (10) is described that allows block access in a block access mode and row access in a row access mode. The facility comprises—a memory unit (20) comprising a plurality of memory banks (20.0, . . . , 20.F) each having a respective bank index (0, . . . , F), —an address generator (30) for generating for each of said memory banks a rotated bank address as a function of an input address and a shift parameter, —an input vector data rotator (40) for rotating an input vector and for providing vector elements of the rotated input vector to a respective bank of the memory unit, and —an output vector rotator (50) for inverse rotating a vector comprising vector elements retrieved from respective banks of the memory unit and for providing the rotated output vector.
    Type: Application
    Filed: February 22, 2010
    Publication date: February 16, 2012
    Applicant: Silicon Hive B.V.
    Inventors: Nikhil Kumar Sharma, Carlos Antonio Alba Pinto
  • Patent number: 8099448
    Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: January 17, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Muhammad Ahmed, Ajay Anant Ingle, Sujat Jamil
  • Patent number: 8051272
    Abstract: A method for generating addresses for a processor is provided. The addresses are for use by an application that may be executed by the processor. The application comprises a plurality of instructions, and each instruction comprises at least one line. The method includes storing a plurality of predetermined addresses and, for each line of each instruction, generating at least one address for the processor based on the predetermined addresses.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eran Pisek
  • Publication number: 20110246727
    Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Inventors: David Dice, Nir N. Shavit
  • Patent number: 8028149
    Abstract: A method of reading a group of memory words from an integrated circuit memory of a contactless tag, comprising the sending by a remote interrogation unit to the contactless tag of a specific command for reading the group of memory words from a given start address, the initialization of an address counter for the contactless tag to the value of the given start address, and the sending by the contactless tag of the memory word at the start address, as well as an iterative process comprising in succession a first step of sending by the remote interrogation unit to the contactless tag of an incrementation marker recognizable by the contactless tag, a second step of incrementation of the address counter for the contactless tag in response to the incrementation marker, and a third step of sending by the contactless tag to the remote interrogation unit of a data frame comprising the memory word stored in the memory at the address pointed at by the current value of the address counter.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: September 27, 2011
    Assignee: STMicroelectronics SA
    Inventors: Christophe Moreaux, Pierre Rizzo
  • Patent number: 7974275
    Abstract: Methods for aging datagrams in the memory portion of a datagram distribution device or other network device are provided. According to some of these methods, an attribute of each datagram entering the device may be used to assign an initial aging counter value to each datagram. Then, the attribute-specific aging counter values may be used to extend the time until expiration of certain datagrams relative to other datagrams. Also, devices for implementing these methods are provided.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: July 5, 2011
    Assignee: Broadcom Corporation
    Inventor: Chien-Hsien Wu
  • Patent number: 7962705
    Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: June 14, 2011
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Andrew Caldwell, Brad Hutchings, Jason Redgrave, Steven Teig
  • Publication number: 20110035566
    Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: OC APPLICATIONS RESEARCH LLC
    Inventor: Laurence H. Cooke