Abstract: Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.

Abstract: In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: A multimode accessible storage facility (10) is described that allows block access in a block access mode and row access in a row access mode. The facility comprises—a memory unit (20) comprising a plurality of memory banks (20.0, . . . , 20.F) each having a respective bank index (0, . . . , F), —an address generator (30) for generating for each of said memory banks a rotated bank address as a function of an input address and a shift parameter, —an input vector data rotator (40) for rotating an input vector and for providing vector elements of the rotated input vector to a respective bank of the memory unit, and —an output vector rotator (50) for inverse rotating a vector comprising vector elements retrieved from respective banks of the memory unit and for providing the rotated output vector.

Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

Abstract: A method for generating addresses for a processor is provided. The addresses are for use by an application that may be executed by the processor. The application comprises a plurality of instructions, and each instruction comprises at least one line. The method includes storing a plurality of predetermined addresses and, for each line of each instruction, generating at least one address for the processor based on the predetermined addresses.

Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.

Abstract: A method of reading a group of memory words from an integrated circuit memory of a contactless tag, comprising the sending by a remote interrogation unit to the contactless tag of a specific command for reading the group of memory words from a given start address, the initialization of an address counter for the contactless tag to the value of the given start address, and the sending by the contactless tag of the memory word at the start address, as well as an iterative process comprising in succession a first step of sending by the remote interrogation unit to the contactless tag of an incrementation marker recognizable by the contactless tag, a second step of incrementation of the address counter for the contactless tag in response to the incrementation marker, and a third step of sending by the contactless tag to the remote interrogation unit of a data frame comprising the memory word stored in the memory at the address pointed at by the current value of the address counter.

Abstract: Methods for aging datagrams in the memory portion of a datagram distribution device or other network device are provided. According to some of these methods, an attribute of each datagram entering the device may be used to assign an initial aging counter value to each datagram. Then, the attribute-specific aging counter values may be used to extend the time until expiration of certain datagrams relative to other datagrams. Also, devices for implementing these methods are provided.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: Disclosed are a method and apparatus of non-system bus width data transfer executable at a non-aligned system bus address. In one embodiment, a method of a controller is described. The method includes applying a FIFO buffer having a buffer width (e.g., determined using a transfer algorithm) that is wider than that of a system bus width. A system bus that permits transfer of data amounts which are non-integer multiples of a width of the system bus is used. The system bus is designed such that it supports any non-aligned system bus address. Data is transferred between devices coupled to the system bus.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.

Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

Abstract: A serial decoding technique may employ one or more circular shift register strings in which an input to an element of a shift register string may be gated by either an address input or the inverse of the address input. An output word line of the decoder may be driven by a respective shift register stage in the case of a single shift register string, or by a logical combination of shift register stages from respective shift register strings in the case of multiple shift register strings.

Abstract: An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.

Abstract: A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.

Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

Abstract: Techniques are provided for incrementally maintaining an XML index built to access XML data that is encoded in binary XML form. Rather than delete and reinsert index entries of all the nodes of a modified XML document, only the index entries of the affected nodes are modified. Consequently, the order key values stored in the index may become inconsistent with the current hierarchical locations of the nodes to which the order key values correspond. Techniques are described for resolving the inconsistencies, and for addressing additional problems that result when the XML index is path-subsetted.

Abstract: Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to select one of a plurality of entries in a segment table, each entry of the segment table representing a different segment of a memory using at least a portion of the selected entry of the segment table as a reference to one or more of a plurality of entries in a page table, each entry in the page table including at least a portion of a physical address in the memory and belonging to a group of entries representing a page in the selected segment of the memory; using the second portion of the first intermediate address to produce a second intermediate address; and using at least a portion of the second intermediate address as a pointer directly to one of the referenced entries in the page table to obtain an at least partially translated physical address into the memory for the external address.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.

Abstract: A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

Abstract: A device comprises a processor configured to execute a sequence of program instructions, a first storage configured to store a first memory address, a second storage configured to store a second memory address, a program counter configured to determine a memory address of program instructions to be executed, and a program counter manipulator configured to set the program counter to a value corresponding to a content of the second storage in response to the program counter reaching a value corresponding to a content of the first storage.

Abstract: A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

Abstract: In a KVM system, a system provides for USB devices to be accessed by target computers. A KVM switch connects a client with a target server via a network, the client computer having at least one device attached thereto. A second mechanism connects to a USB port of the target and communicates with the target using a USB protocol. A client mechanism communicates with the second mechanism via the network. A virtual media mechanism enables the target server to access the USB device attached to the client.

Abstract: Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure. Memory is divided into blocks having sequential addresses based on the number of simultaneous memory access specified, e.g. base addresses at A, A+B, A+2B, A+3B. Individual slave side arbiters are assigned to each block of memory. Addresses for memory accesses associated with master components or master ports are modified to allow simultaneous access to multiple memory locations.

Abstract: Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer 310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

Abstract: A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31) and a modulo value (33). The next address (36) is generated based on these inputs as follows. An adder (22) generates a first address (32) by adding the input address (30) and the increment (31) and a second address (34) is generated by subtracting the modulo (33) from the first address (32) by means of the subtractor (23). The comparator (45) checks whether the second address is lower than or equal to zero and if so, the multiplexer (24) outputs the first address at its output (36). If the second address is higher than zero, the multiplexer (24) is controlled such that it outputs the second address (34). A further comparator (63) compares the input address (30) and the modulo (33).

Abstract: Abuse of a content-sharing service is detected by an arrangement in which an in-memory cache is distributed among a plurality of nodes, such as front-end web servers, and which caches each item accessed by users of the service as a single instance in the distributed cache. Associated with each cached item is a unit of metadata which functions as a counter that is automatically incremented each time the item is served from the distributed cache. Because abusive items often tend to become quickly popular for downloading, when the counter exceeds a predetermined threshold over a given time interval, it is indicative of an access rate that makes the item a candidate for being deemed abusive. A reference to the item and its access count are responsively written to a persistent store such as a log file or database.

Abstract: For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.

Abstract: A system includes a processor for executing a collector program to perform a method (e.g., a method of collection). The method includes using an object model during a collection phase that is different than an object model used during program execution. The processor may also perform a method including assigning a hash code to at least some objects, and consulting a structure that maintains a mapping of objects to hashcode values to determine said hashcode for one of said objects. The processor may also perform a method including storing a class pointer and garbage collector state information in a single word, and accessing said class pointer by masking out non-class bits.

Abstract: A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of the memory die within a given range of sizes.

Abstract: An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the base unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.

Abstract: Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in electronic memory by hashing a value to determine a home address of an entry in the hash table, the hash table having a plurality of entries, each entry comprising an address, a value, and a link. The embodiments may include determining whether there is a collision of the value with a value stored in the entry; inserting the value in the entry if there is no collision; and generating the addresses of further entries until an entry is found in which the value can be inserted if there is a collision. The embodiments may include generating a plurality of addresses of entries based upon the address of a previously generated entry.

Abstract: A method, system, computer system, and computer-readable medium that enable a secondary host that is not the file system host to create a backup of a clone file set that shares at least one data block on a storage device with an active file set. Start and end locations are identified for a set of contiguous storage locations (referred to as a “chunk”) on the storage device. Physical location information is obtained for each portion of a file contained in the chunk. The start and end locations and physical location information for portions of files contained in the chunk are provided to the secondary host, which sequentially reads data from the set of contiguous storage locations and constructs a copy of the file(s) making up the clone file set. The file(s) are written by the secondary host to a storage device to create a backup of the clone file set.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: A method and apparatus for high speed addressing of a memory space from a relatively small address space. An N-bit bus interfaces with a memory device having a 2M address memory space, where M is greater than N. The method and apparatus provide for (a) providing at least two registers, (b) receiving one byte of a plurality of N-bit bytes that together define an address in the memory space, (c) incrementing a count as a result of completing step (b), (d) addressing one of the two registers according to the incremented count in step (c), and (e) storing the one byte in the register addressed in step (d).

Abstract: A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.

Abstract: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually rise, based on external address signals that have already been received until new external address signals are received.

Abstract: A system, method, and apparatus for load balancing to a plurality of ports is presented herein. A miniport driver is adapted to multiplex and demultiplex traffic workload across the ports. The miniport driver classifies outgoing packet streams and distributes each packet stream to a communication ring, such as an Ethernet ring, for example, associated with at least one of the ports. Additionally, the miniport driver can be configured to configure a operation of the plurality of ports in one of several modes, including a mode wherein the plurality of ports are operable and act as a single logical interface for the operation.

Abstract: Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which comprises a plurality of memory modules disposed as an array of parallel columns. In response to receiving an indication that said plurality of instances of data is being accessed as a row of data, a first address translation table is accessed which describes the same row address in each of said plurality of memory modules wherein an instance of data is stored. Then, in response to receiving an indication that said plurality of instances of data is being accessed as a column of data, a second address translation table is accessed which describes a successive row address in each successive memory module wherein an instance of data is stored.

Abstract: A system for booting a microprocessor controlled system wherein a basic interface between the processor and peripheral devices is stored and retrieved from the general purpose application and file storage device.

Abstract: Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.