Abstract: A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch.

Abstract: In a heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems, an I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least one disk connected to the I/O subsystem B in a magnetic tape library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

Abstract: A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles used to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.

Abstract: In a digital system having a host, a controller device and at least one flash memory integrated circuit, a method and apparatus for storing location identification information regarding blocks of information within at least one of the flash memory integrated circuits wherein at least two buffers within the at least one of the flash memory integrated circuits are designated as primary and secondary buffers for storing the identification information in the primary buffer until the primary buffer is effectively full and storing additional identification information in the secondary buffer until it is effectively full, swapping buffer designation so that the primary buffer becomes the secondary buffer and the secondary buffer becomes the primary buffer, erasing the effectively-full buffer for re-use and in this manner, continuously swapping storage of identification information between the two buffers.

Abstract: A look-up switch accelerator which includes an associative memory for storing information associated with one or more look-up switch statements. For each look-up switch statement, this information includes a look-up switch identifier value, a plurality of match values and a corresponding plurality of jump offset values. The look-up switch accelerator also includes circuitry for determining whether a current instruction corresponds to a look-up switch statement stored in the memory, circuitry for determining whether a current match value associated with the current instruction corresponds with one of the match values stored in the memory, and circuitry for accessing a jump offset value from the memory when the current instruction corresponds to a look-up switch statement stored in the memory and the current match value corresponds with one of the match values stored in the memory (wherein the accessed jump offset value corresponds with the current match value).

Abstract: The invention described herein works in conjunction with a processor having an address translation cache that is updated by referencing a page table directory and a plurality of associated page tables referenced by the page table directory. The page table directory and a single page table are configured to generate a memory fault whenever the processor attempts to update its address translation cache. In response to such a memory fault, a memory fault handler temporarily loads a single page table entry with the needed address translation. In addition, the memory fault handler initializes the page table directory so that it references the single page table entry that has been loaded. Control is then returned from the memory fault handler, and the processor obtains the address translation. In response to a subsequent memory fault, the memory fault handler invalidates the previously loaded entry, and loads whatever address translation is currently needed by the processor.

Abstract: A backup system enables unmodified data to be copied to a read-only backup container that is smaller than the read-write container. The system creates and maintains structures that map the unmodified copies of data in the backing store container to locations in the read-write container. The mapping structures contain addresses of locations in the backing store container where collections of blocks of data are stored based on the original data block address of the data in the read-write container. In order to obtain the address of the location in the backing store container where a block of data is stored, the system converts the physical block number of the read-write block of data into a physical block address in the backing store container which actually contains the data.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The present invention also generates a second sample page base address corresponding to a first part of a second address received from the DSP. The first and second generated sample page base addresses are then stored in respective first and second locations within a multiple entry sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a third address.

Abstract: In a multiprocessor system where a shared expansion memory and a number of loosely coupled clusters are provided, each cluster comprises at least one CPU and a main memory connected to a system bus, and an address memory. During system initialization, a configuration table is created in the main memory, and an expansion memory location is accessed and status of the access is received. If the access status indicates that the access is successful, the address of the memory location is written into the address memory. Otherwise, an inaccessibility indication is stored in the configuration table to prevent the operating system from accessing that expansion memory location. During read/write operation, when an address of the expansion memory is received from the system bus, the address memory is searched for an address corresponding to the received address. If the received address has a corresponding address in the address memeory, data is tranferred between the expansion memory and the system bus.

Abstract: A memory controller for optimizing direct memory access (DMA) read transactions wherein a number of cache lines are prefetched from a main memory as specified in a prefetch length field stored in a page table. When all prefetch data has been fetched, the memory controller waits to determine whether the initiator of the DMA read transaction will request additional data. If additional data is needed, additional cache lines are fetched. Once the initiator terminates the DMA read transaction, the prefetch length field for a selected page other entry in the table is updated to reflect the actual DMA read transaction length. As a result, an optimum number of cache lines are always prefetched thereby reducing the number of wait states required.

Abstract: A storage device has a relative address table. An address is sequentially generated by an address adder based on a start address and a plurality of relative addresses held in the relative address table. When a pattern of the address is unchanged, a succeeding access is processed without resetting the relative addresses in the relative address table.

Abstract: A hardware/software system for analyzing memory dumps. The system collects data structures in a memory dump into logical tables, one logical table per selected type of data structure. The logical tables are generated by use of extraction logic for extracting data in data structures in the memory dump. The extraction logic is used in conjunction with a template library that contains data structure definitions for various types of data structures. The extraction logic, together with the template library, make possible populating logical tables with the contents of data structures found in the memory dump. Each row in a logical table is dedicated to one data structure of the selected type. Collecting data structures into logical tables makes available the power of a standard database management system for operating on the logical tables to determine the cause of a crash of a hardware/software system for which the memory dump was taken.

Abstract: In an assemble processing system, when a syntactical analysis procedure syntactically analyzes a source program, a macro definition procedure stores a macro definition program body of the source program in a macro definition area, and a macro reference procedure stores a macro formal parameter and a macro local symbol of the source program in a symbol table. After the operation of the syntactical analysis means is completed, the macro reference procedure deletes the stored macro formal parameter and the macro local symbol from said symbol table.

Abstract: A logical address and a pointer entry for a file in an indirect address file system are translated into a physical address. A decision module tests a pointer flag in a present pointer entry. The pointer entry has a pointer and a pointer flag to identify whether the pointer points to a data storage area or a metadata storage area. The decision module indicates whether the pointer is a data pointer or a metadata pointer. In response to the decision module indicating the pointer is a data pointer, a set module combines the data pointer with the logical address to generate a physical address. A split module, in response to the decision module indicating the pointer is a metadata pointer, divides the logical address into a first portion as an index value and a remaining portion as an offset value. An update module then sets the logical address to the offset value. A retrieve module combines the metadata pointer with the index value to get the next pointer entry.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The generated sample page base address is then stored in a sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a second address. Provided that the first part of the first address and the first part of the second address are the same, the present invention combines a second portion of the second address sent from the DSP with the generated sample page base address stored in the sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

Abstract: A data recording disk drive includes a system and method for mapping around skip sectors, both bad sectors and spare sectors. A received logical block address is converted to a corresponding physical block address by mapping through a set of tables. A first table includes entries for virtual tracks which group together LBAs having shared high order bits. A second table contains entries for the skip sectors. The high order bits of a given LBA are used to select an entry in the first table, which entry is an index into the second table. Starting from the index point, the second table is searched, using the low order bits of the LBA, for a skip sector beyond the LBA value. Once the appropriate skip sector is found, the index of this skip sector within the second table is added to the LBA to compute the PBA. The PBA is then mapped to a zone, cylinder, head, sector location on the disk drive.

Abstract: Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A "virtual two-port" solution also is described for using single-port memory in the shared configuration with multiple address sources.

Abstract: A data movement apparatus (10) and method therefor include a register file (14) for storing data in a plurality of addressable locations. A register decoder (18) is connected to the register file (14) to modify addresses to access desired data. During move commands, data is not physically moved in the register file (14), but the register decoder (18) modifies a variable upon receiving the move command to correlate the new logical address to the physical location.

Abstract: The present invention relates to methods and devices for generating cycled waveforms of nonsingle period, and more particularly to an improvement from the one-way counter used by conventional cycled waveform generator of nonsingle period into an up-down counter or a programmable up-down counter, along with an adder/subtracter. Thus, only the varied values in waveform relative to a DC level have to be filled into a table, and then the varied values in waveform (i.e. the digital waveform sampling values) are input into said adder/subtracter to obtain a periodic digital values by adding/subtracting with a predetermined DC level. Finally, cycled waveforms of nonsingle period are obtained by digital-to-analog converting of said digital values. With the methods and devices of the present invention, not only the fillings in said table can be decreased to reduce the cost, but also the DC output level can be fixed or adjusted arbitrarily for convenient signal processing.

Abstract: A block storage memory management scheme. According to the disclosed embodiments, a memory list of data is generated from a set of address ranges, a descriptor is created to interact with the memory list, and data is retrieved by preparing the memory specified by the descriptor for an input/output operation, performing the operation, and deleting the descriptor. Memory mappings are delayed as long as possible to enhance the performance of the system, particularly for RAID applications.

Abstract: A method for processing interface messages, such as SCSI messages, using an indexed jump table. Two single-dimensional tables are implemented by the method described. The first table stores index values for all valid sequence instruction locations for which an ATN signal can be detected. The second table stores index values for all valid interface messages. The index values of these two tables are used as entry points to the indexed jump table whose elements contain addresses to message handling functions.

Abstract: A computer system provides enhanced performance when executing irregular code that include pointer de-reference operations. A memory controller of the computer system first fetches a pointer value from an address location in the memory and then calculates a new address adding a constant or scale factor to the pointer value. A logical-to-physical (i.e., virtual-to-physical) translation of the pointer value is also performed. The loading of data for the initial pointer load operation is overlapped with the de-reference operation, wherein the de-reference data is prefetched from memory using the resulting address and placed into the CPU's cache.

Abstract: A display controller for a computer or the like stored display data in a tiled format in a display memory. Tile shape may be dynamically altered depending upon display mode (resolution, pixel depth, or the like) or other display factors. Tile shape (height versus width) may be optimized for different types of display (e.g., video, text, graphics, or the like). A display memory address conversion apparatus may receive pixel position data (e.g., from a BIT BLT engine or the like) and tile shape data and convert pixel position data to a tiled display memory address.

Abstract: A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.