Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up the data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A cache memory apparatus is provided with a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group, an address managment table for managing both an address and a range with respect to the cache memory into which the information is stored, and a selection circuit for selecting the cache memory in response to an access to the address management table. As a result, information related to a system control is stored into the cache memory apparatus.

Abstract: In modifying a program fixedly recorded in a ROM or the like, desired positions in the program can be modified with a little hardware. In order to achieve the object, the program modification device comprises the modifying address register 17 which stores the addresses of program data to be modified prior to the execution of the data and the modifying address storage table 19 which stores all the addresses of the modification source programs to be loaded to the modifying address register 17 and all the addresses of the modification target programs in pairs, and further comprises a modification target program having instructions embedded therein so as to load necessary information from the modifying address storage table 19 to the modifying address register 17 before the program to be modified is executed.

Abstract: A data processing system and method of fetching instructions in a data processing system are described. The data processing system includes at least one execution unit that executes fetched instructions and instruction sequencing logic that fetches instructions from memory. In response to detection of a particular instruction trigger within an instruction stream, the instruction sequencing logic fetches one or more non-sequential blocks of instructions from memory, where each of the non-sequential blocks includes a plurality of instructions.

Abstract: A storage controller executes logical format to enable host access to a physical disk, where the logical format of a physical disk is executed without waiting for host access. The storage controller comprises a logical format management module having bit map memory for managing progress information on format processing of a logical volume, and a lower layer module which accesses a physical disk according to the request of the management module. The management module judges whether all the access areas have been formatted referring to the bit map memory, requests the disk access to the lower layer module if judged as formatted, while, issues a logical format processing request before the disk access, queues the disk access request to the queue if not formatted, further searches the unformatted area from the bit map memory, and issues a logical format processing request if no disk access request exists in the queue.

Abstract: The Internet data defining destinations accessible by a router are partitioned into a portion containing the address search information and a portion containing forwarding option data. The address search information is stored in fast memory in a tree search format and the set of possible next destinations are stored as forwarding option data in slower memory at addresses derived algorithmically from the tree search address information. Internet data packets are received and data therein is compared to determine the best match address in the fast memory to the set of possible best next destinations. The multiple accesses necessary to determine the best match address are confined to high speed memory. An algorithm receives option data from an Internet packet and option threshold data from the best match address of the high speed memory and determines which address of the slower memory has the desired forwarding data using one access.

Abstract: Object oriented processing is performed by holding pointers to memory locations of object variables and method tables in dedicated registers. The pointers for current and previous operations of the processor are held in respective first and second groups of the dedicated registers. For each object, the respective object variables are stored at a memory location and the pointer to a respective method table is stored at a memory location indexed off of the location of the object variables.

Abstract: An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a single instruction stream, multiple data stream (SIMD) system, and the processing elements can be the multiple data paths of the SIMD system. Each processing element or data path is associated with an identifying value which distinguishes it from the other elements. A memory, which can be configured as an interleaved memory including multiple memory banks, stores data accessed by the processing elements. The data can be a table used for table look-ups for such functions as mathematical operations. Also, multiple copies of the table can be stored in multiple respective banks of the memory. An instruction calling for a memory access such as a table look-up is received. The instruction contains address information which can be a starting address of a table in memory.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock because the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: In a secure fast packet switch having a plurality of input ports and a plurality of output ports, a method of determining which port in the plurality of output ports data that is received on one input port in the plurality of input ports is to be sent to, the method including the steps of determining a physical layer address of a sending node, determining a physical layer address of a receiving node, determining an input port in the plurality of input ports that the data was received on, determining if the physical layer address of the sending node and the physical layer address of the receiving node are an allowed combination, determining the magnitude of the node identification number of the sending node, determining the magnitude of the node identification number of the receiving node, obtaining outbound port information from a first predetermined location in a data structure stored in a memory if the node identification number of the sending node is greater than the node identification number of the recei

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent a collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable in a q-bit module address and an (n−q) bit row address in a power-of-two stride fashion. The row address is selected from (n−q) bits of the index address, and the module address for one of the Q accesses is obtained from bitwise exclusive-OR operation on bits obtained from corresponding positions in a plurality of q-bit fields grouped from the index address.

Abstract: To accelerate searching of large file system directories, hashing information for a selected directory is compiled and retained in random access memory prior to a need for access to the directory to satisfy a file access request from an application. No change in the on-disk file system representation is required, nor is there any need for nonvolatile storage of the hashing information. If memory is scarce, the hashing information can be incomplete yet give hints for searching the most-recently-accessed directory entries. In a preferred implementation, the hashing information for a directory includes a hash table for searching for names of objects such as files, subdirectories or links in the directory, and a hash table for searching for free space in the directory.

Abstract: A method and system for updating routes in a route table on a personal computer operatively connected to at least one peripheral device. The method includes the steps of determining whether a first Device Internet Protocol address in a maintenance list is communicating with the client computer, creating a NIC IP list for all Network Interface Card Internet Protocol addresses bound to a Device Internet Protocol address on the client computer when the first Device Internet Protocol address is not communicating with the client computer, and adding a route table entry including the first Device Internet Protocol Address and an Network Interface Card Internet Protocol address from the NIC IP list to the route table.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock because the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A method and apparatus in a data processing system for traversing a plurality of frames for a stack stored sequentially in a memory. A method block associated with a current frame is found. The method block is read to identify an offset to previous frame information in the current frame. A previous frame is located within the plurality of frames using the previous frame information.

Abstract: According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.

Abstract: A data carrier is disclosed for the communication of transmission information to a communication station. In particular, the data carrier includes a program memory for storing a program code including instruction and address information in at least one program code line, a data memory for storing data information, and a processor for processing the communicated transmission information, wherein each program code line address mode information included in the instruction information and the associated address information can be determined/processed to access a memory location of the program or data memory, and includes an address mode extension device, which in the presence of specific address information, determines stored additional address mode information.

Abstract: A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

Abstract: The equivalent computational precision in an associative memory is increased by determining the difference between the bit precision that is required in order to represent a given number in the memory and the bit precision that can be represented in a memory element of the memory, which is dictated by the inherent characteristics of the memory; determining, on the basis of the difference, the number of memory elements of the memory required in order to represent the given number with the required bit precision; and dividing the given number over the number of memory element of the memory, determining a base value to be loaded into the number of memory element and a remainder which indicates a subset of the number of memory element of the memory over which the remainder is to be divided.

Abstract: A file management system is provided which enables the peaceful coexistence of two or more file systems from different applications (12,16) on the same medium (10). Available free space can be assigned to each of the file systems. Static partitioning of the medium in fixed sized parts is not necessary, as partition sizes can be dynamically changed.

Abstract: A method and system for implementing a mirror addressing scheme in conjunction with a symmetrical data table are disclosed. The method includes receiving a first address. In response to determining that the first address corresponds to an upper portion of a data table, generating a second address from the first address, where the second address corresponds to a lower portion of the data table. The method further includes using the second memory address to access a memory array, whereby data corresponding to the upper portion of the data table is accessed from the lower portion of the data table. In one embodiment, determining that the first address corresponds to an upper portion of the data table is achieved by determining upper segment and lower segment boundaries for the first memory address determining that the most significant bit of the lower segment is asserted.

Abstract: A method and system are disclosed for balanced transmitting of data across a link aggregation of k links in a network, where k is not a power of 2, where data is specified by frames each having a source address and a destination address. N bits of the source address and N bits of the destination address are determined to be XORed together where N is greater than 2. An index table with 2N entry positions is created where each of the entry positions is assigned an index number between 0 and 2N−1. The entry positions of the index table are filled with one link of the k links in each entry position by repetitively entering each of the k links until all of the entry positions are filled. The frames of data with identical source address and destination addresses as other frames of data are grouped into a flow. N bits of the source address are XORed together with N bits of the destination address for each flow to obtain an N bit index number for each flow.

Abstract: A method and system for laying out and accessing data in a disk drive system. The layout resides in a table in firmware of the disk drive system. The table includes multiple entries or rows, one corresponding to each different area in the disk media. The entry provides information about the range of block addresses in that area including the starting and end block address in the area, and information about the range of physical addresses including the head and the starting and ending cylinder number. A firmware routine finds the appropriate entry in the table and converts the block address to the physical address, or vice versa.

Abstract: In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based on the memory unit addresses mapped from the bus addresses included in the requests. When desired, a data value from the source memory location is dynamically moved to the destination memory location, and the mappings are updated such that a bus address mapped to a memory unit address identifying the source memory location is instead mapped to a memory unit address identifying the destination memory location.

Abstract: A content addressable memory (“CAM”) engine or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known, commercially-available random access memory (“RAM”) devices. The CAM engine configures the RAM as content addressable memory, thereby causing the normally location-addressed RAM to function as CAM. The CAM engine thus allows for the benefits of both RAM and CAM devices, such as speed, density, cost and intuitiveness, without their inherent drawbacks. Further, the CAM engine implements various flexible memory storage configurations for the keys and associations stored in RAM. Also, the CAM engine implements certain algorithms that provide for the hashing of data, for table load and unload capabilities, for proximity matching, for dealing with overflow conditions, and for implementing hierarchical search capabilities.

Abstract: A novel table look-up/indirect addressing system and method uses a dual fetch Harvard architecture to accomplish one full table look-up access per instruction cycle. The offset access fetch, the indirect data fetch and the table offset and base address addition are all performed during a single cycle. The system and method also accommodate data accesses using packed (half word) offsets.

Abstract: Automated address mapping is achieved by a system and methodology which automatically reacts to changes in the disk configuration. Prior to utilizing the disk, disk configuration information is provided by the user resulting in a stored configuration table. This configuration table is then used to compute an address translation structure which can be later used to perform actual address mapping operations. Utilizing this address translation structure, in combination with appropriate formulas, address mapping from a logical block address, provided by the host computer, to a surface-track-sector address (STSA) is easily accomplished. By having the actual address translations dependent upon the configuration table, the system and method automatically reacts to changes in the disk configuration.

Abstract: A code export symbol offset table A 1128 stores sets of the identifier and the offset of the area of a code symbol. In an export symbol import step 1160, the identifier that matches the identifier of a symbol is retrieved from the code export symbol offset table A 1128, the offset corresponding to the retrieved identifier is extracted, and a predetermined calculation is performed to create an absolute address.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A flexible memory overlaying apparatus and method stores repeatedly referenced information, e.g, common global variables, common code segments, interrupt service routines, and/or any other user or system definable information, in spare addressable circuits accessed by a memory aliasing or overlaying module. The memory aliasing module monitors (or snoops) memory access by a processor to redirect access to certain appropriate addressable circuits to provide faster access to the information than would be available in an access made from main memory. The memory overlaying apparatus and method provides an efficient context switching, e.g., during an interrupt, enables a reduction in the size of instruction code requirements, and helps avoid the occurrences of cache misses, and/or thrashing between cached pages.

Abstract: An electronic pet having reality by various machines is implemented. An IC card stores a matter to be renewed in accordance with an action when an electronic pet takes the action on the basis of an internal status parameter which contains the feeling of the electronic pet and represents the internal status thereof, and it is detachably mounted in a device functioning as the body of the electronic pet. A virtual pet device functions as the body of the electronic pet and performs processing to display the electronic pet, and it has a slot in which the IC card is detachably mounted. A pet type robot functions as the body of the electronic pet, and it has a slot in which the IC card is detachably mounted.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address.

Abstract: A novel table look-up/indirect addressing system and method uses a dual fetch Harvard architecture to accomplish one full table look-up access per instruction cycle. The offset access fetch, the indirect data fetch and the table offset and base address addition are all performed during a single cycle. The system and method also accommodate data accesses using packed (half word) offsets.

Abstract: There is provided a digital recording and reproducing apparatus which is capable of determining whether or not recording data was rewritten, reliably and in a short time period without increasing manufacturing costs thereof. A digital recording and reproducing apparatus is configured to be capable of having a removable external memory mounted therein, for recording recording data in the external memory and reproducing a sound based on the recording data recorded in the external memory. An identification data-generating block generates identification data for use in determining whether or not the recording data was rewritten. An internal memory can record the identification data. A control block records the identification data in the external memory as part of the recording data and at the same time records the identification data in the internal memory such that the identification data is recorded in FAT data concerning the recording data in a manner correlated to a title of a file to be recorded therein.

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generate data forwarding decisions. The address table includes source addresses, destination addresses and data forwarding information. The switch may be configured to generate data forwarding decisions based on two data forwarding models. In the first model, data frames received with unknown source addresses are forwarded and the source addresses are added to the address table. In the second model, data frames received with unknown source address are forwarded without adding information to the address table.

Abstract: The invention provides structure and method for controlling access to a shared storage device, such as a disk drive storage array, in computer systems and networks having a plurality of host computers. A method for controlling access to a hardware device in a computer system having a plurality of computers and at least one hardware device connected to the plurality of computers. The method includes the steps of associating a locally unique identifier with each the plurality of computers, defining a data structure in a memory identifying which particular ones of the computers based on the locally unique identifier may be granted access to the device; and querying the data structure to determine if a requesting one of the computers should be granted access to the hardware device.

Abstract: A system for accessing contents of the directory structure in a computing system having a CPU and implementing indirectly addressable main memory via a first directory structure included in the memory. In this system, CPU generated real memory addresses are translated to one or more physical memory locations using the directory structure. A second directory structure is provided in main memory that includes one or more entries with each entry formatted to provide addressability to a predetermined number of entries in the first directory structure. The second directory structure alternately may access all contents of main memory, and is adaptable as main memory capacity varies. The second directory structure may alternately be implemented as a hardware device which computes the addresses for accessing data in main memory.

Abstract: A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copies to local memory space of a node such that accesses to the data may be performed locally rather than globally. The copies data is referred to as a shadow page. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, the page to which shadow copies may be stored and which global addresses may be converted to local physical addresses may be restricted. Multiple page of local memory space may be allocated to one entry of a local physical address to global address (LPA2GA) table. When a page is allocated to store shadow pages, an entry in the LPA2GA table associated with that page is marked as unavailable.

Abstract: An address match determining device has an address filter memory (22) for storing a matrix or table having a plurality of elements each of which is a 1-bit address match determination data indicating whether or not a corresponding N-bit address code is available, and is distinguished by a pair of a first index composed of the m most significant or high-order m bits of the corresponding address code and a second index composed of the remaining lowest or low-order (N−m) bits of the corresponding address code. A received-address latch (21) extracts the high-order m bits and remaining low-order (N−m) bits from an address code latched thereinto.

Abstract: A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. The address table represents a plurality of bins of address entries. A decision-making engine receives a source address of a frame and a receive port number and searches a particular bin in the address table for a match. When the decision-making engine does not find a match, the switch adds an entry to a particular bin in the address table. A host device may also add entries in a particular bin. In addition, entries may also be deleted from a particular bin.

Abstract: A method is provided for I/O data transfer between memory and disk. In one embodiment, an application program generates N data transfer requests. Thereafter, a data transfer list is created that comprises N entries each comprising a file sector descriptor and a buffer address. The application program is suspended in favor of initiating the operating system. Thereafter, N data transfers are performed, each one of which comprises transferring data between a file sector and a buffer identified by the file sector descriptor and a buffer address, respectively, contained in one of the entries of the data transfer list. On completion of N data transfers, the operating system is suspended and the application program is reinitiated.

Abstract: The present invention relates to a user's database structure in the network and a method of constructing the same, in particular, to a user's database structure and a method of constructing the same in Ethernet. The structure comprises a set of bytes having a plurality of fields, a main storage layer having the set of bytes, a plurality of sub-storage layers having the set of bytes, a plurality of main connection lines and sub-connection lines, to form a database of tree structure. For retrieval of the user's address data, only the main storage layer, the main connection line and sub-connection lines, and the last sub-storage layer are required to retrieve a user's address data so as to save the storage space occupied by the database.

Abstract: Segments of storage of a computer system are shared among any number of users at varying virtual addresses. The virtual addresses can be in the same address space or different address spaces. The sharing of a segment of storage is provided by storing the real address of a page table corresponding to the segment of storage to be shared at different virtual addresses. This allows users of the same or different address spaces to share the same segment of storage by referencing the same page table.

Abstract: A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed. Additionally, a process capability can be changed by altering a setting in this table. As a result, a data processing device that can perform the processes for general-purpose data, such as a stream data process, etc., at high speed, and can flexibly change a capability according to the circumstances.

Abstract: A computer system employing a microkernel executes two different tasks, e.g., operating systems, yet uses common shared libraries. Rather than each task setting up its own libraries, during compile a global offset table is set up for each task so that the tasks can use common shared libraries. An abstractions layer is established to allow the tasks to share the global offset table, and thus to use common shared libraries. Threading package related services are resolved via the abstractions mechanism. This abstractions mechanism includes services implemented as operating system abstractions, and include thread creation, exit from a thread, etc. Abstracted functions utilize pointers to runtime environment-specific functions, and are utilized by the task's runtime environment.

Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.

Abstract: The present invention generally relates to a system and method for a message protocol to extend cache coherence management of scalable shared memory multiprocessing computer systems having a plurality of processors connected to an interconnection over which the plurality of processors communicate with each other. Each processor communicates with other interconnection processors by sending and receiving messages on the interconnection by means of a messaging protocol which can be used for shared-memory computer systems, shared nothing computer systems, and hybrid computer systems in which some processors are sharing memory while others are not. With this invention a processor node is able to tell whether an incoming message is from within the same coherence group (in which case it is completely unprotected) or whether it is from outside the coherence group (in which case the shared-nothing protections apply).

Abstract: A method for searching for a record in a table in a memory of a computer system. A table of records is organized into a group of arrays. A hashing algorithm locates a record in the table. Multiple hashing functions are executed concurrently, according to the number of arrays in the group, such that the record can be located relatively quickly in one of the arrays in the group. The table is analyzed to determine the information content of each bit in a string of bits comprising an index value associated with the table, according to Shannon's formula for information-theoretic entropy. The entropy associated with each bit in the string of bits provides a basis for selecting a subset of bits in the string of bits from which to obtain the seed values utilized in the hashing functions. A rotating mask, based on Neumann's code, is applied to the subset of bits to obtain different seed values for each of the hashing functions, thereby minimizing the correlation of the keys provided by the hashing functions.