Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: Method, system and computer products are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. The re-mapping and interleaving technique ensures unique identification of transport packets associated with multiple transport streams to be multiplexed onto a transport channel for demultiplexing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams.

Abstract: A system and method for managing data updates by cascading those updates through a virtual copy hierarchy from parent copies to child copies are provided. Virtual copies are created and managed through the use of an instant copy mechanism. Metadata subsets manage both the original data and the copies created by the instant copy mechanism. With an exemplary embodiment of the system and method, changes made to one copy of the data are cascaded to all child copies of the data. In this paradigm not only is the metadata entry for one particular copy changed, but also the corresponding metadata entries of any copies descended from that copy. In an exemplary method, a tree structure is used to maintain a record of all metadata table subsets created by use of an instant copy method. The tree structure can then be searched to find all child copies of a particular copy.

Abstract: A method and apparatus are provided for an efficient lock-free, non-blocking hash table. Under one aspect, a linked list of nodes is formed in the hash table where each node includes a protected pointer to the next node in the list and a reference counter indicating the number of references currently made to the node. The reference counter of a node must be zero and none of the protected pointers in a linked list can be pointing at the node before the node can be destroyed. In another aspect of the invention, searching for a node in the hash table with a particular key involves examining the hash signatures of nodes along a linked list and only comparing the key of a node to a search key of the node if the hash signature of the node matches a search hash signature.

Abstract: A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts. The mechanism is placed between a processing element and a memory system such that write data is buffered and both reads and writes are recorded. When a memory conflict is detected, based on a strict or alternate ordering model, a restart signal is generated and the entries for the associated sequence number are flushed. When the work associated with a sequence number has completed, a signal is made so that associated write data can be sent to the memory system and the entries for that sequence number can be flushed.

Abstract: Provided are methods and systems for controlling the conversion of data inputs to a computer-based light system into lighting control signals. The methods and systems include facilities for controlling a nonlinear relationship between data inputs and lighting control signal ouputs. The nonlinear relationship may be programmed to account for varying responses of the viewer of a light source to different light source intensities.

Abstract: A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system operates on larger, second-sized virtual memory pages. In an embodiment GART driver software maps each virtual page to Z continuous or non-contiguous real pages by filling up the GART with Z entries per virtual page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a target address, corresponding to an address within a virtual page, issuing from a processor into a second address, corresponding to a base address of a real page in main memory. Also described are an integrated circuit and a computer-readable medium to map memory pages of disparate sizes.

Abstract: A method and apparatus for managing a dynamic alias page table are provided. With the apparatus and method, alias page table entries are added to an alias page table dynamically by determining if the alias page table has space for the entry and, if so, the entry describing the virtual address to physical address mapping is added to the alias page table and a successful completion is returned to the virtual memory manager. If the alias page table does not have space for the entry, a new page is used to map the next virtual page of the alias page table. This page must be marked as a fixed page if it not so marked already. This page is pinned in the software page frame table, and the hardware page table entry for this page is also pinned.

Abstract: A routing table circuit for a router has one or more input ports and output ports for message communication. In the routing table circuit, one or more routing table memories store a plurality of routing table arrays. The routing table arrays are arranged hierarchically in levels, and each routing table array is associated with a predetermined subset of prefixes. Each routing table array has entries. The entries include a block default route pointer field to store a block default route pointer, if any, and a routing field. The route engine may access any level of table array by using a next level route pointer stored in the routing field. Using the block default route and the routing field, the present invention further reduces the number of memory accesses and the update cost for route insertion and deletion by identifying and skipping elements that do not require route updating.

Abstract: A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: There is disclosed a method and apparatus for mapping between logical and physical addresses in a solid state data storage device, particularly but not exclusively a magnetic random access solid state data storage device, in which a list of mappings between ranges of logical addresses and ranges of physical addresses are stored in a data table, the mappings being operated on to look up a physical address from a logical address and vice versa, and being operated on by a data processor, to amend the data mappings by introduction of new ranges of logical and physical addresses, upon ranges of individual physical memory elements becoming defective.

Abstract: A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node, accessing a local connection table at the local node using the connection descriptor to produce a system node identifier for a remote node and a remote address space number, communicating the virtual address and remote address space number to the remote node, and translating the virtual address to a physical address at the remote node (qualified by the remote address space number). A user process running at the local node provides the connection descriptor and virtual address. The translation is performed by matching the virtual address and remote address space number with an entry of a translation-lookaside buffer (TLB) at the remote node. Performing the translation at the remote node reduces the amount of translation information needed at the local node for remote memory accesses.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: A remote translation mechanism for a multi-node system. One embodiment of the invention provides a method for remotely translating a virtual memory address into a physical memory address in a multi-node system. The method includes providing the virtual memory address at a source node, determining that the virtual memory address is to be sent to a remote node, sending the virtual memory address to the remote node, and translating the virtual memory address on the remote node into a physical memory address using a remote-translation table (RTT). The RTT contains translation information for an entire virtual memory address space associated with the remote node.

Abstract: A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit incrementable validity counter. The target associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the target processor when access to a given page in main memory is sought. Each entry in the target associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. The target multi-digit counter stores a current validity count.

Abstract: The present invention provides an architecture and method for increasing the performance and resource utilization of networked storage architectures by use of hardware-based storage element mapping. The architecture utilizes a customized programmable processing element to map host read or write commands to physical storage element commands. The present invention uses a plurality of data structures, such as tables, to map host read and write commands to physical storage elements. The hardware-based storage element mapping controller uses the tables, including a mapping segment descriptor table, to map from global address space addresses to physical storage element addresses.

Abstract: A table management method allowing efficient hash search with suppressing the possibility of occurrence of rehashing is disclosed. A MAC address table is divided into a plurality of banks, which are simultaneously accessed according to a hash output. Each of registered MAC addresses read out from respective ones of the banks is compared to the input MAC address. When a match is indicated by at least one comparison result, the input MAC address is judged to have been registered in the MAC address table. When no match is indicated by all comparison results, the input MAC address is judged as a new MAC address. If an available memory area is left in memory space of the banks concurrently accessed according to the hash output, then the new MAC address is registered in the available memory area.

Abstract: The preferred embodiments described herein provide a method for making a write-once memory device read compatible with a write-many file system. In one preferred embodiment, a method for re-writing to a logical address of a write-once memory device is provided. A physical-to-logical address map is built from data stored in the memory device that associates individual physical addresses with individual logical addresses. When a logical address is re-written, data associating that logical address with a new physical address is stored, and data associating that logical address with an old physical address is invalidated. When the logical address is read, the physical-to-logical address map is used to read the new physical address instead of the old physical address. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract: An IC card having nonvolatile and volatile memory is disclosed. An IC card generates a volatile object, and accesses the volatile object using a reference address on a nonvolatile memory. These volatile objects are dynamically generated. The objects are allocated addresses in order from volatile objects with shorter terms to volatile objects with longer terms, so as to allow garbage collection and reuse of a volatile memory.

Abstract: A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identifiers initiates I/O requests directed to a device that is able to address a different, first memory space using first identifiers, which are represented using a second number of address bits. The second identifiers are initially mapped into the second memory space, but for any I/O request that meets a remapping criterion, the corresponding second identifier is remapped to one of the first identifiers that identifies a portion of the memory in the first memory space. The second space is different from the first space and the second number of address bits is greater less than the first number of address bits.

Abstract: Aspects of the invention include a method and apparatus to transfer specific data files from a disc drive storage system to an output device such as a printer. In one aspect, the disc drive uses a transfer protocol that determines the files stored from a peripheral device and sent to the output device. In another aspect, the transfer program compares the files sent to the output device to a file structure stored on the disc drive and presents the unsent files to the output device for processing.

Abstract: A data table includes a source pointer indicating a starting address of drawing data, a destination pointer indicating a destination of drawing data to be transferred, and a data length indicating a data length of drawing data to be transferred. Data table may indicate drawing data to be drawn. Thus frames may share drawing data. As such the amount of drawing data can be reduced.

Abstract: A data processing device includes a read-only memory, a flash memory capable of modifying information stored therein and adding information thereto, a central processing unit performing data processing using information stored in the read-only memory and the flash memory, an information storage area provided in the flash memory for storing predetermined modifiable information among the information used by the central processing unit for data processing, an address storage area provided in the flash memory for storing at least the address of information stored in the information storage area, and an address-modification control unit for, after at least one of modification of modifiable information stored in the information storage area and addition of modifiable information to the information storage area is performed, performing modification of the address of the information stored in the address storage area.

Abstract: A data processing system providing high performance two-dimensional and three-dimensional graphics includes at least one system processor, chipset core logic, a graphics processor, main memory storing computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized memory pages, while the operating system operates on larger, second-sized memory pages. In one embodiment GART driver software maps each second-sized page to Z first-sized pages by filling up the GART with Z entries per second-sized page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a first page number, corresponding to a first-sized page, issuing from a system processor into a second page number, corresponding to a second-sized page, and a page offset within the second-sized page.

Abstract: A data selection apparatus which performs selection processes in parallel is provided. The data selection apparatus includes search units and a unit output control device. Each of the search units includes table search circuits and a data output control circuit which selects the highest priority output data. The unit output control device selects the highest priority output data from outputs of the search units. A table search circuit which succeeds in a search sends a search success signal to the data output control circuit. The search unit including the data output control circuit sends a unit search success signal to the unit output control device before performing a selection process for the highest priority data.

Abstract: In the method of generating an interleaved address, each 2^i mod (p?1) value for i=0 to x?1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and x is greater than one. An inter-row sequence number is multiplied with a column index number to obtain a binary product. Both the inter-row sequence number and the column index number are for the block size K and the prime number p. Then, each binary component of the binary product is multiplied with a respective one of the stored 2^i mod (p?1) values to obtain a plurality of intermediate mod value. An intra-row permutation address is generated based on the plurality of intermediate mod values, and an interleaved address is generated based on the intra-row permutation address.

Abstract: A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

Abstract: A method is provided to allow a system administrator of a utility storage server to provision virtual volumes several times larger than the amount of physical storage within the storage server. A virtual volume is a virtual representation of multiple disks as a single large volume to a host or an application. In one embodiment, a virtual volume comprises an exception list containing the set of differences from dummy base volume consisting of all zeros. This exception list can be made up of address tables that map virtual volume pages to logical disk pages. As storage demand grows, additional storage is allocated for the address tables and the data pages from separate pools of storage. If any of the pools runs low, more logical disk regions are allocated to that pool.

Abstract: An encoder and decoder provide coding of information communicated on busses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.

Abstract: An apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the transmit and receive data paths. The second circuit may be configured (i) to transfer the data between the transmit and receive data paths and a second interface and (ii) to control a configuration update of the first and second circuits in response to a plurality of control signals. The configuration of the first and second circuits is generally dynamically updated.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various physical locations, and a relocation table is created with entries used to locate these blocks. To access memory for a particular piece of data, a program first uses a virtual address of the data, which, through a translation look-aside buffer, is translated into a physical address within the computer system. Using the relocation table, the physical address is then translated to a relocation address that identifies the relocation block containing the requested data. From the identified relocation block, the data is returned to the program.

Abstract: A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single logical register file. The first set of instructions appears to access the single logical register file as a flat register file. In addition, a first instruction of a second instruction type operates on the logical register file. However, the first instruction appears to access the logical register file as a stack referenced register file. Furthermore, sometime between starting the execution of the first set of instructions and completing the execution of the first instruction, all tags in a set of tags indicating whether corresponding registers in the single logical register file are empty or non-empty are caused to indicate non-empty states.

Abstract: A method and structure for a “dynamic CCR/sparse directory implementation,” includes maintaining state information of the main memory cached in the shared caches of the other compute nodes, organizing a cache directory so that the state information can be stored in a first area efficient CCR directory format, switching to a second sparse directory format if the entry is shared by more than one other compute node, and dynamically switching between formats so as to maximize the number of entries stored in the directory.

Abstract: A memory system having a semiconductor storage device divided into plural areas, in which information becomes accessible by specifying an absolute physical address, and a control section for controlling the semiconductor storage device is provided. The control section receives a designating signal for designating one area out of the plural areas of the semiconductor storage device and a relative physical address independent by each area and specifies the absolute physical address by adding an offset address corresponding to the area designated by the designating signal to the relative physical address so that the semiconductor storage device is accessed.

Abstract: A digital data storage system comprises a storage device, a descriptor memory and a control device. The storage device stores a series of records, the records being organized in a plurality of tracks, each track being associated with one of a plurality of cylinders. The descriptor memory stores a descriptor associated with storage device. The descriptor contains selected information relating to the records stored by the at least one storage device. Each descriptor includes a plurality of cylinder portions each configured to store selected information relating to a respective one of the cylinders in the storage device. Each cylinder portion, in turn, includes a plurality of track descriptors each configured to store selected information relating to a respective one of the tracks in the respective cylinder. The storage device also stores the descriptor associated therewith, the cylinder portions of the descriptor being augmented with additional information relating to the respective ones of the cylinders.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: According to one embodiment, a CAM system (100) may include a comparand register (CMPR) index block (106) for monitoring a status of comparand registers within the CAM blocks (104). A CMPR index block (106) may include a free index register set (120). A free head pointer (122) and a free tail pointer (124) can point to a start and end of a list of free comparand index values stored within a free index register set (120). A CMPR index block (106) may also include a busy index register set (126). A busy head pointer (128) and a busy tail pointer (130) can point to a start and end of a list of busy comparand index values stored within a busy index register set (126).

Abstract: A router allowing the entry hit probability of the cache to be increased is disclosed. The cache is searched using a different mask for each cache entry. A maximum or optimum cache prefix length is determined as a length of upper bits of the destination address of the received packet which are not masked by a corresponding mask. Alternatively, the cache is searched using longest prefix match (LFM). A cache entry allowing a plurality of destination addresses to be hit can be registered in the cache, resulting in increased cache hit probability.

Abstract: A method and software for managing memory are provided in which objects residing in session memory are formatted so the references contained in the objects are in a machine-independent format, namely, that the references are encoded numerically. An exit table is provided to handle references with session memory that refer to locations in call memory, in which each entry in the exit table is associated with a corresponding reference in session memory and contains a pointer to the location in call memory.

Abstract: A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register.

Abstract: A system, method and computer readable medium for deferring copy-on-write of a snapshot is disclosed. The method includes the generation of snapshot of a source file. Upon modification of a first data block referenced by the source file, the first data block is referenced by the snapshot and a second data block is allocated for the source file. Then, a first variable associated with the source file is set to a value indicating an incomplete source file data block and a second variable associated with the source file is set to a value indicating the valid portion of the second data block. Any portion of the second data block that is overwritten is considered valid. The second data block is then modified and the second variable is changed to reflect the modification. Upon reception of a read request, the corresponding portion of the second data block is retrieved.

Abstract: A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.

Abstract: There is disclosed a method and apparatus for mapping between logical and physical addresses in a solid state data storage device, particularly but not exclusively a magnetic random access solid state data storage device, in which a list of mappings between ranges of logical addresses and ranges of physical addresses are stored in a data table, the mappings being operated on to look up a physical address from a logical address and vice versa, and being operated on by a data processor, to amend the data mappings by introduction of new ranges of logical and physical addresses, upon ranges of individual physical memory elements becoming defective.

Abstract: A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region. Requests for memory are mapped at least once, for example from virtual to physical page numbers. The I/O requests are conditionally remapped to pages in the first region as a function of how often they are involved in the I/O operations and would normally otherwise need to be copied. Remapping may also be made conditional on a function of availability of memory in the first region. In a preferred embodiment of the invention, the I/O requests are initiated by a subsystem within a virtual machine, which runs via an intermediate software layer such as a virtual machine monitor on an underlying hardware and software platform. A typical application of the invention is DMA.

Abstract: Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.

Abstract: An application program (6) may issue a file access request to an operating system (4) accompanied by a caching hint. This caching hint may be selected in dependence upon the file type and file size of the computer file to which access has been requested. The data defining which hint type is to be used for each combination of file type and file size may be adaptively updated depending upon measured performance for the different hint types. The hint defining data may be initialised in dependence upon the operating system version and the installed memory size of the computer system concerned.