Abstract: An apparatus for reproducing digital signals recorded on a disk having first and second recording surfaces. The digital signals are in the form of a data frame including a lead-in block and n data blocks. The lead-in block has a same format as the n data blocks. n block addresses are assigned to the n data blocks. Information identifying an area on the disk in which the n data blocks is recorded is assigned to the n data blocks. m data blocks (0<m<n) are recorded on the first recording surface, and remaining (n−m) data blocks are recorded on the second recording surface. The lead-in block is recorded at the head of the data frame, and includes information identifying an area on the disk in which the lead-in block is recorded, a number of recording surfaces, the block address of one of the m data blocks recorded last on the first recording surface, and the block address of a last one of the n data blocks in the data frame.

Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Abstract: As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by “vertical transistors” in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Abstract: A method of providing maintenance for a memory device of a computer system without interrupting operation of the computer system, by partially mirroring a primary memory array in a secondary memory array, wherein the secondary memory array has a different amount of available memory than the primary memory array. Values are copied from the primary memory array to the permanent storage device, allowing the primary memory array to quiesce and be serviced while using the secondary memory array to operate the computer system. Thereafter, the primary memory array is brought on-line, and the mirrored values are written back from the secondary memory array to the primary memory array. The memory service program itself may be embedded in the operating system. In an illustrative embodiment, the primary memory array is located on a first removable memory card, and the secondary memory array is located on a second removable memory card. The amount of memory available in the secondary memory array may be programmable.

Abstract: An IC memory card having an expanded function of transmitting and receiving special data other than preservative data. The IC memory card comprises an odd attribute control circuit for outputting a control signal for an odd-numbered address area of an attribute memory, a data storage circuit capable of transmitting and receiving the data other than preservative data to and from the odd-numbered address area of the attribute memory, a signal selection circuit for selecting signals for accessing the data storage circuit, and a special operation circuit which operates in accordance with data stored in the data storage circuit.

Abstract: A data processing apparatus is described which comprises a microprocessor having data lines, address lines and control lines, a memory interface having input control lines, input address lines, output control lines, and output I/O lines wherein one or more input address lines of the memory interface are coupled to an equal number of address lines of the microprocessor. Further, a memory having control lines and I/O lines is provided, the control lines of the memory being coupled to output control lines of the memory interface, and I/O lines of the memory being coupled to output I/O lines of the memory interface. The memory receives command, data and address information through the I/O lines.

Abstract: A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to achieve wide data paths and to support a high number of memory devices, such as dynamic random access memory devices, per data bus. The packet protocol is defined to compensate for the delay stages of the pipelined memory subsystem in order to optimize the access time of the memory devices.

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus.

Abstract: The present invention relates to a memory interface controller for a data transmission system. A memory interface controller is capable of randomly accessing a memory using an associative memory and variably processing data using an extended memory. There is provided a memory interface controller which includes a control logic unit for selectively outputting signals; a comparand register for storing a sequence number; an associative memory for outputting a match address; a priority address encoder for outputting a priority match address; an external memory controller for outputting an empty address of the associative memory; an external tended memory controller for outputting a priority empty address; and an extended memory address and control signal generator for generating an address and a control signal (enable/read/write).

Abstract: An information processing device has a plurality of processors each having a register file formed on a single semiconductor chip. A virtual register in one processor and an extension register in the other processor are connected directly through an exclusive data transfer bus to directly execute data read/write operations between these virtual and extension registers. For example, each virtual register and extension register has a 32 bit width and data transfers between these registers are performed in parallel. These fixed connection wires directly connected between these registers are formed during fabrication processes.

Abstract: A memory extension mechanism for a computer printer or other computer output device. The mechanism allows the computer printer to function with less than the maximum amount of real memory normally required by the computer printer in processing a print job. When the computer printer runs low on the amount of memory available, a portion of real memory of the printer containing infrequently used data is copied through a network to a computer's file system storage. The portion of the real memory containing the infrequently used data is then cleared and made available for other uses by the computer printer. When the piece of memory that was previously copied through the network is subsequently needed, it is copied through the network back into the computer printer's real memory.

Abstract: A method and apparatus for extending an on-chip processing device's access to memory are accomplished by depositing a processing circuit, memory, and configuration circuitry on a die. When the memory has sufficient digital storage capabilities for the processing circuit, the configuration circuitry directly couples an address bus and data bus between the memory and the processing device. When the memory does not have sufficient digital storage capabilities for the processing circuit, the configuration circuitry reconfigures the memory. In additional, the configuration circuitry extends the address bus to an external memory and combines the internal data bus with an external data bus. Configured in this manner, the processing device can access both the on-chip memory and the external memory as a single addressable memory, thereby increasing the memory available to the processing circuit.

Abstract: A synchronous SRAM comprising an SRAM core having a memory array of a plurality of bytes, having a plurality of byte write drivers, having sense amplifiers, and having I/O buffers; a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array during a write operation; a plurality of data inputs organized into bytes; a byte write enable input; a plurality of byte write inputs; and byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs.

Abstract: A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal.

Abstract: An IC card includes a card body, a memory section buried inside the card body and adapted to store data information and control information, and an interface section. The interface section inputs the data information to be stored in the memory section and outputs the data information stored in the memory section. The interface section also outputs the control information stored in the memory section. The memory section stores control information including card maker identification information to be reported to the outside. Therefore, it becomes possible to automatically identify the maker of each IC card, so that the IC card, the IC card reading/writing apparatus, etc., can be procured from multiple vendors when an IC card system is constructed.

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: A method and system in accordance with the present invention provides additional addressable space on a disk for use by a host processor using a virtual data storage subsystem. The method and system includes defining at least one of a plurality of extended image devices on a disk and requesting an instant image to be addressed to an extended image device utilizing channel command words by a host processor. The method and system also includes reading the instant image utilizing commands, such as channel command words or common descriptor blocks, by the host processor. In a method and system in accordance with the present invention, a plurality of extended image devices are defined as extensions of a primary functional device. Data may be transferred between at least one of the plurality of extended images and the primary functional device, or between at least one of the plurality of extended image devices and another of the plurality of extended image devices.

Abstract: A method for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data. The method uses an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the method to access graphics data pointed to by the selected virtual register.

Abstract: A data transmission device which can read information on an IC card without changing a structure of a conventional floppy disc drive is provided. The IC card includes memory elements for storing information therein. The IC card is accommodated in the data transmission device and the data transmission device is attached to the floppy disc drive so that data stored in the IC card is read via the floppy disc drive. The IC card is electrically connected to the data transmission device. A magnetic head core unit of the data transmission device is magnetically connected to a magnetic head of the floppy disc drive so as to transmit data to the floppy disc drive via the magnetic head. A waveform of data read from the IC card is changed to a waveform which is conformable to a reproduction characteristic of the floppy disc drive.

Abstract: Dynamic random access memory with variable configuration depending on the number and capacity of standard memory modules, of DIMM type plugged into a first plurality of slots of a memory motherboard comprising a control unit, into which it is possible to plug, into the first plurality of slots, in substitution for the memory modules, expansion supports, in turn provided with a second plurality of slots for the insertion of standard memory modules of DIMM type, and of column address latch registers each associated with a slot of the second plurality and thereby to support and allow the configurability and operability of interleaved-block memory, and access cycles, with partial time overlap, without renouncing the use of commercially available DIMM memory modules and without burdening the basic memory configuration with all the overheads required to support the interleaved-block configuration.

Abstract: A data processor capable of accessing data with the data processing capacity of a central processing unit (CPU), even if the data processing capacity of the CPU within the data processor is larger than the data output capacity of the memory storing the data.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

Abstract: A method and apparatus for automatically reclaiming and restoring memory occupied by redundant software components. In a computing environment which permits applications to run in the real-mode as well as the protected-mode, only one set of software components, either real-mode or protected-mode can be active at any one time. Protected-mode applications cooperate with a real-mode applications to remove and reclaim the memory occupied by redundant software components such as device drivers when the protected-mode applications boots. The real-mode software components are restored and replaced in memory when the protected-mode application quits. The memory reclaimed from redundant software components contributes to the maximum amount of memory available for use by both protected-mode applications, and real-mode applications.

Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Abstract: In this invention, data track of a magneto-optical disc is divided into a volume management area and an extent area to record data of file into the extent area, and to record directory management information and file management information into the volume management area. The volume management area is caused to consist of 32 clusters. Data allocation unit of the volume management area is caused to be 2 k bytes and data allocation unit in the extent area is caused to be 8 k bytes. Relative recording location within the volume management area of sub directory is recorded, as directory information, into the volume management area. Thus, this invention can quickly carry out access.

Abstract: A method for decreasing the size of a root partition on a computer system operating under control of a UNIX type operating system without reinstalling the operating system. The computer system includes a first storage device. The first storage device includes the root partition which has a first size. The root partition includes a root file system. The method includes backing up the root file system to a backup file system, booting the computer system to a maintenance mode, deactivating the root partition, activating the root partition at a second size smaller than the first size, and restoring the root file system from the backup file system.

Abstract: An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

Abstract: A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field operations. Additionally, such a system advantageously provides a processor which does not include an original bit field instruction set with the ability of performing bit field operations. Such a system also advantageously avoids difficulties involved in encoding bit field instructions.

Abstract: A method and apparatus for reducing processor response time to selected transfer instructions in an instruction processor using a plurality of memory banks including four banks in a basic mode and one memory bank in an extended mode. This invention provides fast transfer hardware to improve the response time by a speed up transfer for normal extended mode transfer instructions only. The bank descriptor of the instruction is used to determine appropriate transfer instructions which are then tested for characteristics indicating whether a fast transfer is possible. The fast transfer process requires fewer checks than the previous apparatus which accelerates the response to selected transfer instructions by one cycle.

Abstract: An I/O adapter connects an I/O adapter to an I/O bus and includes a device interrupt status register and an interrupt status shadow address register. The device interrupt status register stores the interrupt status of the I/O adapter. The I/O adapter accesses the interrupt status shadow address register to determine an address of main memory at which the device interrupt status register is shadowed. After shadowing the interrupt status, the I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status. A multifunction I/O adapter permits a plurality of I/O adapters to be connected thereto and includes a function interrupt status register to summarize the interrupt status of all the I/O adapters attached thereto. After shadowing the summarized interrupt status, the multifunction I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status.

Abstract: A method and apparatus for assisting garbage collection process within a Java virtual machine are disclosed. A virtual object heap and a physical object heap are provided within the Java virtual machine, with the virtual object heap considerably larger than the physical object heap. Objects from Java applications are allocated within the virtual object heap. Each address of the allocated objects within the virtual object heap is translated into an address of a location within the physical object heap. Garbage collection is performed in the virtual object heap only when a total number of objects within the virtual object heap has reached a predetermined threshold.

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise.

Abstract: An output apparatus automatically selects one of a plurality of interfaces and ensures receiving buffers corresponding to the interfaces. Data is taken through each interface into the corresponding receiving buffer and the device is controlled to change sizes of the receiving buffers in accordance with conditions of selection.

Abstract: Electrical circuit (5) arranged to move data blocks from a source memory unit (8, 9, 12) to a target memory unit (9, 12, 8) by a data path (5, 6, 7), to send, in a given order, requests to read blocks in the source memory, to generate an end marker in the request to read the last block of the source memory, to receive the blocks read, in the form of response messages, in the order in which the requests were sent, and to send requests to write the received blocks, in the target memory, during receiving of response messages until receiving a message from the source memory with the end marker.

Abstract: A data processing system has a processing unit and a memory which provides a common pool of physical storage. This storage is initially assigned as either main storage or expanded storage during power on. Subsequent to the initial assignment, storage assigned as main storage or expanded storage may be unassigned and thus returned to the common pool. Once returned to the common pool, the storage may be reassigned as either main storage or expanded storage. The storage reassignment is done dynamically without requiring a reset action and transparent to the operating system and any active application programs.

Abstract: A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of translation units, a future file, a central window, a plurality of functional units, a result queue, and a plurality of physical registers. The floating point unit receives speculative instructions, decodes them, and then stores them in the central window. Speculative top of stack values are generated for each instruction during decoding. Top of stack relative operands are computed to physical registers using a register map. Register stack exchange operations are performed during decoding. Instructions are then stored in the central window, which selects the oldest stored instructions to be issued to each functional pipeline and issues them. Conversion units convert the instruction's operands to an internal format, and normalization units detect and normalize any denormal operands.

Abstract: In response to an extension request to a shared memory file 104, shared file adding means 111 allocates an (additional) memory file 110; inter-host locking means 103 locks a hash table 106; hash table updating means 108 checks the number of data blocks in the (additional) shared memory file, and updates the hash table 106 to alter one of the data block addresses, out of those stored in entries in the hash table 106, pointing to the same data block in the shared buffer 104 so as to point to a data block in the (additional) shared memory file 110; and the added shared memory file 110 is thereby made available for shared use.

Abstract: A microcontroller with a page zero mode where a memory address space is restricted to one page of a multiple page address space to produce improved performance. Address mapping logic and memory segment selection logic limits addresses to the least significant 16 bits of a possible 24 bit address. Different or alternate microcode program controlled instruction sequences with eliminated high order address clock cycles are used in the page zero mode.

Abstract: A synchronous SRAM module comprises first and second SRAM chips. Each SRAM chip has three chip enable inputs. A module enable and memory selection circuit is coupled to the two SRAM chips to perform the dual tasks of (1) selectively enabling or disabling both SRAM chips and (2) choosing either the first or second SRAM chips for access. The SRAM module can also be placed in a pipelining mode where external signals from a microprocessor are ignored to facilitate internal operation, such as burst reads. A synchronous burst SRAM device employed in the SRAM module is also described.

Abstract: A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis.

Abstract: In the case of a process for changing an electronic memory for use-related data of a vehicle, the changed new data and the old data maintained in the memory are sent to a comparator, in which case the comparator permits the taking-over or acceptance of the new data into the memory only if the new data have changed in comparison to the old data in a manner which conforms with the use of the data.

Abstract: Flat-model, 32-bit, real-mode execution may be obtained in an INTEL.TM. X86-compatible processor of a computer to increase address space, while handling interrupts transparently. A protected-mode operating system is not required. A LOADALL instruction available to an operating system may load hidden cache descriptor registers of a processor with the base addresses, segment limits, and other attributes consistent with 32-bit, real-mode operation to provide 32-bit addressing. Interrupts, would normally interfere with the contents of the hidden cache descriptor registers. A new interrupt vector table is provided, with each new vector therein pointing to one of the new interposer routines provided. Upon receipt of an interrupt, a new interrupt vector points to an interposer routine, which saves the state of the hidden cache descriptor registers.

Abstract: An improved microcomputer has a page register connected to a program counter in order to extend the program address range of the microcomputer. A page stack is connected to the pager register and operates in conjunction with an address stack. The page register is loaded from bits in the first word of a two word branch or call instruction in such a manner that no additional execution time is required nor are any additional instructions required to provide the extended address range. A predefined microprocessor ASIC cell is augmented by externally connecting a page register and an opcode decoder so that instruction memory address range can be expanded by paging without redesigning the microprocessor cell.

Abstract: A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU) cache. The computer system contains an I/O bus connected to I/O devices and an expansion bus connected to expansion memory devices, a system memory not accessible via the I/O bus or expansion bus, and the system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory. The I/O bus supports data transfers between pairs of I/O devices, and I/O devices and expansion memory devices on the expansion bus, as well as data transfers between individual I/O devices and the system, which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device or expansion memory device to a cacheable memory location in another I/O device or expansion memory device.

Abstract: Interface processor (IP)(50) sends and receives data units to and from an external host and a processor. The IP is capable of simultaneous, full duplex operation via high speed serial and parallel interfaces. The IP provides a highly flexible and configurable interface which is capable of interfacing to a variety of systems with minimal external hardware. The IP also provides a method of converting received data into data packets. The IP provides buffering of multiple data packets for use in systems having "bursty" data traffic. The IP has a memory expansion capability allowing for changeable buffer capacities.

Abstract: The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.

Abstract: A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Abstract: A multischeme memory management system for large memory computer systems which combines traditional hardware based memory management with a versatile software based memory management scheme. The memory management system includes a conventional memory handler implemented in hardware for managing memory addresses below a fixed limit, for example four gigabytes; and a plurality of memory handlers implemented in software for managing memory addresses greater than four gigabytes. A programmable memory range detectors is associated with each software implemented memory handler. Memory handlers are selected by addressing the different memory address ranges programmed into the memory range detectors.

Abstract: A computer bridge processes transactions in a computer system that includes a system memory. The bridge includes a first address decoder that allocates address space to the system memory according to a first allocation scheme and, in response to receiving transaction requests, directs the transaction requests to the system memory according to the first allocation scheme. The bridge also includes a second address decoder that allocates address space to the system memory and to a selected target device according to a second allocation scheme. In response to receiving transaction requests, the second address decoder directs the transactions requests to the system memory and the selected target device according to the second allocation scheme.

Abstract: A data reading testing method of a microcomputer loaded with a PROM being conducted under a normal operation mode. Setting the operation mode of the microcomputer to a ROM-less mode. Setting the externally extended function under the ROM-less mode. Diverging addresses to an externally extended region. Setting the microcomputer to the normal operation mode, upon which a CPU is to fetch instructions being previously provided to applicable addresses of the externally extended region, and to read the data from the PROM. Reading the data from the PROM. Evaluating the read data and terminating the reading test.