Abstract: Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.

Abstract: A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration source storage, and an external volume. After destaging all dirty data accumulated in the disk cache of the migration source storage to the external volume, an expansion device for virtualizing the external volume is mapped to the migration destination logical unit.

Abstract: An approach is provided for providing persistent computations. A persistent computation manager determines at least one non-volatile memory space of a device. The persistent computation manager also determines at least one other non-volatile memory space of at least one other device. The persistent computation manager further determines to form a persistent memory address space based, at least in part, on the at least one non-volatile memory space and the at least one other non-volatile memory space.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: In a computing system having virtualization software including a guest operating system (OS), a method for providing page tables that includes: providing a guest page table used by the guest OS and a shadow page table used by the virtualization software wherein at least a portion of the guest page table and the shadow page table share computer memory; wherein: machine pages have a predetermined size; and the virtualization software maps guest OS physical pages to machine pages at a predetermined alignment.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: A registered dual in-line memory module is configured with multiple random access memory chips and a DRAM register configured to receive address and control signals from a memory controller. The DRAM register distributes the address and control signals to the random access memory chips, thereby providing the memory controller access to the chips. The module further includes a control register configured to store control bits for setting operating modes of the registered dual in-line memory module. The control bits are software programmable using signals received from the memory controller.

Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: It is recognized that an attached USB memory is an unanalyzable USB memory. Then, disconnect setting is made. A USB connection process is performed. A PC is instructed through a connection line to establish USB connection. The PC recognizes that the attached device is a USB-connected MFP. The PC acquires data control information of the MFP. The MFP then transfers, through the connection line, the data control information output from the USB memory.

Abstract: Supporting limited address mode memory access involves receiving a write request from the processor targeted to a first predetermined address. A data portion of the write request includes a target address of the system memory. In response to determining the write request is targeted to the first predetermined address, the target address is sent via a system interface to be stored in a configuration register of the processor director. A memory access request targeted to a second predetermined address is received from the processor. In response to determining the memory access request is targeted to the second predetermined address, the target address is retrieved from the configuration register of the processor director. The memory access is serviced using the target address retrieved from the configuration register.

Abstract: A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: The present invention discloses an electronic device using a memory to expand storage capacity, and the device includes a main board and a data storage module. The main board includes at least one interface card slot, and the data storage module includes at least one storage interface card, and a plurality of memory slots disposed on the storage interface card for movably inserting a memory. The memory is for storing data, and the storage interface card is inserted into the interface card slot. With the memory slot on the storage interface card, the memory can be expanded conveniently, and the storage capacity can be increased dynamically as needed. The invention also enhances the security, performance, and vibration resisting function of the data storage.

Abstract: Apparatus and methods for full address resolution in a zoning SAS expander. A single memory circuit is used in a zoning SAS expander to store zone information associated with the SAS address (e.g., WWN) of devices exchanging information through the expander. The source and destination addresses in a received SAS frame are used as inputs to the memory circuit to generate outputs of the memory circuit representing the source and destination zone group identifiers. These outputs are then applied to the zone permission table to determine the zoning permission for forwarding the frame through the expander. Pipelined logic within the expander sequences the operations of the memory circuit and the zone permissions table to account for clock cycle delays in processing of each. In one exemplary embodiment, the memory circuit is a content addressable memory (CAM). In another exemplary embodiment, the CAM also includes port routing information.

Abstract: A system comprising a processor, a data storage device that is accessible by the processor, and filesystem software that is executable by the processor to organize files on the data storage device are provided. The filesystem software is executable to maintain a filename cache having variable size filename entries. The filename entries may include a filename header section and a name section storing an entire filename of a corresponding file.

Abstract: Methods for processing more securely are disclosed. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.

Abstract: In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method includes receiving an identifier, receiving output from a command line utility, and storing the command line utility output in a system storage at a location identified by the identifier. In one illustrative embodiment, command line utility output is stored in a system registry database. In another illustrative embodiment, command line utility output is stored in a shared system memory. The method may be stored in any media that is readable and executable by a computer system.

Abstract: A data storage enclosure management system of a plurality of service processors is configured to communicate externally via a pair of FC-AL loops. Lead and subsidiary service processors are defined and lead service processors connect to ones of the FC-AL loops with an FC-AL address, and the lead and subsidiary service processors are connected by a secondary communication link. The lead service processor(s) employ an identifier unassociated with the FC-AL address to differentiate communications of the lead service processor from communications of an associated subsidiary service processor, the lead service processor serving as a proxy for the associated subsidiary service processor with respect to the FC-AL address and communicating with the associated subsidiary service processor via the secondary communication link.

Abstract: Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.

Abstract: A CDA processing section extracts an unused area of an information recording medium via a disc status management section and a drive control section. The CDA processing section divides the extracted unused areas by a division criteria value MAS, which allows continuous reproduction of a video and audio stream, and reserves areas having the size of the division criteria value MAS as CDAs. This enables continuous reproduction of AV data, and multiple data can be recorded simultaneously.

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: A system comprising a processor, a data storage device that is accessible by the processor, and filesystem software that is executable by the processor to organize files on the data storage device are provided. The filesystem software is executable to maintain a filename cache having variable size filename entries. The filename entries may include a filename header section and a name section storing an entire filename of a corresponding file.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses oldie surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: An image forming apparatus comprises an interface which can communicate with the information processing apparatus that serves as the source of updating firmware. The image forming apparatus further comprises a memory which stores a plurality of firmware programs and a controller which performs firmware updates by sequentially storing the updating firmware transferred from the information processing apparatus. When a plurality of firmware programs are transferred from the information processing apparatus, the controller performs a reboot operation to activate the updated firmware upon completing the storage and the rewriting of the updating firmware in the memory.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: A storage controller that can control memory addresses even when a memory module having a different device configuration than an already mounted memory module is added as an expansion module. More specifically, a storage controller for controlling a storage unit that can be constructed using a plurality of memory modules is configured so as to include: a register which stores memory module configuration information for a basic memory module and an expansion memory module independently of each other; and an address conversion unit which, based on the memory module configuration information stored in the register, generates an address that can access the storage unit even when the memory address space of the expansion memory module is different from the memory address space of the basic memory module.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: The present invention relates to an application of the Universal Serial Bus (USB) technology, and more particularly, to a USB apparatus with data storage and security token and control method therein. In an embodiment of the present invention, both mass storage and security token are implemented in a USB apparatus with a single controller. Thus, the host needs to enumerate the apparatus only once, and then may operate differentially in response to different commands. The mass storage is capable of swapping a mass of data, and has a file allocation table compatible with the system. The security token can be used for authenticating a person through digital certificates or biometric characteristics, maintaining the security of the computer and network applications.

Abstract: A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration source storage, and an external volume. After destaging all dirty data accumulated in the disk cache of the migration source storage to the external volume, an expansion device for virtualizing the external volume is mapped to the migration destination logical unit.

Abstract: A local interface driver generates a network communication channel through which resources of a peripheral device connected via a local interface can be seen, from application software for accessing resources of a peripheral device connected via a network interface by use of a predetermined network communication system, as network resources accessible using the same predetermined network communication system. Depending on which of the peripheral devices connected to the individual interfaces is used to communicate, either the local interface driver or a network interface driver is selected. A unified user interface can be used for making user's operations or setup operations to peripheral devices without being limited to interfaces via which a host device user gains access to the peripheral devices.

Abstract: Interleaving improves noise rejection in digital communication and storage systems. According a known scheme, the interleaving/deinterleaving is achieved by storing symbols in a temporary memory table of R rows×C columns in a row by row order, and reading them in a column by column order, or vice versa, so obtaining a rearranged order. Methods and devices for interleaving and deinterleaving are proposed which accomplish the same interleaving/deinterleaving operation with a reduced size of the temporary memory table. The rearrangement of the symbols according to the rearranged order is accomplished by using a table with a reduced memory size, in combination with the order with which the symbols are fetched from or stored in a further memory. The invention further relates to ICs and apparatuses for interleaving and/or deinterleaving.

Abstract: Aspects of the subject matter described herein relate to initializing a database to be used for synchronization. In aspects, a peer in a synchronization topology creates a consistent copy of its database. Metadata associated with this copy is marked to distinguish changes made before the copy was created from changes made after the copy was created and also that the copy needs to be prepared before being used in synchronization. Any client may then download the copy and start immediately reading and modifying its downloaded copy. Before the client synchronizes its copy with other databases already in the synchronization topology, the downloaded copy is prepared for use in the topology using the markers.

Abstract: Clustering related objects in a region-based garbage collector is solved by associating one or more regions with each cluster, and allocating objects from a region belonging to the primary cluster for the object. Relatedness may refer to, e.g., proximity to a cluster center (such as topic) in a persistent knowledge base or a home node in a distributed object system. The cluster for an object may be determined, e.g., from reachability from particular roots or objects during global tracing. For new objects, the initial cluster may be guessed based on history of where objects allocated in that call site have recently been clustered (possibly several stack frames deep).

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: A bank note processing machine includes a plurality of sensors, a transport system, an input/output device, a control device and an interface. The control device has a memory configured to control elements of the bank note processing machine by means of software and/or data stored in the memory. The interface is arranged to couple memory systems of different kinds to the bank note processing machine in order to alter, supplement or replace software and/or data stored in the memory.

Abstract: A mobile phone with an expanded telephone directory, wherein any electronic telephone directory of the mobile phone is supplemented by, in each case, one data base located in the nonvolatile memory of the mobile phone, each data base being assigned to precisely one specific telephone directory. The data base assigned to a telephone directory is preferably an expansion telephone directory, and a number of the expansion telephone directories can be assigned to each telephone directory.

Abstract: When a computer 10 receives a request from the client computer 30 to access snapshot files, the target device to be used is identified. The computer 10 makes a request to the identified target device TD for attachment of the logical device LDEV that stores the snapshot files for which access is requested. When the computer 10 receives notification that the attachment has ended from the storage device system 20, the identified target device is mounted on the directory in which the snapshot files are stored.

Abstract: A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.

Abstract: Methods for processing more securely. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.

Abstract: A data processing apparatus includes a data processing section that issues a plurality of data transfer requests simultaneously; an internal memory provided inside a circuit including the data processing section; an internal memory control section that performs an access control for the internal memory; an external memory that exchanges data with the data processing section via an external bus; an external memory control section that performs an access control for the external memory; and a memory selecting section that assigns to at least one of the internal memory and the external memory a data transfer request from the data processing section.