Addressing Combined With Specific Memory Configuration Or System Patents (Class 711/1)
  • Patent number: 10353725
    Abstract: A computer system implements a hypervisor which, in turn, implements one or more computer system instances and a controller. The controller and a computer system instance share a memory. A request is processed using facilities of both the computer system instance and the controller. As part of request processing, information is passed between the computer system instance and the controller via the shared memory.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: July 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Nicholas Alexander Allen
  • Patent number: 10348583
    Abstract: The disclosed embodiments provide a method and system for processing network data. During operation, the system obtains, at a remote capture agent, configuration information for the remote capture agent from a configuration server over a network. Next, the system uses the configuration information to configure the generation of event data from network data obtained from network packets at the remote capture agent. The system then uses the configuration information to configure transformation of the event data or the network data into transformed event data at the remote capture agent.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 9, 2019
    Assignee: Splunk Inc.
    Inventor: Michael Dickey
  • Patent number: 10338947
    Abstract: Files can be segmented into distinct groups and allocated storage units such as blocks. Files associated with parent and child files can be segmented into separate groups, for instance. Further, a group associated with parent files can be extended to include additional blocks reserved for subsequent update. Additionally, metadata can be merged across groups to provide a unified view of the distinct groups.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Galen C. Hunt
  • Patent number: 10303615
    Abstract: In one example in accordance with the present disclosure, a system may comprise a memory accessor to access a memory and a pointer loader to load a virtual address (VA) pointer corresponding to a first location in the memory and a physical address (PA) pointer corresponding to the VA pointer. The system may comprise a pointer handler to determine a first physical address in the memory mapped to the first location in the memory and a location matcher to determine whether the second physical address mapped to the PA pointer matches the first physical address. The system may also comprise an exception handler to raise an exception when the second physical address does not match the first physical address.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 28, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Dejan S. Milojicic, Moritz J. Hoffmann, Alexander Richardson
  • Patent number: 10289345
    Abstract: A mapping apparatus comprises a mapper that translates from an input key to an output key in one or more storage devices. A pre-mapper for processing update operations comprises a plurality of mapping tablets and an in-memory look-up filter to identify a given mapping table storing a given input key. The mapping tablets comprise at least one dynamic in-memory ingress tablet and a plurality of persisted frozen tablets. For a given update operation, a first entry is added to one dynamic in-memory ingress tablet comprising the input key for the given update operation and a corresponding output key where data for the given update operation is stored; and a second entry is added to the look-up filter comprising the input key of the first entry and an identifier of the dynamic in-memory ingress tablet storing the first entry for the given update operation. The dynamic in-memory ingress tablet is persisted as a persisted frozen tablet.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 14, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Joris Wils
  • Patent number: 10290332
    Abstract: A system may include a controller, a data receiving circuit, and a plurality of banks. The banks may send data to the data receiving circuit via a common data bus. The controller may control the communication of the data to the receiving circuit by sending control signals and clock signals to the banks. Relative lengths of control signal paths and clock signal paths may be directly related to each other and inversely related to relative lengths of data paths.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 14, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yukeun Sim, Anurag Nigam, Yingchang Chen
  • Patent number: 10282808
    Abstract: Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Larry Seiler, Prasoonkumar Surti, Aditya Navale
  • Patent number: 10275469
    Abstract: Embodiments described herein provide techniques for maintaining consistency in a distributed system (e.g., a distributed secondary storage system). According to one embodiment of the present disclosure, a first set of file system objects included in performing the requested file system operation is identified in response to a request to perform a file system operation. An update intent corresponding to the requested file system operation is inserted into an inode associated with each identified file system object. Each file system object corresponding to the inode is modified as specified by the update intent in that inode. After modifying the file system object corresponding to the inode, the update intent is removed from that inode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 30, 2019
    Assignee: Cohesity, Inc.
    Inventors: Mohit Aron, Ganesha Shanmuganathan
  • Patent number: 10248538
    Abstract: There are provided a controller of a semiconductor memory device, which stores data for debug processing, and an operating method of the controller. A controller for controlling a semiconductor memory device includes an event occurrence detection unit configured to detect whether an event occurs, an event information generation unit configured to generate event information in response to the detecting result from the event occurrence detection unit, and a command generation unit configured to generate a command for storing the event information in the semiconductor memory device.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Young Dong Roh
  • Patent number: 10198142
    Abstract: Some embodiments of the invention provide a graphical user interface for receiving a server configuration (e.g., receiving a new configuration or a modification to an existing configuration). The graphical user interface (UI) includes several UI control elements for defining components of the server configuration. It also includes a display area for displaying graphical representations of the defined components of the server configuration. Examples of control elements in some embodiments include control elements for adding, deleting, and modifying servers. In some embodiments, at least one control element is displayed when a cursor control operation is performed on the UI. The cursor control operation (e.g., a right hand click operation) in some embodiments opens a display area that shows the control element. In some embodiments, at least two different components in the server configuration correspond to two different layers (e.g., a web server layer and a data storage layer) in the server configuration.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 5, 2019
    Assignee: GOGRID, LLC
    Inventors: Paul Lappas, John Martin Keagy, Nicholas F. Peterson
  • Patent number: 10198198
    Abstract: A storage device includes a volatile memory, a nonvolatile memory, an auxiliary power source, and a controller configured to start a setting process to store a setting value in the volatile memory in response to a setting command received from a host, and operate in accordance with one or more setting values stored in the volatile memory. When the controller determines that a main power supply will stop, power from the auxiliary power source starts to be primarily used, and the controller saves at least part of said one or more setting values stored in the volatile memory to the nonvolatile memory, before power supply from the auxiliary power source ends.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Satoshi Machida
  • Patent number: 10198200
    Abstract: A method for responding to a command sequence includes receiving the command sequence associated with a targeted access to a memory system, detecting a non-consecutive clock associated with a start of the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock associated with the start of the command sequence.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 5, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Craig DeSimone, Praveen Singh, Alejandro Gonzalez, Yue Yu, YanBo Wang
  • Patent number: 10162324
    Abstract: A method for manipulating a first function of a control program of an electronic control device, using a second function. The control program is processed using a first calculation kernel of a processor, and the second function is processed by a second calculation kernel during the processing of the control program. The first function assigns a first value to a variable and writes the first value to the storage address of the variable at a first time. The second function assigns a second value to the variable, which value is written to the storage address of the variable at a second time, wherein the second value written by the first function is overwritten. At a third time, the control program reads the second value from the storage address of the variable. A control entity coordinates the times at which the storage address of the variable is accessed.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 25, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Bastian Kellers, Marc Dressler, Thorsten Hufnagel
  • Patent number: 10152424
    Abstract: A method, computer program product, and computing system for reducing write operations on a flash-based cache memory system includes writing user data to a flash-based cache memory system. Initial status metadata concerning the user data is written to a RAM-based memory system. The user data is written to a backend storage system. Mapping metadata concerning the user data is written to the flash-based cache memory system.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 11, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Xinlei Xu, Charles Hopkins, John V. Harvey, Xiongcheng Li, Jian Gao
  • Patent number: 10140476
    Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operatio
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: November 27, 2018
    Assignee: ARM Limited
    Inventors: John Michael Horley, Michael John Williams, Simon John Craske, Uma Maheswari Ramalingam
  • Patent number: 10140029
    Abstract: Managing pages in a memory based file system by maintaining a memory into two lists, an Lr list and an Lf list, moving pages from the Lr list to the Lf list based on a repeated access pattern, and moving a page out of the Lr list or the Lf list arbitrarily, thereby enabling the two lists to re-grow according to current workload.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: November 27, 2018
    Assignee: NETAPP, INC.
    Inventors: Amit Golander, Boaz Harrosh, Sagi Manole, Omer Caspi
  • Patent number: 10120752
    Abstract: The present invention provides a data-storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector, and the spare data sector respectively corresponds to the sub-pages. The controller is arranged to access the sub-pages according to the spare data sector.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 6, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Li-Shuo Hsiao, Chang-Kai Cheng
  • Patent number: 10063839
    Abstract: In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for receiving a first command via a first interface that is addressable by a first address and receiving a second command via a second interface that is addressable by a second address.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 28, 2018
    Assignee: Nokia Technologies Oy
    Inventor: Mikko Muukki
  • Patent number: 10042759
    Abstract: A computer system includes an addressing assembly, connected respectively to high bits of a memory address line of a processor and high bits of a word address line of a storage, and used to convert, in a preset continuous or discrete range on the storage, high bits of a memory address formed by the processor into high bits of a corresponding word address of the storage and output the high bits to the storage. Low bits of the memory address line of the processor are connected to low bits of the word address line of the storage. The preset range is smaller than or equal to an addressing range of the memory address line of the processor. The processor changes storage units of the storage covered by the preset range by changing the preset range. Thus it reduces cost, improves operation efficiency, shortens operation time, and has wide applicability.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 7, 2018
    Assignee: SHANGHAI UNIVERSITY
    Inventors: Yi Jin, Shan Ouyang, Yunfu Shen, Junjie Peng, Xuemin Liu
  • Patent number: 10026461
    Abstract: A semiconductor device may include a strobe signal buffer, a strobe signal division circuit, and a drive control circuit. The strobe signal buffer may buffer a first data strobe signal and a second data strobe signal to generate a buffer output signal and an inverted buffer output signal. The strobe signal division circuit may divide the buffer output signal and the inverted buffer output signal to generate internal strobe signals which are used in capturing data when receiving data. The drive control circuit may drive the buffer output signal to a predetermined logic level during an initial section of time from a point of time when a write operation is performed.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: July 17, 2018
    Assignee: SK hynix Inc.
    Inventor: Geun Ho Choi
  • Patent number: 10019290
    Abstract: A technique for multi-layer quality of service (QoS) management in a distributed computing environment includes receiving a workload to run in a distributed computing environment. A workload quality of service (QoS) class for the workload is identified, and the workload QoS class is translated to a storage level QoS class. The workload is scheduled to run on a compute node of the environment, and the storage level QoS class is communicated to a workload execution manager of the compute node. The storage level QoS class is communicated to one or more storage managers of the environment where the storage managers manage storage resources in the environment. The storage managers extend the storage level QoS class to the storage resources to support the workload QoS class.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yonggang Hu, Zhenhua Hu, Reshu Jain, Prasenjit Sarkar, Rui Zhang
  • Patent number: 10019289
    Abstract: A system for multi-layer quality of service (QoS) management in a distributed computing environment includes a management node hosting a workload scheduler operable to receive a workload and identify a workload QoS class for the workload. The system also includes a plurality of distributed compute nodes. A workload scheduler is operable to schedule running of the workload on the compute nodes. The workload scheduler is operable to translate the workload QoS class to a storage level QoS class and communicate the storage level QoS class to a workload execution manager of the compute nodes. The workload scheduler communicates the storage level QoS class to one or more storage managers where the storage managers manage storage resources, and the storage managers are operable to extend the storage level QoS class to the storage resources to support the workload QoS class.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yonggang Hu, Zhenhua Hu, Reshu Jain, Prasenjit Sarkar, Rui Zhang
  • Patent number: 10013195
    Abstract: A memory module may include a plurality of memory groups configured to include a plurality of memory packages, respectively, and input/output data through input/output pins. The memory module may include a control circuit configured to activate one or more of the plurality of memory groups on a basis of an address signal. The memory module may include a multiplexer circuit configured to couple the memory group activated on the basis of the address signal to input/output buses of the memory module.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: July 3, 2018
    Assignee: SK hynix Inc.
    Inventors: Do Yun Lee, Min Chang Kim, Chang Hyun Kim, Jae Jin Lee, Hun Sam Jung
  • Patent number: 9935667
    Abstract: Method and system for obtaining on-line service are provided. The method may include: a vehicle mounted system sending a first piece of information about its capability and a request for an on-line service to a mobile communication device connected to the vehicle mounted system; and the vehicle mounted system receiving contents of the on-line service from the mobile communication device, where the contents of the on-line service are obtained by processing to match the capability of the vehicle mounted system. Computation load of the vehicle mounted system may be reduced and more utilization may be realized.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: April 3, 2018
    Assignee: HARMAN INTERNATIONAL INDUSTIRES, INCORPORATED
    Inventors: Jianjun Ma, Xiaopei Huang, Jian Kang
  • Patent number: 9921777
    Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, James J. Shawver
  • Patent number: 9888012
    Abstract: A control component of a computing environment initiates sending of request(s) over a network of the computing environment by an activated virtual adapter. The activated virtual adapter is hosted on a physical adapter of a host system coupled to the network, and is for use by a guest, hosted by the host system, in performing data input and output. The request(s) retrieve access control information from the network indicative of access control(s) enforced in controlling access by the activated virtual adapter to network component(s). The initiating provides indication(s) to the physical adapter, absent involvement of the guest, that the request(s) be sent by the virtual adapter. Based on the initiating, the control component obtains the access control information from the physical adapter, and determines, based on that information, the access control(s) being enforced by the network in controlling access by the activated virtual adapter to the network component(s).
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ralph Friedrich, Raymond M. Higgs, George P. Kuch, Elizabeth A. Moore, Johnathon R. Pandich, Richard M. Sczepczenski
  • Patent number: 9865173
    Abstract: These teachings are applicable for use with an individual who faces problems with respect to forming new long term memories. Generally speaking, pursuant to these various embodiments, one automatically captures (101) a record of experiential content to which the individual is exposed during a given episode and then automatically associates (102) that record of experiential content with metadata that characterizes the given episode. This record of experiential content is then automatically used (103) to re-expose the individual to at least portions of the given episode to thereby encourage development of a long term recollection of at least a portion of the given episode. These teachings will accommodate a variety of experiential content modalities including both audio content and visual content.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: January 9, 2018
    Assignee: Persinvitro LLC
    Inventor: Leslie G. Seymour
  • Patent number: 9852014
    Abstract: A deferral instruction associated with a transaction is executed in a transaction execution computing environment with transactional memory. Based on executing the deferral instruction, a processor sets a defer-state indicating that pending disruptive events such as interrupts or conflicting memory accesses are to be deferred. A pending disruptive event is deferred based on the set defer-state, and the transaction is completed based on the disruptive event being deferred. The progress of the transaction may be monitored during a deferral period. The length of such deferral period may be specified by the deferral instruction. Whether the deferral period has expired may be determined based on the monitored progress of the transaction. If the deferral period has expired, the transaction may be aborted and the disruptive event may be processed.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9851960
    Abstract: A solution is proposed for managing a multi-tenant software application adapted to serve a plurality of tenants. A deletion request is received for deleting one of the tenants from the plurality of tenants. Responsive to receiving the deletion request, an instance of the software application associated with the tenant to be deleted is disabled. The disabled instance of the software application associated with the tenant to be deleted is deleted after a protection period from the deletion request. An addition request for adding a new tenant to the software application is received. An instance of the software application for the new tenant is allocated to a selected instance of the software application.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Domenico Agostinacchio, Franco Mossotto, Riccardo Pizzutilo, Luigi Presti
  • Patent number: 9854016
    Abstract: The multimedia client-server system provides a multimedia client program with a set of features and a server system that creates feature access information that determines which features are to be made available to a particular user. The server system may send the feature access information to the user such that the information is accessible to the multimedia client program. The multimedia client program may dynamically control the user's access to the program's feature set by using the feature access information to validate and verify the user. In addition, the feature access information may be accessible to the server system, such that the server system may periodically update the feature access information, such as, for example, when the user accesses the server system to download multimedia content.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Jeffrey M. Chasen, Joshua E. Elman
  • Patent number: 9841927
    Abstract: Systems and methods for implementing remote direct memory access (RDMA) with copy-on-write support. An example method may comprise: registering, with an RDMA adapter, by a first computer system, a mapping of a first virtual address to a first physical address, for transmitting a memory page identified by the first virtual address to a second computer system; registering, with the RDMA adapter, a mapping of a second virtual address to the first physical address; detecting an attempt to modify the memory page; copying the memory page to a second physical address; and registering, with the RDMA adapter, a mapping of a first virtual address to the second physical address.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: December 12, 2017
    Assignee: Red Hat Israel, Ltd
    Inventors: Michael Tsirkin, Gleb Natapov
  • Patent number: 9838451
    Abstract: The multimedia client-server system provides a multimedia client program with a set of features and a server system that creates feature access information that determines which features are to be made available to a particular user. The server system may send the feature access information to the user such that the information is accessible to the multimedia client program. The multimedia client program may dynamically control the user's access to the program's feature set by using the feature access information to validate and verify the user. In addition, the feature access information may be accessible to the server system, such that the server system may periodically update the feature access information, such as, for example, when the user accesses the server system to download multimedia content.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Jeffrey M. Chasen, Joshua E. Elman
  • Patent number: 9823881
    Abstract: A management server allocates storage for a virtual disk of a virtual machine configured to execute on a first host computer, where the first host computer is associated with a plurality of data storage devices including first and second data storage devices, and where a first portion of storage is allocated to the virtual disk from the first storage device. The management server receives a request to allocate a second portion of storage to the virtual disk of the virtual machine and, responsive to determining that the first data storage device has insufficient free storage space from which to allocate the second portion of storage, selects the second data storage device having sufficient free storage space from which to allocate the second portion of storage. The management server allocates the second portion of storage for the virtual disk of the virtual machine from the second data storage device, wherein the virtual machine accesses the first and second portions of storage as a single virtual disk.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: November 21, 2017
    Assignee: VMware, Inc.
    Inventors: Gururaja Hegdal, Kiran Kasala, Marichetty M. S.
  • Patent number: 9792049
    Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 17, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Qamrul Hasan, Shinsuke Okada, Yuichi Ise, Kai Dieffenbach, Kiyomatsu Shouji
  • Patent number: 9785352
    Abstract: An application located in one or more first memory regions is executed. The application has a separate modified portion, which is located in one or more second memory regions. A request is obtained to access one of a first memory region or a second memory region, the request including an address of a first type. Based on obtaining the request, the address is translated to another address. The other address is of a second type and indicates the first memory region or the second memory region. The translating is based on an attribute associated with the address, in which the attribute is used to select information from a plurality of information concurrently available for selection. The plurality of information provide multiple addresses of the second type, one of which is the other address. The other address is used to access the first memory region or the second memory region.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9785418
    Abstract: A system and computer program product for developing software in which the software comprises a plurality of programs. A change to a program is received. A data structure checking procedure may then be invoked. The changed program is parsed for a reference to a data structure. Other instances of the data structure are located in other programs within the software. The referenced data structure is compared to the located other instances of the data structure. A predefined action (such as notifying a programmer or correcting the inconsistencies) is performed in response to any detected differences between the referenced data structure and the located other instances of the data structure. These steps are repeated for all data structures within the changed program.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen J. Burghard, Mark Todd, Philip R. Lee, Andrew Wright
  • Patent number: 9787598
    Abstract: A resource manager is tasked with monitoring and managing information technology (IT) resources in a virtual environment. The IT resources are assigned tags that correspond to conditions that alert the resource manager when to begin actively managing the IT resource. The resource manager may monitor events occurring in the virtual environment that have conditions that match the predefined tags. When such an event occurs, the resource manager identifies an appropriate resource by searching a data store that includes the tags and the corresponding resource. The resource manager then begins to actively manage the resource and assigns the resource to a workload. By tagging the resources, the resource manager does not need to actively manage all of the IT resource in the virtual environment. Furthermore, the tags permit the resource manager to automatically select which resources to actively manage without receiving instructions from a system administrator.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Randal L. Bertram, Gregory R. Hintermeister, David M. S. Niedergeses
  • Patent number: 9781051
    Abstract: A resource manager is tasked with monitoring and managing information technology (IT) resources in a virtual environment. The IT resources are assigned tags that correspond to conditions that alert the resource manager when to begin actively managing the IT resource. The resource manager may monitor events occurring in the virtual environment that have conditions that match the predefined tags. When such an event occurs, the resource manager identifies an appropriate resource by searching a data store that includes the tags and the corresponding resource. The resource manager then begins to actively manage the resource and assigns the resource to a workload. By tagging the resources, the resource manager does not need to actively manage all of the IT resource in the virtual environment. Furthermore, the tags permit the resource manager to automatically select which resources to actively manage without receiving instructions from a system administrator.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Randal L. Bertram, Gregory R. Hintermeister, David M. S. Niedergeses
  • Patent number: 9779017
    Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of dies having a plurality of columns, wherein each of the columns is constituted by a plurality of sectors. The controller performs a read operation or a write operation from a first column to an Nth column in response to a read command or a write command, and skips at least two columns within the range of the first column to the Nth column according to a first bad column data set, wherein the first bad column data set has a starting address and the number of columns.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 3, 2017
    Assignee: Silicon Motion, Inc.
    Inventors: Chi-Lung Wang, Chia-Ta Huang
  • Patent number: 9772797
    Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The method includes allocating a first zone and a second zone in the buffer memory for temporarily storing a plurality of logical address-physical address mapping tables and performing a restore operation on the first zone. The method also includes receiving a write command, wherein a logical address-physical address table to which a logical address indicated by the write command belongs has been temporarily stored in the first zone. The method further includes copying the logical address-physical address table into the second zone, and updating the logical address-physical address table in the second zone.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 26, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 9766865
    Abstract: A method for developing software in which the software comprises a plurality of programs. A change to a program is received. A data structure checking procedure may then be invoked. The changed program is parsed for a reference to a data structure. Other instances of the data structure are located in other programs within the software. The referenced data structure is compared to the located other instances of the data structure. A predefined action (such as notifying a programmer or correcting the inconsistencies) is performed in response to any detected differences between the referenced data structure and the located other instances of the data structure. These steps are repeated for all data structures within the changed program.
    Type: Grant
    Filed: February 26, 2012
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen J. Burghard, Mark Todd, Philip R. Lee, Andrew Wright
  • Patent number: 9760305
    Abstract: A method and system for migrating data in a storage system by a computer system. The storage system includes a first storage and a second storage with a sequential access medium. The computer system selects a plurality of data to migrate from the first storage to the second storage. The computer system then obtains metadata information of each data and orders the plurality of the data based on the metadata information. The order of the data follows an expectation of update of the data. The computer system transfers the plurality of the data to the second storage based on the order of the data. The computer system determines whether data written in a rear region of the sequential access medium is inactive. The computer system overwrites the data determined to be inactive on the sequential access medium by transferred data.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
  • Patent number: 9720440
    Abstract: There is provided a communication apparatus. A communication unit transmits data to a communication module, which communicates with an external device, according to a clock signal, and receives data from the communication module in accordance with a timing corresponding to a timing signal generated by delaying the clock signal. An adjustment unit adjusts an amount of the delay. A control unit controls the communication unit to repeatedly perform first processing for transmitting a first command to the communication module, second processing for receiving a first response that is sent from the communication module, and third processing for transmitting a packet to the communication module according to the first response. In a predetermined mode, the control unit controls the communication unit to perform processing for transmitting data of the packet regardless of contents of the first response.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: August 1, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuhiro Shiraishi
  • Patent number: 9678877
    Abstract: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: June 13, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Kevin M. Conley, Reuven Elhamias
  • Patent number: 9679621
    Abstract: A semiconductor system may include a first semiconductor device configured to output commands, addresses and data. The semiconductor system may include a second semiconductor device configured to convert a logic level combination of the data when only any one of bits of the data is a different logic level, and store the data in response to the commands and the addresses, in a write operation.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 13, 2017
    Assignee: SK hynix Inc.
    Inventors: Min Soo Park, Jin Se Kim, Moon Yub Na, Min Jun Choi, Hyun Wook Han
  • Patent number: 9659003
    Abstract: For hybrid language processing, a method is disclosed that includes identifying, by use of a processor, one or more user specific terms in a user generated portion of text, modifying the portion of text by replacing one or more of the user specific terms with general tokens, and converting the modified portion of text to one or more commands to be executed by the processor.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 23, 2017
    Assignee: Lenovo (Singapore) PTE. LTD.
    Inventor: Antoine Roland Raux
  • Patent number: 9652306
    Abstract: A service manages a plurality of virtual machine instances for low latency execution of user codes. The service can provide the capability to execute user code in response to events triggered on various event sources and initiate execution of other control functions to improve the code execution environment in response to detecting errors or unexpected execution results. The service may maintain or communicate with a separate storage area for storing code execution requests that were not successfully processed by the service. Requests stored in such a storage area may subsequently be re-processed by the service.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 16, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Allen Wagner, Ajay Nair, Marc John Brooker, Scott Daniel Wisniewski
  • Patent number: 9654447
    Abstract: Making a determination of originality of content is disclosed. At least one originality factor related to the content is analyzed, wherein the originality factor is independent of a time when the content is detected. Based on the analysis of the at least one originality factor, automatically the determination is automatically made. The determination is outputted.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: May 16, 2017
    Assignee: Digimarc Corporation
    Inventors: James L. Brock, James E. Pitkow
  • Patent number: 9640232
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. The second semiconductor device aligns the data in synchronization with the data strobe signal to generate first and second alignment data and latches the first and second alignment data to generate first and second latch data in response to a latch signal which is generated by dividing the data strobe signal.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 2, 2017
    Assignee: SK HYNIX INC.
    Inventors: Min Chang Kim, Chang Hyun Kim, Do Yun Lee, Jae Jin Lee, Hun Sam Jung
  • Patent number: 9626108
    Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 18, 2017
    Assignee: Kove IP, LLC
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, John Overton, Andrew S. Poling, Jesse I. Taylor