Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.

Abstract: Bursts of data are managed. Data is stored in a machine readable memory device a first time at a first memory address. The machine readable memory device has one or more burst boundaries. The first memory address has a first alignment with respect to the burst boundaries. The data is stored in the machine readable memory device a second time at a second memory address. The second memory address has a second alignment with respect to the burst boundaries.

Abstract: An information storage apparatus capable of setting the number and sizes of partitioned areas resulting from partitioning a memory area based on a user's intention is provided. For this purpose, an information storage apparatus having a plurality of partitioned areas of different security levels in a memory area is provided with an area control section that controls addresses of partitioned areas in the memory area, an area update condition control section that controls update conditions when the number or sizes of partitioned areas are updated, an area update decision section that decides whether a partition request requesting updating of the number or sizes of partitioned areas satisfies the update conditions and an area update section that executes, when the partition request satisfies the update conditions, updating of the partitioned areas in the memory area according to the partition request.

Abstract: A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Abstract: A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a program segment and a hold segment. At startup, instructions are loaded into the hold segment, and the programmable device begins executing those instructions. While the hold segment instructions are executed, the program segment is loaded with instructions. Once the program segment is filled, control is shifted to it and instructions from this segment are executed by the programmable device. When the program segment has been executed, control is shifted back to the hold segment, and instructions are taken from it while the program segment is reloaded with a fresh set of instructions from the host application. Once the program segment is reloaded, control is redirected and execution of instructions from the program segment is continued.

Abstract: Described is a system and method whereby processes may have multiple memory maps associated therewith to provide curtained memory and overcome other memory-related problems. Multiple maps are used to restrict memory access of existing code such as drivers, without changing that code, and without changing existing microprocessors. A thread of a process is associated with one memory map at a time, which by mapping to different memory locations, provides memory isolation without requiring a process switch. Memory isolation may be combined with controlled, closed memory map switching performed only by trusted code, to ensure that some protected memory is inaccessible to all but the trusted code (curtained memory). For example, the threads of the process may ordinarily run at one privilege level with a restricted map, with map switching is only allowed at a higher privilege level.

Abstract: A method and apparatus for address mapping are provided, wherein the method sets a first address region that is accessible by a processor when a system is booted and a second address region that is expanded by a virtual address, respectively. The first and second address regions are then mapped so that a first physical address region corresponding to a predetermined part of the first address region and a second physical address region corresponding to a predetermined part of the second address region access the same address region. Accordingly, embodiments of the present invention do not require consideration of reallocation of physical address during programming, and the decoding process for address mapping is simplified.

Abstract: A data control apparatus has a user interface section, an operation control section which operates based on an instruction from the user interface section, a USB device interface section which is connected to an external equipment, and controls USB communications with the external equipment, a file system control section which transfers data to and from the operation control section, and controls a file, an internal storage which stores data from the file system control section and data from the external equipment, and a USB mass storage class control section which controls a USB mass storage class, wherein the USB device interface section controls so that the external equipment identifies the data control apparatus as an external storage, and transfers to and from the external equipment.

Abstract: Some embodiments include a storage device with a storage medium having a memory capacity. The storage device also includes virtual storage device firmware that is configured to directly respond to commands from a guest operating system in a virtual machine for accesses to a subset of the memory capacity of the storage medium when a virtual storage device is enabled.

Abstract: A common external storage device is connected to the first and second storage systems.

Abstract: A microprocessor system contains a read-only memory (ROM) for storing programs or firmware. Retrieval and execution of program code is controlled by a microprocessor address bus. Erroneous data in the ROM can be corrected by address comparison and translation. Trap, region, and patch tables are provided to store addresses, regions, and translated addresses. An address issued by the microprocessor is stored in the trap and region tables can be translated for selecting another programmable device, such as a SRAM or DRAM, other than the original ROM. Thus, erroneous code in the ROM can be corrected, inserted, or replaced.

Abstract: A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration source storage, and an external volume. After destaging all dirty data accumulated in the disk cache of the migration source storage to the external volume, an expansion device for virtualizing the external volume is mapped to the migration destination logical unit.

Abstract: A method for initiating a system is provided. In the present invention, a specific data, which is not used for executing an initiating program of an interface device, is moved from a conventional memory to an extended memory temporarily, such that the available space of the conventional memory is increased. As a result, the computer system can have enough conventional memory space for loading and executing the initiating program of the interface device during a Power-On Self Test (POST) so as to achieve the purpose of initiating the system.

Abstract: A logic device. The logic device includes a control module, a memory management unit, a memory module, and at least one first register. The memory management unit controls flow of software code between the control module and the memory module; the control module programs at least one of the first registers during start-up procedures of the logic device to specify at least one data memory section in the memory module. The memory management unit communicates with the first registers to identify the at least one data memory section, and the memory management unit excludes executable code from storage in the at least one data memory section. After completion of the start-up procedures, the first registers are write protected, thereby preventing subsequent programming of the first registers, and the memory management unit cannot be disabled without shutting down the logic device.

Abstract: An integrated circuit having an embedded multiple time programmable memory includes a processing core for executing stored instructions with a data memory and a non volatile memory. The non-volatile memory block provides for storage of program instructions and includes a plurality of blocks of non-volatile memory, each of which can be written to once and read from many times and each having a size that is equal to or less than a program memory address space addressable by the processing core for output of data there from.

Abstract: Embodiments of the invention achieve data write in an appending manner by conversion from a logical block address to a physical block address in a HDD that has only one storage device and does not have a large-scale cache memory. In one embodiment, a check is made as to whether or not the size of an address translation table in a cache memory exceeds a threshold value. If the size exceeds the threshold value, entries whose number is specified are selected by the LRU method. The selected entries are added to a WRITE buffer, and the address translation table is saved on the HDD by executing WRITE. Seek time of a head at the time of WRITE is reduced, thereby improving WRITE performance. There is produced an effect of building such a snapshot that while a usual access to a HDD volume is allowed, it is possible to make an access to a volume of the snapshot which is a past state of the HDD. Disabling write after writing to the HDD is disabled.

Abstract: A memory card comprising a first modular component that comprises a first interface and first conductors and a data mover that comprises second conductors coupled to the first conductors. The first modular component is replaceable with a second modular component that comprises a second interface that differs from the first interface and third conductors that are configured to couple to the second conductors.

Abstract: A memory management apparatus suitable for reducing amount of memory usage and simplifying programs is provided. When an area allocation request has been inputted, an unused area having a size that is determined by area size information included in the area allocation request is searched for as a candidate area on the basis of a memory management table 400. And overlap flag corresponding to an adjoining area that is contiguous with the candidate area in its lower address orientation is read from the memory management table 400, and, based on the overlap flag, it is determined whether or not the adjoining area is an area that allows overlapped allocation. If it is determined the area is an area allowing overlapped allocation, a used area that overlaps with the adjoining area is allocated.

Abstract: Accessing data comprises executing a set of computer instructions in a first environment, wherein the first environment has limited addressing capability to address memory up to a size limit, specifying a set of data in a memory space of a second environment, wherein the memory space has a size that exceeds the size limit, and accessing the set of data from the first environment using the limited addressing capability.

Abstract: Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Abstract: A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width, thereby avoiding the need for extra write cycles when a processing unit tests a memory having a greater data width. The test pattern data may be expanded by, for example, copying a specific bit to multiple bit positions, inverting a specific bit and copying the inverted bit to multiple bit positions, or performing arithmetic operations that generate a test pattern similar to the test pattern received from the processing unit.

Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can provide a relatively high performance storage access environment for the mobile users moving around a wide area. For example, in one applicable environment, there are several data centers in the wide area, and each data center has a local storage system that is connected to the other storage systems through a network. Copies of a user's volume can be made in some of the storage systems. A remote copy function is utilized for making real time copies of the user's volume.

Abstract: Audio and visual information processing components are co-located on a PCI Express graphics card by communicating audio and visual information received through the PCI Express interface of the graphics card to a PCI Express switch which switches audio information to audio processing components and video information to video processing components for processing of the information to an audiovisual appliance output. The audio processing components may include an AC97 interface and CODEC or an audio controller that processes PCI Express information. The audiovisual output signal may include a variety of combined or separate audiovisual appliance compatible outputs such as coaxial cable output, EVC output, HDMI output, HDTV output or 1394 output.

Abstract: A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first rank address, and driving the second rank address to a second one of the memory chips. Alternatively, the first rank address may be driven to the second memory chip, and then, a second rank address is generated in that second memory chip. Further, the second memory chip is set to have the second rank address in response to the driving the second/first rank address. A power-up sequence after voltage supply, or command signals sent via a serial management bus or the command address bus can be used to initiate the setting of ranks. The rank addresses are re-driven to adjacent memory chips by DQ-lines along a byte lane.

Abstract: In some embodiments, the invention involves a system and method relating to switching to protected mode to access extended memory while executing instruction code that is designed for real mode memory access. In at least one embodiment, the present invention is intended to enable complex option-ROM code to be executed during pre-boot without corrupting system memory used by the BIOS or other option-ROMs. Other embodiments are described and claimed.

Abstract: A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: An image forming device includes an operating system to execute any of a plurality of programs. The image forming device comprises a rewritable memory which has a virtual memory area managed by the operating system and an image memory area used to store image data. A memory assignment unit assigns one of the virtual memory area and the image memory area of the rewritable memory for execution of a program of the plurality of programs upon starting up of the image forming device.

Abstract: A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, each for connection to a respective data line of the data bus; an identity acquisition unit capable of functioning in a first mode of operation of the device to receive data transmitted over the data bus and in response to the order in which the bits of one or more data words of a predetermined form are received on the data bus connectors during the first mode of operation determine an identity for the device and store the identity in an identity store of the device; and a data handling unit capable of functioning in a second mode of operation of the device to handle communications transmitted over the bus and that specify the identity stored in the data store as a destination.

Abstract: The invention relates to a method for the automatic retrieval of engineering data from installations. The engineering and runtime objects are described by a uniform object model. This allows the correspondence between engineering objects and runtime objects to be determined at object level and no information is lost as a result of the mapping. In addition, a direct communication between engineering and runtime objects can take place, which can be utilized when the method is carried out.

Abstract: An address decoder 10 decodes an address signal 20 to generate access signals 22, 24. An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An address generation circuit 14 generates an address signal 28 to access the RAM in ascending order from a head address based upon the signal 20. An address inversion circuit 16 inverts and outputs each bit of the signal 28 when the signal 24 is “1” or outputs the address signal without inversion when the signal 24 is “0.” When the chip enable signal is “1,” the RAM performs reading/writing data according to an address signal 30 from the inversion circuit.

Abstract: To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the ranks and address signal lines via which to flow address signals specifying addresses on the rank, and a control unit transmitting the signal for selecting the rank via part of the address signal line and via the selection signal line.

Abstract: In one embodiment, the present invention includes a method for reassigning a first address of a block-alterable memory to a second address of the block-alterable memory, where the second address corresponds to an updated available block. In such manner block-alterable memories may be dynamically mapped.

Abstract: A method for managing an external memory of a microprocessor so that the external memory only contains one copy of a common area. By providing an address translator, mapping the page and the address of the common area of the page pointed by a microprocessor to the physical address of the common area of the external memory, using the address translator to translate a page and an address pointed by a microprocessor to a physical address of the external memory, and using the microprocessor to access data stored at the physical address of the external memory; the memory can be more efficiently used.

Abstract: Techniques for extending memory addressing with more accessing range are disclosed. According to one aspect of the techniques, an apparatus for extending addressing space comprises a plurality of extended memories, each being allocated an unique identifier, a direct addressing memory reserving a data cell as a public identifier cell for receiving the identifier of each of the extended memories to be accessed, a decision unit determining that which one of the extended memories is to be accessed by comparing an identifier received by the public identifier cell with the identifier of each of the extended memories, and a mapping unit mapping one of the extended memories determined by the decision unit to be accessed onto the direct addressing memory so that the one of the extended memories can be indirectly accessed by directly accessing the direct addressing memory.

Abstract: A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is congestion of resources within the system and transfers data packets to external memory to ease the congestion. Data packets are eventually transferred from the internal or external memory to one or more output ports.

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Abstract: When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus controller BSC makes address translation according to information on the relation between addresses of both memory spaces. The invention assures wider latitude in CPU type selection and makes it easy to reuse an existing program or develop a new program.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: A method is provided for sharing and/or transporting data within a single node of a multi-node data processing. The method avoids the necessity of making more than one copy of the data to be shared or transported. The method is tunable based on the size of the data segment involved. A shared memory area between tasks running in different address spaces on the node is used to coordinate the process and for task to task communication. The increase in efficiency provided by the intranodal process described herein also provides advantages to the internodal communication process since more CPU cycles are available for that aspect of system operation.

Abstract: The present invention relates to computer systems and methods for providing a memory buffer for use with native and platform-independent software code. In a particular embodiment, the method includes providing a first software program compiled to platform-independent code for execution in a first process of the computer system, providing a second software program compiled to native code for execution in a second process of the computer system, and sending a message from the first process to the second process to request a memory buffer. In another particular embodiment, the computer system includes a processor and a memory. The computer system includes a first process to execute a first software program coded in a safe language, a second process to execute a second software program coded in an unsafe language, and an inter-process communication mechanism that allows data message communication between the first process and the second process.

Abstract: A method for controlling a storage system including a host computer, and a first and a second storage control apparatuses each receiving a data input/output request from the host computer and executing a data input/output process for a storage device in response to the request, comprises connecting a first communication path between the host computer and the first apparatus; connecting a second communication path between the first apparatus and the second apparatus; receiving by the first apparatus a first data input/output request from the host computer through the first path; when the first apparatus has judged that the first request is not for the first apparatus, transmitting by the first apparatus a second data input/output request corresponding to the first request, to the second apparatus through the second path; and by the second apparatus, receiving the second request and executing a data input/output process corresponding to the second request received.

Abstract: The disclosed embodiments provide for a system and method for storing data in a flash memory device that has a code bank and a data bank. The method includes writing data to the data bank under control of a flash driver in the code bank when sufficient space is expected to exist in the data bank. Otherwise, the method includes writing data to the code bank under control of a flash driver in a storage device that is external to the flash memory device.

Abstract: A recording medium holder enables a user to easily find a desired recording medium from recording mediums that the user manages. The recording medium holder includes a recording medium holding unit for holding a plurality of recording mediums, a liquid crystal displaying unit for displaying each of the plurality of recording mediums held in the recording medium holding unit by an icon, and an information displaying unit for displaying information of a recording medium that corresponds to an icon clicked in the liquid crystal displaying unit, the information including ID information, title information, index information, and other information. The information is read out from the recording medium at a first click, and from a storing unit at a second click and after.

Abstract: Each of a plurality of storage devices (N?1 to N-n) has a plurality of memory blocks for storing data. A data writing apparatus obtains error information which represents good blocks which can store data correctly, from the plurality of storage devices (N?1 to N-n). The data writing apparatus determines a memory block in which data is to be written, in each of the plurality of storage devices (N?1 to N-n), based on the obtained error information. The data writing apparatus controls the plurality of storage devices (N?1 to N-n), and writes predetermined data in the determined memory blocks.

Abstract: Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

Abstract: An allocation instructions and an extension instructions allow a program to continue to execute even when the program requires more stack space than has been allocated to the program. The methods and systems thereby allow programs to run to completion in more situations than programs running in conventional data processing systems. As a result, the programs avoid wasting computing resources by terminating prematurely, without producing results.