Addressing Cache Memories Patents (Class 711/3)
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Publication number: 20150106545Abstract: A computer processing system with a hierarchical memory system having at least one cache and physical memory, and a processor having execution logic that generates memory requests that are supplied to the hierarchical memory system. The at least one cache stores a plurality of cache lines including at least one backless cache line.Type: ApplicationFiled: October 15, 2014Publication date: April 16, 2015Applicant: Mill Computing, Inc.Inventors: Roger Rawson Godard, Arthur David Kahlich
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Publication number: 20150095545Abstract: A method of controlling a cache memory includes receiving location information of one piece of data included in a data block and size information of the data block; mapping the data block onto cache memory by using the location information and the size information; and selecting at least one unit cache out of unit caches included in the cache memory based on the mapping result.Type: ApplicationFiled: September 25, 2014Publication date: April 2, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-chang LEE, Do-hyung KIM, Si-hwa LEE
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Publication number: 20150067230Abstract: Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Paul Chan
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Publication number: 20150052286Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.Type: ApplicationFiled: August 15, 2013Publication date: February 19, 2015Applicant: APPLIED MICRO CIRCUITS CORPORATIONInventor: Kjeld Svendsen
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Patent number: 8949572Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.Type: GrantFiled: October 16, 2009Date of Patent: February 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
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Patent number: 8924648Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.Type: GrantFiled: September 20, 2013Date of Patent: December 30, 2014Inventors: H. Peter Anvin, Guillermo J. Rozas, Alexander Klaiber, John P. Banning
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Patent number: 8924359Abstract: Various systems and methods for cooperative tiering between an application and a storage device. One method can include receiving information from the application where the information identifies a storage object and identifies a location in a storage device. The location identifies one or more tiers of a plurality of tiers included in the storage device, and the storage object is assigned to the one or more tiers. The method also involves detecting whether the storage object is stored in the one or more tiers. If not, the storage device copies the storage object to the identified location. The information can also include an instruction by the application to move the storage object from a first tier to a second tier.Type: GrantFiled: April 7, 2011Date of Patent: December 30, 2014Assignee: Symantec CorporationInventors: Niranjan Pendharkar, Ashish Karnik
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Patent number: 8898424Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.Type: GrantFiled: April 9, 2013Date of Patent: November 25, 2014Assignee: Micron Technology, Inc.Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
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Patent number: 8862828Abstract: Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.Type: GrantFiled: August 13, 2012Date of Patent: October 14, 2014Assignee: Intel CorporationInventors: Ravindra P. Saraf, Rahul Pal, Ashok Jagannathan
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Patent number: 8856474Abstract: An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.Type: GrantFiled: September 2, 2011Date of Patent: October 7, 2014Assignee: Fujitsu LimitedInventors: Masahiro Ise, Michiyo Garbe, Jin Abe
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Patent number: 8856454Abstract: Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or speculates about what the client may request in the future. Rather than await the client request (that may or may not ultimately be made), the service provides the unrequested anticipatory data to the client in the same data stream as the response data that actual responds to the specific client requests. The client may then use the anticipatory data to fully or partially respond to future requests from the client, if the client does make the request anticipated by the service. Thus, in some cases, latency may be reduced when responding to requests in which anticipatory data has already been provided. The service may give priority to the actual requested data, and gives secondary priority to the anticipatory data.Type: GrantFiled: June 24, 2013Date of Patent: October 7, 2014Assignee: Microsoft CorporationInventors: Nicholas Alexander Allen, Kenneth D. Wolf
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Patent number: 8850118Abstract: A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.Type: GrantFiled: September 14, 2011Date of Patent: September 30, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kazuhiko Okada
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Patent number: 8843690Abstract: An apparatus having a memory and circuit is disclosed. The memory may (i) assert a first signal in response to detecting a conflict between at least two addresses requesting access to a block at a first time, (ii) generate a second signal in response to a cache miss caused by an address requesting access to the block at a second time and (iii) store a line fetched in response to the cache miss in another block by adjusting the first address by an offset. The second time is generally after the first time. The circuit may (i) generate the offset in response to the assertion of the first signal and (ii) present the offset in a third signal to the memory in response to the assertion of the second signal corresponding to reception of the first address at the second time. The offset is generally associated with the first address.Type: GrantFiled: July 11, 2011Date of Patent: September 23, 2014Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Dmitry Podvalny, Alex Shinkar, Assaf Rachlevski
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Publication number: 20140281115Abstract: A technique for concurrently accessing a data set includes initializing a shared cache with a column data store configured to store an expected data set in columns and creating a memory map for accessing the physical memory location in the shared cache. Other operations include mapping the applications' data access requests to the shared cache with the memory map. One advantage of the disclosed technique is that only one instance of the expected data set is stored in memory, so each application is not required to create additional instances of the expected data set in the applications memory address space. Therefore, larger expected data sets may be entirely stored in memory without limiting the number of applications running concurrently.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Punya BISWAL, Beyang LIU, Eugene MARINELLI, Nima GHAMSARI
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Publication number: 20140281116Abstract: A microprocessor implemented method for processing a load instruction is disclosed. The method comprises computing a virtual address corresponding to the load instruction. Next, it comprises performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel using early calculated lower address bits of the virtual address. Subsequently, it comprises retrieving a set of entries from the TLB corresponding to a first group of lower address bits transmitted to the TLB, wherein the set of entries comprise a plurality of virtual addresses and corresponding physical addresses. Further, it comprises finding a matching entry for the virtual address in the set of entries using upper bits of the virtual address, wherein the matching entry comprises a physical address corresponding to the virtual address. Finally, it comprises finding a matching entry in the data cache memory using the physical address.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Soft Machines, Inc.Inventors: Mohammad A. ABDALLAH, Ravishankar Rao
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Patent number: 8838936Abstract: A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the processor, data for storing at a physical address in the non-volatile memory, the data being associated with a logical address of the host, storing, by the processor, the physical address in a first LtoP zone of a plurality of LtoP zones of the LtoP table, the LtoP table being stored in the volatile memory, adding, by the processor, the first LtoP zone to a list of modified zones, and storing, by the processor, a second LtoP zone of the plurality of LtoP zones in the non-volatile memory when a size of the list of modified zones exceeds a threshold.Type: GrantFiled: November 27, 2013Date of Patent: September 16, 2014Assignee: NXGN Data, Inc.Inventors: Nader Salessi, Joao Alcantara
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Patent number: 8831229Abstract: A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein each of the key segments has a start position and a segment length. The method also includes setting a transmission length belonging to each of key segments based on the start positions and the segment lengths of the key segments; assigning a transmission bit stream belonging to each of the key segments from the bits of the key according to the start positions and the transmission lengths of the key segments; determining a transmission sequence; and sending the start position, the segment length and the transmission bit stream belonging to each of the key segments to the encryption/decryption unit from the buffer memory based on the transmission sequence. Accordingly, the method can transport the key safely.Type: GrantFiled: December 1, 2011Date of Patent: September 9, 2014Assignee: Phison Electronics Corp.Inventor: Ching-Wen Chang
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Patent number: 8819392Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.Type: GrantFiled: July 17, 2012Date of Patent: August 26, 2014Assignee: Intel CorporationInventors: David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar, Shih-Lien Lu
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Publication number: 20140237157Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Applicant: Diablo Technologies Inc.Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone
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Patent number: 8812789Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.Type: GrantFiled: May 15, 2013Date of Patent: August 19, 2014Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Erich James Plondke, Lucian Codrescu
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Patent number: 8806102Abstract: A cache system includes a primary cache memory configured to input and output data between a computation unit, the primary cache memory includes multi-port memory units each including a storing unit that stores unit data having a first data size, a writing unit that simultaneously writes sequentially inputted plural unit data to consecutive locations of the storing unit, and an outputting unit that reads out and outputs unit data written in the storing unit, wherein when writing data having a second data size that is an arbitrary multiple of a first data size and is segmented into unit data to the primary cache memory, the data is stored in different multi-port memory units by writing the sequential unit data to a subset of the multi-port memory units, and writing the other sequential unit data to another subset of the multi-port memory units.Type: GrantFiled: January 25, 2011Date of Patent: August 12, 2014Assignee: Fujitsu LimitedInventor: Takahito Hirano
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Patent number: 8806142Abstract: Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or speculates about what the client may request in the future. Rather than await the client request (that may or may not ultimately be made), the service provides the unrequested anticipatory data to the client in the same data stream as the response data that actual responds to the specific client requests. The client may then use the anticipatory data to fully or partially respond to future requests from the client, if the client does make the request anticipated by the service. Thus, in some cases, latency may be reduced when responding to requests in which anticipatory data has already been provided. The service may give priority to the actual requested data, and gives secondary priority to the anticipatory data.Type: GrantFiled: June 24, 2013Date of Patent: August 12, 2014Assignee: Microsoft CorporationInventors: Nicholas Alexander Allen, Kenneth D. Wolf
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Patent number: 8806101Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.Type: GrantFiled: December 30, 2008Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis
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Patent number: 8782667Abstract: Embodiments of the present invention provide a method, system and computer program product for weather adaptive environmentally hardened appliances. In an embodiment of the invention, a method for weather adaptation of an environmentally hardened computing appliance includes determining a location of an environmentally hardened computing appliance. Thereafter, a weather forecast including a temperature forecast can be retrieved for a block of time at the location. As a result, a cache policy for a cache of the environmentally hardened computing appliance can be adjusted to account for the weather forecast.Type: GrantFiled: December 27, 2010Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Erik J. Burckart, Gennaro Cuomo, Andrew J. Ivory, Victor S. Moore, Aaron K. Shook
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Publication number: 20140189193Abstract: An image forming apparatus includes a function unit to perform functions of the image forming apparatus, and a control unit to control the function unit to perform the functions of the image forming apparatus. The control unit includes a processor core to operate in a virtual memory address, a main memory to operate in a physical memory address and store data used in the functions of the image forming apparatus, and a plurality of input/output (I/O) logics to operate in the virtual memory address and control at least one of the functions performed by the image forming apparatus. Each of the plurality of I/O logics translates the virtual memory address into the physical memory address corresponding to the virtual memory address and accesses the main memory.Type: ApplicationFiled: March 7, 2014Publication date: July 3, 2014Applicant: SAMSUNG Electronics, Co., Ltd.Inventor: Byoung-tae CHO
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Publication number: 20140189191Abstract: A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Ilan Pardo, Michael Behar, Oren Ben-Kiki, Dror Markovich
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Publication number: 20140189192Abstract: An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Shlomo Raikin, Oren Hamama, Robert S. Chappell, Camron B. Rust, Han S. Luu, Leslie A. Ong, Gur Hildesheim
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Patent number: 8756400Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.Type: GrantFiled: April 9, 2013Date of Patent: June 17, 2014Assignee: Micron Technology, Inc.Inventors: Troy A. Manning, Martin L. Culley, Troy D. Larsen
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Patent number: 8751751Abstract: A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set.Type: GrantFiled: January 28, 2011Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua
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Patent number: 8745307Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.Type: GrantFiled: May 13, 2010Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Cathy May, Naresh Nayar, Randal Craig Swanberg
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Publication number: 20140149632Abstract: Processors and methods for preventing lower level prefetch units from stalling at page boundaries. An upper level prefetch unit closest to the processor core issues a preemptive request for a translation of the next page in a given prefetch stream. The upper level prefetch unit sends the translation to the lower level prefetch units prior to the lower level prefetch units reaching the end of the current page for the given prefetch stream. When the lower level prefetch units reach the boundary of the current page, instead of stopping, these prefetch units can continue to prefetch by jumping to the next physical page number provided in the translation.Type: ApplicationFiled: November 29, 2012Publication date: May 29, 2014Applicant: APPLE INC.Inventors: Hari S. Kannan, Pradeep Kanapathipillai, Brian P. Lilly, Perumal R. Subramoniam, Mahnaz Sadoughi-Yarandi
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Patent number: 8719502Abstract: A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.Type: GrantFiled: March 30, 2012Date of Patent: May 6, 2014Assignee: Intel CorporationInventors: Christopher B. Wilkerson, Alaa R. Alameldeen, Jaydeep P. Kulkarni
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Publication number: 20140115225Abstract: A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.Type: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rahul Chandrakar, Venkatesh Sainath, Vaidyanathan Srinivasan
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Publication number: 20140115226Abstract: A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.Type: ApplicationFiled: February 11, 2013Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rahul Chandrakar, Venkatesh Sainath, Vaidyanathan Srinivasan
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Patent number: 8694924Abstract: A mobile terminal having a function of managing files and folders is disclosed. In one embodiment, the mobile terminal displays folder items representing one or more memory elements installed in or joined to the mobile terminal on a display unit when a request to perform a search function is inputted, and displays selection items corresponding to at least one of files included in the folder item and subfolders on the display unit when a select command for a folder item is inputted. At least one embodiment of the invention allows easy management of data (e.g., files, folders, etc.) stored in one or more memory devices installed in or joined to the mobile terminal.Type: GrantFiled: June 5, 2007Date of Patent: April 8, 2014Assignee: KT CorporationInventor: Sang-Joon Jung
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Patent number: 8688890Abstract: A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.Type: GrantFiled: December 5, 2006Date of Patent: April 1, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Blaine D. Gaither, Verna Knapp
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Patent number: 8688962Abstract: Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of data elements in response to a gather instruction. The apparatus includes memory comprising a plurality of memory rows including a memory row associated with the gather instruction. The apparatus further includes memory structure to store data element addresses accessed in response to the gather instruction.Type: GrantFiled: April 1, 2011Date of Patent: April 1, 2014Assignee: Intel CorporationInventors: Shlomo Raikin, Robert Valentine
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Patent number: 8688913Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.Type: GrantFiled: November 1, 2011Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Stephen L. Blinick, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
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Patent number: 8681169Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.Type: GrantFiled: December 31, 2009Date of Patent: March 25, 2014Assignee: Nvidia CorporationInventors: Jesse D. Hall, Jerome F. Duluk, Jr., Andrew Tao, Henry Moreton
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Publication number: 20140082252Abstract: Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory. Each set identifier indicates a set within a higher level cache directory. The mechanism looks up a second portion of the logical address in the higher level cache directory and compares each absolute address value received from the higher level cache directory to an absolute address received from a translation look-aside buffer to generate a higher level cache hit signal. The mechanism compares the higher level cache hit signal to each set identifier to generate a local cache hit signal and responsive to the local cache hit signal indicating a local cache hit, accesses the local cache based on the local cache hit signal.Type: ApplicationFiled: September 17, 2012Publication date: March 20, 2014Applicant: International Business Machines CorporationInventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, Barry W. Krumm
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Patent number: 8677049Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.Type: GrantFiled: April 13, 2009Date of Patent: March 18, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Mahadev S. Deshpande, Ronny L. Arnold, Josef A. Dvorak, Paul L. Rogers
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Patent number: 8677050Abstract: According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.Type: GrantFiled: November 12, 2010Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Wen-Tzer T. Chen, Diane G. Flemming, William A. Maron, Mysore S. Srinivas, David B. Whitworth
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Patent number: 8661179Abstract: A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.Type: GrantFiled: October 3, 2008Date of Patent: February 25, 2014Assignee: Agere Systems LLCInventors: Allen B. Goodrich, Alex Rabinovitch, Assaf Rachlevski, Alex Shinkar
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Patent number: 8655842Abstract: Embodiments are directed towards modifying a distribution of writers as either a push writer or a pull writer based on a cost model that decides for a given content reader whether it is more effective for the writer to be a pull writer or a push writer. A cache is maintained for each content reader for caching content items pushed by a push writer in the content writer's push list of writers when the content is generated. At query time, content items are pulled by the content reader based on writers a content reader's pull list. One embodiment of the cost model employs data about a previous number of requests for content items for a given writer for a number of previous blended display results of content items. When a writer is determined to be popular, mechanisms are proposed for pushing content items to a plurality of content readers.Type: GrantFiled: August 17, 2009Date of Patent: February 18, 2014Assignee: Yahoo! Inc.Inventor: Zhichen Xu
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Patent number: 8627039Abstract: An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More specifically, data access requests to the cloud computing environment are monitored to identifying data addresses having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein the creating of the memory page includes creating a cross-sectional partition from the multi-dimensional cluster. The multi-dimensional clusters and the memory page are stored in the cloud computing environment. A request for a data object in the cloud computing environment is received from a user interface. The data address corresponding to the data object is identified and mapped to the multi-dimensional cluster and/or the memory page. The memory page is transferred to the user interface.Type: GrantFiled: November 9, 2011Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventor: Maharaj Mukherjee
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Publication number: 20140006681Abstract: An architecture is described for performing memory management in a virtualization environment. Multiple levels of caches are provided to perform address translations, where at least one of the caches contains a mapping between a guest virtual address and a host physical address. This type of caching implementation serves to minimize the need to perform costly multi-stage translations in a virtualization environment.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: Broadcom CorporationInventors: Wei-Hsiang CHEN, Ricardo RAMIREZ, Hai N. NGUYEN
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Patent number: 8619790Abstract: Certain embodiments of the invention may be found in a method and system for an adaptive cache for caching context and for adapting to collisions in session lookup table. A network processor chip may comprise an on-chip cache that stores transport control blocks (TCB) from a TCB array in external memory to reduce latency in active transmission control protocol/Internet protocol (TCP/IP) sessions. The on-chip cache may comprise a tag portion implemented using a content addressable memory (CAM) and a data portion implemented using a random access memory (RAM). When a session collision occurs the context of a subsequent network connection may be stored in a data overflow portion of an overflow table in the on-chip cache. A search key associated with the subsequent network connection that comprises network connection parameters may be stored in a tag overflow portion of the overflow table.Type: GrantFiled: September 16, 2005Date of Patent: December 31, 2013Assignee: Broadcom CorporationInventor: Fong Pong
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Patent number: 8599707Abstract: Methods and apparatus for operating a mobile device based upon a power capability of the mobile device are disclosed. In one embodiment, the mobile device includes a network selection component configured to select a particular transceiver for communication based upon the power capability of the mobile device and a quality of service associated with available networks. In addition, a cache management component is configured to increase, based upon an indication of the power capability of the mobile device, a size of the cache that is available for requested content so as to increase the likelihood that subsequent requests for the content will be loaded from the mobile device. Moreover, some variations of the mobile device are capable of providing an indication of a power capability of the mobile device to a remote server so the remote server may modify the requested content based upon the power capability.Type: GrantFiled: November 18, 2010Date of Patent: December 3, 2013Assignee: Qualcomm Innovation Center, Inc.Inventor: Dinesh K. Garg
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Patent number: 8566564Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.Type: GrantFiled: December 13, 2012Date of Patent: October 22, 2013Inventors: H. Peter Anvin, Guillermo J. Rozas, Alexander Klaiber, John P. Banning
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Publication number: 20130275649Abstract: An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the data pages are grouped by page-color, and then all the data pages of the weak locality dataset are scanned in a sequence of page-color grouping. Further, a number of memory pages having the same page-color are preset as a page-color queue, in which the page-color queue serves as a memory cache before a memory page is loaded into a CPU cache; the data page of the weak locality dataset first enters the page-color queue in an asynchronous mode, and is then loaded into the CPU cache to complete data processing. Accordingly, cache conflicts between datasets with different data locality strengths can be effectively reduced.Type: ApplicationFiled: May 16, 2012Publication date: October 17, 2013Applicant: RENMIN UNIVERSITY OF CHINAInventors: Yan-Song Zhang, Shan Wang, Xuan Zhou, Min Jiao, Zhan-Wei Wang