Abstract: An approach is provided for providing an application-level cache. A caching application configures at least one memory of a mobile terminal into an application-level cache with a locked region and a floating region. The caching application then causes, at least in part, actions that result in caching, into each of the locked region and the floating region, of data items that are anticipated to be requested via an application of the mobile terminal.

Abstract: A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache for the processor core includes the data corresponding to the effective address of the access instruction. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address. If the level one cache includes the data corresponding to the effective address, the data for the access instruction is provided from the level one cache.

Abstract: A data recording method including, when moving data stored in a cache to a data storage medium, selecting one cache area from an extended cache area group of the data storage medium by using managing information of a translation layer, moving the data stored in the cache to the selected cache area by using a physical address of the data storage medium on the selected cache area, and updating the managing information of the translation layer, wherein the managing information of the translation layer includes a physical block address-based address of the extended cache area group in the data storage medium.

Abstract: One embodiment of the present invention sets forth a technique for computing virtual addresses for accessing thread data. Components of the complete virtual address for a thread group are used to determine whether or not a cache line corresponding to the complete virtual address is not allocated in the cache. Actual computation of the complete virtual address is deferred until after determining that a cache line corresponding to the complete virtual address is not allocated in the cache.

Abstract: Described embodiments provide a media controller that determines the size of a cache of data being transferred between a host device and one or more sectors of a storage device. The one or more sectors are segmented into a plurality of chunks, and each chunk corresponds to at least one sector. The contents of the cache are managed in a cache hash table. At startup of the media controller, a buffer layer module of the media controller initializes the cache in a buffer of the media controller. During operation of the media controller, the buffer layer module determines a number of chunks allocated to the cache. Based on the number of chunks allocated to the cache, the buffer layer module updates the size of the of the cache hash table.

Abstract: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.

Abstract: Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controlling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.

Abstract: A method of optimizing the delivery of a set of data elements from a first device to a second device. The method includes retrieving from a data source the set of data elements, including a first subset of the set of data elements, a second subset of the set of data elements, and a third subset of the set of data elements. The method also includes transferring the first subset of the set of data elements to the second device. The method further includes selecting a forth subset of the set of data elements, wherein the forth subset can be comprised of data elements from the first subset and the second subset; or wherein the forth subset can be comprised of data elements from the second subset and the third subset. The method also includes transferring a forth subset of the set of data elements to the second device.

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: A microprocessor breakpoint checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: A coherency control system includes a logical-physical address translation unit which translates a logical address including a first tag and an index address into a physical address including a second tag and the index address, a request output unit which transmits a load request, a corresponding state storage unit which stores a relation state between an area of the second storage apparatus and an area of the first storage apparatus based on the way number included in the load request and the second tag and the index address of the physical address also included in the load request which has been received, and an invalidation instructing unit which transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in the store request and the relation state stored in the corresponding state storage unit.

Abstract: A data transfer method for a network system wherein a plurality of computers are connected to each other through a switched network is improved in terms of the TLB hit ratio. Each of the computers includes a main storage device, a processor for issuing a communication process command and a communication device for processing the communication command from the processor and communicating with another one of the computers through a switched network. The communication device includes a transmission section and a reception section each of which includes a TLB for retaining a plurality of TLB entries. When a communication command including information of that one of the computers which is a sending source is issued from the processor, the reception section determines that one of the TLB entries which is to be used in accordance with the computer of the sending source.

Abstract: A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.

Abstract: A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

Abstract: According to a cache memory control method of an embodiment, a data write position in a segment of a cache memory is changed to an address to which a lower bit of a logical block address of write data is added as an offset. Then, even if writing is completed within the segment of the cache memory, the remaining regions of the segment is not wasted.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

Abstract: The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain a physical tag of a physical page by performing address translation on the virtual address; and a comparing unit 16 operable to compare a physical tag TAG obtained by the physical tag obtaining unit 15 with each tag information piece TAG(i) belonging to cache lines corresponding to the virtual indexes and output from the tag array 11a based on the virtual indexes obtained by the virtual index obtaining unit 13, and determines a cache hit/miss.

Abstract: Managing operations in a first compute node of a multi-computer system. A remote write may be received to a first address of a remote compute node. A first data structure entry may be created in a data structure, which may include the first address and status information indicating that the remote write has been received. Upon determining that the local cache of the first compute node has been updated with the remote write, the remote write may be issued to the remote compute node. Accordingly, the first data structure entry may be released upon completion of the remote write.

Abstract: Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module (2) is provided with a page cache control unit (217) that stores page cache information (224) in the non-volatile memory (22) of the information recording module (2) and performs control such that a specific physical block is used as a cache when writing small-sized data. Also, an access module (1) is provided with a page cache information setting unit (104) that sets information necessary for page cache control in the information recording module (2).

Abstract: Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space.

Abstract: Aspects of the subject matter described herein relate to initializing a database to be used for synchronization. In aspects, a peer in a synchronization topology creates a consistent copy of its database. Metadata associated with this copy is marked to distinguish changes made before the copy was created from changes made after the copy was created and also that the copy needs to be prepared before being used in synchronization. Any client may then download the copy and start immediately reading and modifying its downloaded copy. Before the client synchronizes its copy with other databases already in the synchronization topology, the downloaded copy is prepared for use in the topology using the markers.

Abstract: Clustering related objects in a region-based garbage collector is solved by associating one or more regions with each cluster, and allocating objects from a region belonging to the primary cluster for the object. Relatedness may refer to, e.g., proximity to a cluster center (such as topic) in a persistent knowledge base or a home node in a distributed object system. The cluster for an object may be determined, e.g., from reachability from particular roots or objects during global tracing. For new objects, the initial cluster may be guessed based on history of where objects allocated in that call site have recently been clustered (possibly several stack frames deep).

Abstract: A computing system is provided. A flash memory device includes at least one mapping block, at least one modification block and at least one cache block. A processor is configured to perform: receiving a write command with a write logical address and predetermined data, loading content of a cache page from the cache block corresponding to the modification block according to the write logical address to a random access memory device in response to that a page of the mapping block corresponding to the write logical address has been used, the processor, reading orderly the content of the cache page stored in the random access memory device to obtain location information of an empty page of the modification block, and writing the predetermined data to the empty page according to the location information. Each cache page includes data fields to store location information corresponding to the data has been written in the pages of the modification block in order.

Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.

Abstract: An integrated circuit is provided with at least one processing unit (TM), a cache memory (L2 BANK) having a plurality of memory modules, and remapping means (RM) for performing an unrestricted remapping within said plurality of memory modules. Accordingly, faulty modules can be remapped without limitations in order to optimise the utilization of the memory modules by providing an even distribution of the faulty modules.

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node; assigning a modified cache state to said cache data block in response to initiating said first store operation. The method may further include initiating a first load operation to said cache data block from a second processing node; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation, where the pairwise-shared directory state is distinct from a shared directory state.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node and initiating a first load operation to said cache data block from a second processing node subsequent to initiating said first store operation; and assigning a pairwise-shared directory state to a coherence directory entry corresponding to said cache data block in response to initiating said first load operation. The method may further include initiating a second store operation to said cache data block from said second processing node subsequent to initiating said first load operation; and assigning a migratory directory state to said coherence directory entry in response to initiating said second store operation, where the migratory directory state is distinct from a modified directory state.

Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

Abstract: Embodiments of the present invention are directed to a scheme in which information as to the future behavior of particular software is used in order to optimize cache management and reduce cache pollution. Accordingly, a certain type of data can be defined as “short life data” by using knowledge of the expected behavior of particular software. Short life data can be a type of data which, according to the ordinary expected operation of the software, is not expected to be used by the software often in the future. Data blocks which are to be stored in the cache can be examined to determine if they are short life data blocks. If the data blocks are in fact short life data blocks they can be stored only in a particular short life area of the cache.

Abstract: A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.

Abstract: In an information processing apparatus of this invention having a cache memory, a TLB and a TSB, a second retrieval unit retrieves a second physical address from an address translation buffer by using a second virtual address corresponding one-to-one to a first virtual address, and a prefetch controller enters a first address translation pair of the first virtual address from an address translation table into a cache memory by using a second physical address which is a result of the retrieval, thereby largely shortening the processing time of a memory access when a TLB miss occurs at the time of the memory access.

Abstract: Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.

Abstract: A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.

Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

Abstract: A memory access determination circuit includes a counter that outputs a first value counted by using a first reference value, and a control unit that makes a cache determination of an address corresponding to an output of the counter, wherein, when a cache miss occurs for the address, the counter outputs a second value by using a second reference value.

Abstract: One embodiment includes a system comprising a processor configured to read and write data packets via a data bus to and from at least one additional hardware device. The system also comprises a data buffer configured to store a plurality of consecutive related flits associated with at least one of the data packets in one of a plurality of addressable locations of the data buffer. The system further comprises a pointer memory configured to store a respective pointer associated with each of the plurality of addressable locations of the data buffer.

Abstract: One embodiment provides a system that includes a processor with a unified cache structure that facilitates accessing translation table entries (TTEs). This unified cache structure can simultaneously store program instructions, program data, and TTEs. During a memory access, the system receives a virtual memory address. The system then uses this virtual memory address to identify one or more cache lines in the unified cache structure which are associated with the virtual memory address. Next, the system compares a tag portion of the virtual memory address with the tags for the identified cache line(s) to identify a cache line that matches the virtual memory address. The system then loads a translation table entry that corresponds to the virtual memory address from the identified cache line.

Abstract: A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.

Abstract: A storage apparatus using a non-volatile memory, which retains data even after power interruption, as its cache and a method of managing the same are provided. The storage apparatus includes a main storage medium, a non-volatile memory used as a cache of the main storage medium, a region of the non-volatile memory being divided into a fixed region and a non-fixed region according to whether or not data is fixed, and a block management unit managing physical blocks by means of virtual addresses, the physical blocks being allocated to the non-volatile memory.

Abstract: A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.

Abstract: A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer.

Abstract: A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: Profiles hold cache settings externally from a requesting resource. The external cache settings stored within a profile may be associated with one or more resources. This allows the external cache settings for a group of resources to be managed from one location rather than having to change the internal cache settings for each resource. When a resource is processed by the server, the external cache settings are obtained from a cache profile and applied to the requesting resource. The external cache settings may also be merged with any internal resource settings. As a result of merging the settings some of the external cache settings and/or some of the internal cache settings may be overridden.

Abstract: An apparatus having a memory and a controller is disclosed. The memory may be configured to (i) store a plurality of cache lines, each of the cache line comprising a plurality of locations including a respective end location and (ii) accessing a particular one of the cache lines identified by a cache address signal. The controller may be configured to (i) buffer a plurality of line pointers, each of the line pointers identifying a respective boundary one of the locations in one of the cache lines and (ii) generate the cache address signal in response to a processor address signal hitting a given one of the locations residing between the respective boundary location and the respective end location.

Abstract: There is provided a storage system capable of handling a large amount of control data at low cost in high performance. The storage system includes a cache memory for temporarily storing data read/written between a host computer and a disk array, a CPU for making a control related to data transfer, and a local memory for storing control data utilized by the CPU. The disk array has a first user data storing area for storing user data and a control data storing area for storing all control data. A control unit has a virtualization unit for allocating a memory space of the control data storing area to a virtual address accessible from the CPU, reading the control data specified by the virtual address to a physical address of the local memory, and transferring the control data to the CPU.

Abstract: In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing device. That is, the associative cache implements a fully associative map between a predetermined set of addresses and data values, employing only a single tag fetch comparison.