Abstract: An embodiment of the invention provides a method for effective memory clustering to minimize page faults and optimize memory utilization. More specifically, the method monitors data access requests to secondary storage and identifies data addresses in secondary storage having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein a cross-sectional partition is created (sliced) from the multi-dimensional cluster. The method receives a request for a data object in secondary storage and identifies a data address corresponding to the requested data object. The data address is mapped to the multi-dimensional cluster and/or the memory page; and, the memory page is transferred to a data cache in primary storage.

Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist of single-port devices that are not inherently capable of parallel write and read operations.

Abstract: A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache memory contains the data being requested. The data associated with the request is returned from the cache memory without accessing the memory location if there is a cache hit. The data associated is returned from the main memory if there is a cache miss. In response to the cache miss, it is determined whether there have been a number of accesses within a predetermined period of time. A cache entry is allocated from the cache memory to cache the data if there have been a predetermined number of accesses within the predetermined period of time.

Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.

Abstract: A cache memory comprises a data array that stores a cashed block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, when the address stored in the second address array results in a cache hit during a period before a second block which has caused the cache miss is read from a memory and written into the data array.

Abstract: A method and system for providing a binary instrumentation tool to detect memory problems in a runtime application executing on a computer system includes identifying one or more functions or statements in the runtime application. A plurality of compiler annotations defining essential functional characteristic data of each of the plurality of functions is generated by a compiler when compiling the user program from source code to an executable binary code. A program error detector is configured to provide a checker code based on guidelines provided by of the plurality of compiler annotations associated with the function. The program error detector generates a modified function code for the identified function by inserting the checker code into a function code for the corresponding function. A modified executable binary code for the runtime application is then generated by replacing the function code for the function with the corresponding modified function code.

Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active.

Abstract: Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. Only a subset of the plurality of hierarchy levels may be loaded to memory, thereby reducing the memory “footprint” of cache metadata and expediting the process of restoring the cache metadata during startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot. Thereafter, as requests to read data items on the storage medium are processed using cache metadata to identify addresses at which the data items are stored in cache, the identified addresses may be stored in memory.

Abstract: A cache-aware Bloom filter system segments a bit vector of a cache-aware Bloom filter into fixed-size blocks. The system hashes an item to be inserted into the cache-aware Bloom filter to identify one of the fixed-size blocks as a selected block for receiving the item and hashes the item k times to generate k hashed values for encoding the item for insertion in the in the selected block. The system sets bits within the selected block with addresses corresponding to the k hashed values such that accessing the item in the cache-aware Bloom filter requires accessing only the selected block to check the k hashed values. The size of the fixed-size block corresponds to a cache-line size of an associated computer architecture on which the cache-aware Bloom filter is installed.

Abstract: A method, system and computer program product for interfacing between information requesters and information sources. In an embodiment, information is obtained from one or more information sources in response to client requests. In an embodiment, information received from information sources is cached for future use, such as for future client requests. In a caching embodiment, information can also be received by monitoring traffic between an information source and a third party, and/or by proactively querying the information sources. Proactive queries can be generated to populate a cache and/or to update presently cached information. In a caching embodiment, the invention includes methods for determining whether to respond to a request for information out-of-cache and/or with real-time information from an information source. In an embodiment, the invention interfaces with airline availability information sources.

Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

Abstract: A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Abstract: A cache system includes a primary cache memory configured to input and output data between a computation unit, the primary cache memory includes multi-port memory units each including a storing unit that stores unit data having a first data size, a writing unit that simultaneously writes sequentially inputted plural unit data to consecutive locations of the storing unit, and an outputting unit that reads out and outputs unit data written in the storing unit, wherein when writing data having a second data size that is an arbitrary multiple of a first data size and is segmented into unit data to the primary cache memory, the data is stored in different multi-port memory units by writing the sequential unit data to a subset of the multi-port memory units, and writing the other sequential unit data to another subset of the multi-port memory units.

Abstract: A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way within a plurality based on a first portion of the address. The control logic may match the first portion of the address to a predefined value in a mapping table, wherein the predefined value in the mapping table is associated with the way. In addition, the control logic may map the address to a set within cache based on a second portion of the address.

Abstract: A method of merging subsequent updates to a memory location includes receiving, at a first stage in an update pipeline, a first request to update a status word at a first address of a cache memory and receiving the status word from the cache memory. The method continues with determining, at a stage subsequent to the first stage, that a second request to update the status word has been received. Further included is updating the status word according to the first and second requests to form an updated status word and writing the updated status word to the cache memory.

Abstract: Frame data stored in an external memory is partitioned into a plurality of macroblocks, and a plurality of access units each comprising at least one macroblock are provided. A plurality of frames are fetched from the external memory by loading the plurality of access units in a predetermined sequence. A current data for decoding a macroblock of the first access unit and a reference data for decoding a macroblock of the second access unit are loaded from the first access unit, and respectively mapped to a first memory group and a second memory group of a circular cache according to the frame width.

Abstract: A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.

Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.

Abstract: A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.

Abstract: A memory control device for controlling an access from a processing unit to a cache memory, the memory control device includes: an address estimation circuit for receiving a first read address of the cache memory from the processing unit and estimating a second read address on the basis of the first read address; an access start detection circuit for detecting an access start of accessing cache memory at the first read address and outputting an access start signal; a data control circuit for receiving read data from the cache memory and for outputting the read data to the processing unit; and a clock control circuit for controlling a read clock to be output to the processing unit in response to the access start signal, the processing unit receiving the read data from the data control circuit with the read clock.

Abstract: A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effective address matches the requested effective address, the cache manager identifies a corresponding cache location and retrieves the data from the identified cache location. However, when the most recently used effective address fails to match the requested effective address, the cache manager determines whether the requested effective address matches a subsequent effective address stored in the mapped tag vector. When the cache manager determines a match to a subsequent effective address, the cache manager identifies a different cache location corresponding to the subsequent effective address and retrieves the data from the different cache location.

Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Abstract: In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing device. That is, the associative cache implements a fully associative map between a predetermined set of addresses and data values, employing only a single tag fetch comparison.

Abstract: A data storage enclosure management system of a plurality of service processors is configured to communicate externally via a pair of FC-AL loops. Lead and subsidiary service processors are defined and lead service processors connect to ones of the FC-AL loops with an FC-AL address, and the lead and subsidiary service processors are connected by a secondary communication link. The lead service processor(s) employ an identifier unassociated with the FC-AL address to differentiate communications of the lead service processor from communications of an associated subsidiary service processor, the lead service processor serving as a proxy for the associated subsidiary service processor with respect to the FC-AL address and communicating with the associated subsidiary service processor via the secondary communication link.

Abstract: A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract: An approach is provided for providing an application-level cache. A caching application configures at least one memory of a mobile terminal into an application-level cache with a locked region and a floating region. The caching application then causes, at least in part, actions that result in caching, into each of the locked region and the floating region, of data items that are anticipated to be requested via an application of the mobile terminal.

Abstract: A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache for the processor core includes the data corresponding to the effective address of the access instruction. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address. If the level one cache includes the data corresponding to the effective address, the data for the access instruction is provided from the level one cache.

Abstract: A data recording method including, when moving data stored in a cache to a data storage medium, selecting one cache area from an extended cache area group of the data storage medium by using managing information of a translation layer, moving the data stored in the cache to the selected cache area by using a physical address of the data storage medium on the selected cache area, and updating the managing information of the translation layer, wherein the managing information of the translation layer includes a physical block address-based address of the extended cache area group in the data storage medium.

Abstract: One embodiment of the present invention sets forth a technique for computing virtual addresses for accessing thread data. Components of the complete virtual address for a thread group are used to determine whether or not a cache line corresponding to the complete virtual address is not allocated in the cache. Actual computation of the complete virtual address is deferred until after determining that a cache line corresponding to the complete virtual address is not allocated in the cache.

Abstract: Described embodiments provide a media controller that determines the size of a cache of data being transferred between a host device and one or more sectors of a storage device. The one or more sectors are segmented into a plurality of chunks, and each chunk corresponds to at least one sector. The contents of the cache are managed in a cache hash table. At startup of the media controller, a buffer layer module of the media controller initializes the cache in a buffer of the media controller. During operation of the media controller, the buffer layer module determines a number of chunks allocated to the cache. Based on the number of chunks allocated to the cache, the buffer layer module updates the size of the of the cache hash table.

Abstract: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.

Abstract: Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controlling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: A method of optimizing the delivery of a set of data elements from a first device to a second device. The method includes retrieving from a data source the set of data elements, including a first subset of the set of data elements, a second subset of the set of data elements, and a third subset of the set of data elements. The method also includes transferring the first subset of the set of data elements to the second device. The method further includes selecting a forth subset of the set of data elements, wherein the forth subset can be comprised of data elements from the first subset and the second subset; or wherein the forth subset can be comprised of data elements from the second subset and the third subset. The method also includes transferring a forth subset of the set of data elements to the second device.

Abstract: A microprocessor breakpoint checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: A coherency control system includes a logical-physical address translation unit which translates a logical address including a first tag and an index address into a physical address including a second tag and the index address, a request output unit which transmits a load request, a corresponding state storage unit which stores a relation state between an area of the second storage apparatus and an area of the first storage apparatus based on the way number included in the load request and the second tag and the index address of the physical address also included in the load request which has been received, and an invalidation instructing unit which transmits an invalidation instruction including the index address and the way number based on the second tag of the physical address included in the store request and the relation state stored in the corresponding state storage unit.

Abstract: A data transfer method for a network system wherein a plurality of computers are connected to each other through a switched network is improved in terms of the TLB hit ratio. Each of the computers includes a main storage device, a processor for issuing a communication process command and a communication device for processing the communication command from the processor and communicating with another one of the computers through a switched network. The communication device includes a transmission section and a reception section each of which includes a TLB for retaining a plurality of TLB entries. When a communication command including information of that one of the computers which is a sending source is issued from the processor, the reception section determines that one of the TLB entries which is to be used in accordance with the computer of the sending source.

Abstract: A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.

Abstract: A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

Abstract: According to a cache memory control method of an embodiment, a data write position in a segment of a cache memory is changed to an address to which a lower bit of a logical block address of write data is added as an offset. Then, even if writing is completed within the segment of the cache memory, the remaining regions of the segment is not wasted.

Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.

Abstract: The cache memory system 1 comprises: a virtual index obtaining unit 13 operable to obtain, based on a virtual address, virtual indexes of an access-target cache line and a cache line potentially having a cache-aliasing relationship with the access-target cache line; a physical tag obtaining unit 15 operable to obtain a physical tag of a physical page by performing address translation on the virtual address; and a comparing unit 16 operable to compare a physical tag TAG obtained by the physical tag obtaining unit 15 with each tag information piece TAG(i) belonging to cache lines corresponding to the virtual indexes and output from the tag array 11a based on the virtual indexes obtained by the virtual index obtaining unit 13, and determines a cache hit/miss.

Abstract: Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space.

Abstract: Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module (2) is provided with a page cache control unit (217) that stores page cache information (224) in the non-volatile memory (22) of the information recording module (2) and performs control such that a specific physical block is used as a cache when writing small-sized data. Also, an access module (1) is provided with a page cache information setting unit (104) that sets information necessary for page cache control in the information recording module (2).

Abstract: Managing operations in a first compute node of a multi-computer system. A remote write may be received to a first address of a remote compute node. A first data structure entry may be created in a data structure, which may include the first address and status information indicating that the remote write has been received. Upon determining that the local cache of the first compute node has been updated with the remote write, the remote write may be issued to the remote compute node. Accordingly, the first data structure entry may be released upon completion of the remote write.

Abstract: Clustering related objects in a region-based garbage collector is solved by associating one or more regions with each cluster, and allocating objects from a region belonging to the primary cluster for the object. Relatedness may refer to, e.g., proximity to a cluster center (such as topic) in a persistent knowledge base or a home node in a distributed object system. The cluster for an object may be determined, e.g., from reachability from particular roots or objects during global tracing. For new objects, the initial cluster may be guessed based on history of where objects allocated in that call site have recently been clustered (possibly several stack frames deep).