Abstract: This invention provides a method and apparatus for controlling the current drawn in a multi-bank memory device, for example, in a multi-bank memory system. The above and other features and advantages of the invention are achieved by a method and apparatus which controls access to a memory device to prevent an over-current condition. Each memory request is processed for each memory bank as an arbitrated event. A request is coordinated with the local memory controller circuitry controlling access to the memory bank. The memory bank is checked for its availability. The total current demand of the memory device is determined. If the memory bank request would not create an over-current condition and the memory bank is available, then the memory bank request is acknowledged and the memory request is carried out. Also provided is a method of fabricating such a memory device and also a method of operating such a memory device to access a selected memory bank.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.

Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.

Abstract: A method and computer system for accessing initialization data stored in a boot ROM's memory space which is not used by a BIOS contained in the boot ROM. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the boot ROM and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.

Abstract: A semiconductor integrated circuit device includes a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit. A sense amplifier unit control circuit electrically disconnects sense amplifier circuits from the main memory and data is transferred from the main memory to the auxiliary memory in this disconnected state. A data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to the main memory unit.

Abstract: Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks. In one embodiment, each bank includes data from one cache way. In another embodiment, each bank includes data from each way. In another embodiment, memory array banks contain data corresponding to sequential cache lines.

Abstract: In a semiconductor memory device, a memory cell array has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit receives the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and receives the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit receives the even read data from the second even data bus and the odd read data from the second odd data bus, and outputs one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: A memory system which includes a bank of memory chips, a memory interface, and a memory controller. The memory interface stretches a sample period for data from the bank of memory chips, and provides a sufficiently wide timing margin to enable the memory chips to work reliably across various process conditions.

Abstract: A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

Abstract: An addressing scheme to allow for a flexible DRAM configuration.

Abstract: A method for conducting checkpointing within a writeback cache having a cache memory with at least two memory banks. In one embodiment, a first pointer is set to indicate which cache entry of the at least two memory banks contains current data. A second pointer is set to indicate which cache entry of the at least two memory banks contains checkpoint data. Checkpointing is performed by selectively controlling said second pointer or said first pointer.

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.

Abstract: In a system having multiple master devices coupled to a shared resource, methods and structure for a state machine based memory model associated with each bank of memory to provide an arbiter with information for generating optimal sequences of memory commands to enable improved memory subsystem bandwidth utilization. The memory model corresponding to each bank of memory emulates the latencies involved with switching of active rows or pages in the corresponding bank. Signals generated by the memory model are applied to the arbiter to enable the arbiter to efficiently determine the optimal timing for generation of memory access commands corresponding to that bank.

Abstract: A chip select circuit is based on a multiplexed bus having a chip select phase, an address phase, and a data phase. During the chip select phase, a chip select latch receives chip select signals from the multiplexed bus at one input and a chip select enable signal at a second input. The chip select latch has a plurality of outputs to the chip select inputs of a plurality of connected devices. Based on the chip select signals from the multiplexed bus, one of the plurality of outputs enables a selected connected device. During the address phase, an address latch receives address signals from the multiplexed bus at a first input and an address enable signal at a second inputs. The output of the address latch passes the address signals to the address inputs of the plurality of connected devices. The chip select circuit is operative to used the multiplexed bus to select one of the connected devices using the single chip select enable signal without requiring further enabling/control signals.

Abstract: In a system having multiple master devices coupled to a shared resource, methods and structure for generating apriori information by an arbiter of the shared resource to enable the shared resource to better utilize the bandwidth of the shared resource. A first preferred embodiment of the invention provides an arbiter coupling a shared memory controller to a plurality of master devices generating memory requests for the memory controller. The arbiter preferably detects memory requests from another master device to detect when a next request is directed to a different bank of memory. Apriori information indicative of such a change in banks is sent to the memory controller in advance of the memory request that will require the change of banks. This apriori information enables the memory controller to control the sequence of commands applied to the memory subsystem to optimize utilization of the memory subsystem and hence improve system performance.

Abstract: A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention can include a memory system comprising a memory controller, and a synchronous memory device coupled to the memory controller. The synchronous memory includes a plurality of non-volatile elements, and control circuitry to read a status of the plurality of non-volatile fuses during an initialization operation. The memory has input command connections coupled to receive an initialization command from the memory controller. The control circuitry initiates the initialization operation in response to the initialization command.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A memory subsystem including error correction. A memory subsystem includes a memory controller and system memory including a plurality of memory modules. The system memory may be coupled to the memory controller by a memory interconnect. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The memory controller may store portions of a data segment across at least two of the memory modules. The memory controller may further store parity of the portions of the data segment in a corresponding location of another of the memory modules.

Abstract: A system and method for providing dynamic configuration Read Only Memory (ROM) using double image buffers for use with serial bus devices. The dynamic configuration ROM may be updated while linked to the serial bus and with little or no risk of publishing inconsistent configuration ROM information to other nodes on the bus. The dynamic configuration ROM comprises first and second configuration ROM images, one set to active, the other set to update. The dynamic configuration ROM publishes the configuration entries from the active configuration ROM image. Modifications to the configuration ROM are stored in a database. The update configuration ROM image is constructed from entries made to the database. After the construction of the update configuration ROM image is completed, the dynamic configuration ROM switches the states of the ROM images and transmits a serial bus reset signal.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.

Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a single instruction stream, multiple data stream (SIMD) system, and the processing elements can be the multiple data paths of the SIMD system. Each processing element or data path is associated with an identifying value which distinguishes it from the other elements. A memory, which can be configured as an interleaved memory including multiple memory banks, stores data accessed by the processing elements. The data can be a table used for table look-ups for such functions as mathematical operations. Also, multiple copies of the table can be stored in multiple respective banks of the memory. An instruction calling for a memory access such as a table look-up is received. The instruction contains address information which can be a starting address of a table in memory.

Abstract: An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a write command to the SDRAM 300 when a request is made to access the SDRAM 300, without deactivating the accessed row, until a detection signal that detects the last column is asserted. The SDRAM access control section deactivates the accessed row when the detection signal is asserted.

Abstract: A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance.

Abstract: Additional clock-outs are included on DRAMs in a multiple Dual In-Line Module Memory (DIMM) system having DRAMs of different data widths. The additional clock-outs balance the loads seen by the DRAM clock-out and data-out, thereby reducing signal skew between the DRAM data and clock lines. Additionally, in a second embodiment, every other clock line in a series of DRAMs comprising a DIMM are left unconnected. The data from the non connected DRAMs is clocked using the clock line of its neighbor.

Abstract: In a data processing arrangement that includes multiple processing circuits, a group of storage elements provides temporary storage of data intended for the processing circuits. An element selection circuit enables a single storage element to be selected from a plurality of storage elements in order to supply the content of the selected storage element to an input of a processing circuit. A group selection circuit enables a group of storage elements to be selected from a plurality of separate groups of storage elements in order to supply the contents of all the storage elements forming part of the selected group to an input of another processing circuit. Such an arrangement affords a flexible and efficient use of all the storage elements. As a result, a comparatively small number of storage elements are necessary, which leads to cost reduction. The relevant arrangement may be employed in, for example, a digital signal processor capable of (finite impulse response) FIR filtering.

Abstract: Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is received by the memory. A software command sequence is provided to the memory device where the software command sequence was constructed by generating a command sequence of n cycles and providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, where m is less than n. The data input buffers are returned to an off state upon completion of a program or erase operation defined in the received command sequence.

Abstract: In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

Abstract: In a cluster-structured disk subsystem, when creating a volume for an online backup separately from a volume for normal I/O, such creation is desired to be achieved for any volume under the subsystem. Further, with the increase in capacity of the subsystem, it becomes more difficult for a user to determine where to place a volume to which data is copied. The present invention makes it possible to reference/renew snapshot control information in shared memory of other clusters and achieves a snapshot between clusters via an inter-cluster connecting mechanism. Control is performed inside/outside the cluster, and a volume to which data is copied is suggested to the user.

Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

Abstract: A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.

Abstract: A circuit and method of operation for combining commands in a DRAM (dynamic random access memory) are revealed. The method applies to DRAMs having a plurality of memory banks or arrays. The method combines commands to rows on different memory banks, and the method also combines row and column commands on different memory banks. The method eliminates steps in a sequence of commands, and may significantly increase speed of input/output to a DRAM.

Abstract: The present invention provides a memory control apparatus capable of efficiently reducing power consumption. The memory control apparatus controls power consumption for refreshing on a unit region-by-unit region basis. A determination section 22 receives an allocate request from an application and determines whether or not data requires refreshing based on the allocate request. Next, a memory allocating section 23 allocates a memory region within a first memory bank to data having been determined to require refreshing and allocates amemory region within a second memory bank to data having been determined to require no refreshing. A memory control section 25 specifies the first memory bank as a refresh region for refreshing and specifies the second memory region as a non-refresh region which is prevented from being refreshed.

Abstract: A low-end microprocessor 10 includes a stack pointer 18 storing a word SPV, a comparator 17 comparing the SPV with a given value ADR1, an inverter 19 inverting the compared result CP, and an AND gate 16 receiving a write request signal WR from a CPU 11 and the output of the inverter 19. The AND gate 16 provides its output to the write enable signal input WE of a memory 12 in order to determine enabling/disabling of writing according to the depth of stack.

Abstract: A cache memory organized into banks of subarrays includes repeaters for connecting to the data provided by the subarrays to a global data bus. The repeaters comprise a logic gate providing either a NAND or NOR function coupled in series with an inverter. The logic gate has a first input connected to receive a first logic value of a bus line, and a second input coupled to receive data output from a subarray. The inverter drives the first logic value onto the bus line when the cache bank subarray is inactive, and drives the data value from the subarray onto the bus line when the cache bank subarray is activate.

Abstract: A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A memory controlling device is controlled by a CPU to enable information to be read from memory when the memory starts an operation. The memory is capable of retaining data during a power off state and the data is loaded when the memory starts an operation.

Abstract: A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.

Abstract: A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable in a q-bit module address and an (n−q) bit row address in a power-of-two stride fashion. The row address is selected from (n−q) bits of the index address, and the module address for one of the Q accesses is obtained from bitwise exclusive-OR operation on bits obtained from corresponding positions in a plurality of q-bit fields grouped from the index address.

Abstract: In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2 . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory component having a memory core for storing data therein. The memory component comprises a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory component also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.

Abstract: A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.

Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.

Abstract: An apparatus and method for storage of memory packets with a high aggregate bandwidth is disclosed. An odd-even memory bank structure effectively doubles the memory available for packet storage. A packet memory arbitration scheme aligns access of devices reading and writing into packet memory allowing full-rate access to the packet memory.

Abstract: A dual mode memory module includes an interface configured to receive a first memory module, a first control circuit for switching between unbuffered and registered/buffered modes, an interface configured to receive a second memory module, and a second control circuit for switching the operation of the second memory module between unbuffered and registered/buffered modes. The control circuit may include a bus switch and a register/buffer operatively coupled to the bus switch. Enable/disable pins may be included operatively coupled to the first bus switch and the first register/buffer and configured so that only one of the first bus switch and the first register/buffer is active at a time. A system controller for detecting a type of memory module connected to the stackable dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected may be included.