Abstract: A memory subsystem including memory modules having multiple banks. A memory subsystem includes a memory controller and a plurality of memory modules. The plurality of memory modules may be coupled to the memory controller by a memory interconnect having a data path including a plurality of data bits. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The circuit board includes a connector edge for connection to the memory interconnect. Each of the plurality of memory chips may be configured to store data in a plurality of storage locations. Each of the plurality of memory modules may be coupled to a respective mutually exclusive subset of the plurality of data bits.

Abstract: The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.

Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.

Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Abstract: A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.

Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.

Abstract: A network processing device intelligently interleaves packets for read and write access requests in a multibank memory. The system intelligently writes packets into the different memory banks so that the same memory bank is not used for back-to-back packet reads. The last memory bank write is determined for each output queue. This write information is used in combination with look ahead packet read information for a group of packets from the next output queue scheduled to read packets from memory. The scheduler uses all this information to avoid any back-to-back packet read, write, or read/write accesses to the same memory bank. This intelligent packet interleaving scheme preserves memory bus bandwidth normally wasted accessing the same memory banks.

Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.

Abstract: The claimed subject matter facilitates an address mapping of memory access requests.

Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.

Abstract: A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly fields, or four segments of 4-bit addresses, for comparison with a 16-bit top end boundary that has been divided into quarterly fields and a 16-bit bottom end boundary that has been divided into quarterly fields. Consequently, the range match circuit is able to analyze the entire 16-bit address field in parallel and perform simple combinational logic to determine if the incoming address is within the boundaries described by the top edge and bottom edge of the range.

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Abstract: Memory modules in the main memory have a memory device of different storage capacity from one another. BCT (Bank Control Table) has entries for units having the same storage capacity. Each entry stores valid bits each of which indicates whether or not a memory device is allocated to a combination of a relevant unit and a relevant memory module and source addresses to be converted to row addresses of the memory devices. ABPT (Address Bit Position Table) has entries for the memory modules. Each entry of ABPT stores information concerning both the number of bits of row address and the number of bits of column address of a memory device mounted on the relevant memory module. When the main memory is accessed from the processor, number determining portion determines the memory module to be accessed with reference to a line address supplied from the processor and temporally stored in the address register and the contents in the BCT.

Abstract: In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data processor capable of operating at a high memory-accessing speed is provided. Because memory types can often be differentiated based only on partial bits of the address obtained by addition, a partial bit adder and decision logic are used to make this differentiation at high speed. Because the partial addition preferably does not take into account the possible carry from the lower bits, two types of memories are chosen from memories and are both operated in case the carry should be “1” and in case it should be “0.” The result is chosen by a multiplexor and is output. A determination of the entry address of the memory may be similarly carried out by dividing the memory into odd and even entry number banks and utilizing a partial bit adder.

Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM.

Abstract: One embodiment of the invention is a memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising: circuitry for calculating a remainder from a division of the received address by a divisor, wherein the divisor is based on the number of the plurality of banks; circuitry for determining a particular bank of the plurality of banks based on the remainder and at least one bit of the received address; and circuitry for determining the memory location in the particular bank using at least a portion of the received address.

Abstract: A method of indirect addressing involves use of a bank select register and a bank of multiple directly-accessible registers to indirectly access registers of a memory device. Bank select data is written to the bank control register, specifying a bank of registers to be indirectly accessed. Read and/or write operations are then performed, for example, reading data from the specified bank of registers and transferring it to the bank of directly-accessible registers, or writing data to the bank of directly-accessible registers from an external source, and transferring the data to the registers of the specified bank.

Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Abstract: A memory controller is provided, which includes a request input for receiving successive memory access requests and a memory interface configured for coupling to a memory device having a plurality of banks. The memory controller has a bank control circuit, which generates a bank access command on the memory interface for a respective one of the banks in response to each memory access request to that bank. The bank control circuit has a plurality of selectable operating modes, including a Request Count Mode. When in the Request Count Mode, the bank control circuit generates a bank precharge command on the memory interface for the respective bank if none of a predetermined number of subsequent ones of the memory access requests is to that bank.

Abstract: Multi-ported pipelined memory is located on a processor die serving as an addressable on-chip memory for efficiently processing streaming data. The memory sustains multiple wide memory accesses per cycle, clocks synchronously with the rest of the processor, and stores a significant portion of an image. Such memory bypasses the register file directly providing data to the processor's functional units. The memory includes multiple memory banks which permit multiple memory accesses per cycle. The memory banks are connected in pipelined fashion to pipeline registers placed at regular intervals on a global bus. The memory sustains multiple transactions per cycle, at a larger memory density than that of a multi-ported static memory, such as a register file.

Abstract: The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.

Abstract: A method and system for testing a memory module that has at least a first and second memory bank. The first and second memory banks have a plurality of integrated circuit (IC) devices for storing data and the IC devices have a plurality of control lines coupled thereto. A first portion of the plurality of control lines are allocated to the IC devices of the first bank of the module. A second portion of the plurality of control lines are allocated to the IC devices of the second bank of the module. The IC devices of the first and second banks of the module are tested substantially simultaneously using the first and second portions of the plurality of control lines.

Abstract: A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

Abstract: A process/method for controlling a digital data storage unit including a multiplicity of storage media slots for receiving media storage units, a plurality of media storage units loaded in some of the storage media slots, a plurality of data storage drives each having a unique drive address, a loader mechanism for selectively moving a media storage unit between a storage media slot and one of the plurality of data storage drives, and a storage unit controller connected to at least one host computer. One or more of the data storage drives are reserved as spare data storage drives wherein the spare data storage drives are masked from the host computer such the spare data storage drives are not directly accessible by the host computer. The storage unit controller receives and decodes host commands including a source address corresponding to a storage media slot location, and a destination address corresponding to a data storage drive specified by the host computer.

Abstract: A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.

Abstract: A Flash Memory Unit comprises a plurality of memory banks capable of simultaneously programming a plurality of pages into a plurality of data blocks within the respective memory banks. On start up, the Flash Memory System sends a signal to a Host. If the Host fails to respond, the Flash Memory Unit determines that the Host is a standard Host and stores data one page at a time. If the Host responds with a proper signal, the Flash Memory Unit determines that the Host is a high performance Host and stores multiple pages of data simultaneously. The high performance Host is configured to select identical LBA offsets from a plurality of Virtual Logical Blocks of User Data, and send the data defined by these Logical Block Addresses to the Flash Memory Unit for storage. The plurality of Logical Blocks of data are respectively transmitted to a plurality of RAM Data Registers, and simultaneously programmed into their respective memory banks.

Abstract: A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in ac

Abstract: A method and system utilizing data fragments for efficiently importing/exporting a removable storage volume having a number of data files from a first virtual storage system to a second virtual storage system. The method includes writing data fragments to the end of the removable storage volume in the first virtual storage system. In an advantageous embodiment, the data fragments are written to the end of the removable storage volume when the removable storage volume is closed. The data fragments contain information, such as data file headers, that uniquely identifies the data files residing in the removable storage volume. Next, the removable storage volume is transferred to the second virtual storage system. Upon receipt of the removable storage volume, the second virtual storage system updates a tape volume cache in the second virtual storage system utilizing the information contained in the data fragments without having to read each of the data files.

Abstract: A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system.

Abstract: An improved method of operation for a motor vehicle microcontroller uses flash memory (FM) for storing generic data and emulating an EE memory device. The FM is divided into first and second banks, with the first bank being utilized for generic data and the second bank being utilized for EE data, allowing EE data to be updated while the microcontroller accesses stored generic data. The second bank is partitioned into sectors that are individually erasable, and EE data is updated by storing the updated EE data into an unused sector, flagging the old sector to indicate that it contains invalid data, and later erasing the old sector to make it available for future updates of EE data.

Abstract: A module array includes a lead-in transmission line from a driving source. The lead-in transmission line ends with a series impedance between the lead-in transmission line and a star node. The star node has a terminating impedance between it and a termination voltage. At least two branch transmission lines diverge from the star node. Modules connect to the branch transmission lines in a comb topology.

Abstract: In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

Abstract: A memory controller includes an input command decoder circuit for generating an input command, a state machine controller coupled to receive the input command from the input command decoder circuit and generate a state machine input instruction therefrom, a state machine array comprised of a plurality of state machines coupled to receive the input command and state machine input instructions from the state machine controller and to generate state machine output instructions therefrom, and an output command decoder circuit for receiving a state machine output command and generating an output command therefrom for transmission to a memory, associated with the memory controller, comprised of a plurality of memory banks. A first state machine execute a state machine input instruction transmitted, with the input conunand, to all state machines if a memory address contained within the input command corresponds to an address for a corresponding memory bank.

Abstract: A redundant storage system implemented in a web server environment. The system comprises a web server database accessible to multiple web servers. The web server database is comprised of at least a first and a second storage bank. The first storage bank is comprised of at least a first and a second sub-bank with at least a portion of data stored on the first sub-bank also being stored on the second sub-bank. Methods for using the storage system comprise receiving a write access addressed to the first storage bank, and storing data associated with the write access to the second storage bank when the second sub-bank is inoperable. The storage area addressed by the write access is then de-allocated.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a microprocessor and a first cache coupled to the microprocessor. The first cache detects conflicts between multiple requests to access a bank within the first cache.

Abstract: A data transfer memory comprises a plurality of memory devices having the function of transferring data on a system bus or a plurality of memory modules each having the plurality of memory devices. Herein, a memory module buffer in each memory device or memory module and a controller chip located on the system bus include a return clock input/output circuit for inputting or outputting a return clock generated using a clock output from a data processing unit such as a CPU, and an output activation circuit for activating output of data from the memory device in response to a data output enabling signal generated by using the return clock output from the return clock input/output circuit.

Abstract: A parallel memory configured to enable access to a table with aligned and equidistant components constituting a vector of N components. The memory (1) is organized as M memory banks (8). Each memory bank (8) includes an address calculator. The memory (1) also includes a unidirectional network (6) configured to carry out a permutation of the N components of the vector being accessed and to carry out a translation by a specified value t of the components of the vector.

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Abstract: An address look-up device includes a search device and a Discriminant Bits (DB)/Longest Prefix Match (LPM) search device. The search device receives an input key and determines one of at least one memory section of a memory device in which to search for a resultant key having a longest prefix matching the input key. The DB/LPM search device receives the input key and the memory reference, and utilizes a DB pattern and a set of LPM rules to determine and provides a determined key.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.

Abstract: A multipurpose interlaced memory device functions in two different modes, synchronous and asynchronous. The memory uses a circuit for detecting address transitions by acting as a synchronous clock of the system for letting the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of memory cells. The memory device includes a buffer for outputting data. The buffer includes a circuit for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

Abstract: A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.

Abstract: An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.