Abstract: A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple memories corresponding to the multiple processor chips are included. The multiple memories are configured such that one processor chip is associated with one memory. A plurality of fabric chips enabling each of the multiple application processor chips to access any of the multiple memories are included. The data associated with one of the multiple application processor chips is stored across each of the multiple memories. In one embodiment, the application processor chips include a remote direct memory access (RDMA) and striping engine. The RDMA and striping engine is configured to store data in a striped manner across the multiple memories. A method for allowing multiple processors to exchange information through horizontal scaling is also provided.

Abstract: In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data processor capable of operating at a high memory-accessing speed is provided. Because memory types can often be differentiated based only on partial bits of the address obtained by addition, a partial bit adder and decision logic are used to make this differentiation at high speed. Because the partial addition preferably does not take into account the possible carry from the lower bits, two types of memories are chosen from memories and are both operated in case the carry should be “1” and in case it should be “0.” The result is chosen by a multiplexor and is output. A determination of the entry address of the memory may be similarly carried out by dividing the memory into odd and even entry number banks and utilizing a partial bit adder.

Abstract: A distributor and a search controller are added to the memory. A search is performed with an algorithm such as quick search by repeating reading of memory cells, comparing of the reading result, and narrowing down of entries to be compared based on the comparison result. Performing this sequential processing in the memory provides valid data in a bus time plus about half of a cycle time required in repeating reading a conventional memory. Then, the latter half of the cycle time can be used for comparison, as well as generation of the next memory cell address, so that the search can be finished in a bus time multiplied by the number of repetitions of reading the memory cells plus one bus time. As a result, a CAM function can be achieved that allows for more than tens of thousands of entry data items, the number of which is equal to the size of DRAM divided by the number of banks, rather than hundreds or thousands of entry data items as conventional CAM.

Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

Abstract: An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the processor and the modules is connected to a fast AMBA-AHB bus, several advantages are achieved: for one, faster access is possible to each register. For another, the placement of the registers and the routing for the registers is simplified. This in particular allows chip area to be saved, which leads to cost savings in manufacture and enables higher component density. Furthermore, a slow AMBA-APB bus has now become optional.

Abstract: A log-structured block system is provided in which writing log-structured data is done. Subsequently, data mirroring is done. In addition, a data storage system for implementing the log-structured block system is provided.

Abstract: In a system having multiple master devices coupled to a shared resource, methods and structure for a state machine based memory model associated with each bank of memory to provide an arbiter with information for generating optimal sequences of memory commands to enable improved memory subsystem bandwidth utilization. The memory model corresponding to each bank of memory emulates the latencies involved with switching of active rows or pages in the corresponding bank. Signals generated by the memory model are applied to the arbiter to enable the arbiter to efficiently determine the optimal timing for generation of memory access commands corresponding to that bank.

Abstract: Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operation can be successively carried out without latency even though an address region moves from the first semiconductor memory device to the second memory device.

Abstract: Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Abstract: The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.

Abstract: A method and associated apparatus are provided for improving the performance of a high speed data bus, such as a memory bus, using selectively activated receiver and driver pairs. Each receiver and driver pair may be selectively activated to permit data communication on a segment of the high speed data bus coupled to the activated receiver and driver pair. Each receiver and driver pair may also be deactivated, thereby disconnecting at least a respective segment of the high speed data bus, so that communicating system components may be connected in a substantially stubless environment.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: A disk array system of the type that each controller has an independent and dedicated cache. The disk array system can change control of a desired volume between desired controllers without suspending the system. When volumes are taken over between controllers, a switch-source controller de-stages data of a subject volume on the data cache to a storage subject disk to maintain the disk content reflection (coherency). Even if each controller has an independent and dedicated cache, a desired volume can be taken over between desired controllers without suspending the system. Each controller has a configuration manager which stores the controller number of a switch-destination controller to allow automatic volume take-over and automatic control by the original controller.

Abstract: Disclosed is a Rambus DRAM capable of reducing power consumption and layout area by enabling data read/write control signal of accessed memory bank only, in a top memory bank and a bottom memory bank. The disclosed comprises: a top and a bottom memory bank blocks including a plurality of unit memory banks, respectively; and a data read/write control signal generation block for generating a top data write control signal and a top data read control signal to the top memory bank block and a bottom data write control signal and a bottom data read control signal to the bottom memory bank block, thereby controlling the top memory bank block and the bottom memory bank block to separately operate in data read/write operations.

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Abstract: A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.

Abstract: A data processing arrangement (1) comprises a first processor (PROC1) for providing successive sets of input data, a second processor (PROC2) for receiving successive sets of output data and a memory system (2) comprising a plurality of memory circuits (MEM) for storing the input and output data. According to the invention, the data processing arrangement further comprises a master controller (MCP) for setting up memory system by means of control commands (CC) associated with a set of input data and a set of output data. These control commands are received in the memory system by a control unit (MCU). When a data (Di) from the set of input data is provided by the first processor, this control unit selects, on the basis of the control commands, a first memory circuit and generates a write-address (AD_W) in said first memory circuit.

Abstract: The present invention relates to a data processing system comprising a processor (100), at least one data memory (132), at least one program memory (134) and a main bus (110), common to the data and program memories and connecting these memories to the processor, characterized in that at least one of the memories has a rapid-access mode and in that the device also comprises a distribution interface (120) between the main bus (110) and the memories in order to alternately put in communication, by means of the main bus, one from among the data memory and the program memory with the processor, in a so-called active-access mode, and to keep the other memory in a so-called passive-access mode allowing subsequent rapid access.

Abstract: A flash memory includes a data bank having a plurality of banks, a merge bank, and an update data bank. A file system using the flash memory includes a unit storing update data corresponding to a data rewrite command into the update data bank, a unit selecting the latest update data for each block from update data stored in the update data bank when the update data bank becomes full, and a processing unit processing the latest update data. The processing unit includes a unit storing latest update data into a merge bank, a unit selecting data associated with the latest update data from the data bank to store the selected data into the merge bank, and a unit setting the merge bank as a new data bank.

Abstract: Cache memory structures are arranged to further alleviate the continually increasing memory latency or delay problem caused by the ever increasing speed of computer processors. In these memory structures, a plurality of separate and independent memory branches are extended from a common bus that passes from a hierarchical level immediately above the processor. Each memory branch is initiated with a cache memory unit and ascends hierarchically to the main memory. Other intermediate cache memory units may be disposed in the branches between the initial cache memory unit and the main memory thereof. Memory space division may be applied to the intermediate cache memory units or the relative information storage capacities thereof may be sized to alleviate the memory latency or delay problem still further.

Abstract: A high speed bidirectional data rate conversion circuit converts 1× data rate signals from attached devices on port A and port B to 2× data rate signals on bus C and further converts 2× high speed data rate signals on bus C to 1× data rate signals on ports A and B for memory devices attached to ports A and B. The usage of pass gate switches and combination of latches and counters is used to permit proper synchronization of the data signals, and to further generate strobe signals at both system bus and memory bus sides, and to further generate data mask signals for writing to the memory bus side of the circuit. The collection of such switching elements and latches are provided on a single silicon chip which includes of the functions of the invention.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

Abstract: In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

Abstract: The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiving the internal address signal therein and determining whether the corresponding address corresponds to an address for a defective word line of a plurality of normal word lines, and an address counter for generating refresh address signals for sequentially refreshing the plurality of normal word lines and redundant word lines. The redundant judgment circuit is deactivated upon refresh.

Abstract: A method of outputting data from a FIFO incorporated in an integrated circuit generally determines whether input data is valid during a first clock cycle. The method then outputs data from a plurality of output barrel slots during a second clock cycle. Data is then shifted from predetermined upper barrel slots to predetermined output barrel slots during second cycle based upon a barrel count. Finally, data is shifted into the FIFO during said second cycle based upon the barrel count. A new barrel count of valid data in the FIFO can then be determined. Circuitry for implementing the embodiments of the invention is also disclosed.

Abstract: A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM with a plurality of banks. The semiconductor device includes a plurality of memory banks BANK0 to BANK127, each having a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM includes a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM has a plurality of sub lines DATA0 to DATA3 and the tag memory TAGMEM has a plurality of valid bits V0 to V3 and a plurality of dirty bits D0 to D3.

Abstract: The present invention relates to a memory system, or more particularly to a conflict-free memory system, which can reduce access time to the memory system by supporting simultaneous access to pq units of various data elements of types of 4 directional blocks (pq) and eight directional lines of a constant interval at a location of data within M×N array in a SIMD processor having pq units of PE's (Processing Elements). Accordingly, the present invention is an improvement over the previous memory systems, from the perspective of restriction of subarrary types, constant intervals, and the size of a data array, hardware cost, speed and complexity. Further, it provides a method of address calculation and data routing using said improved conflict-free memory system.

Abstract: A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.

Abstract: A memory manager for use in connection with a memory comprises a memory access request receiver module, an address translation module and a memory access operation control module. The memory access request receiver module is configured to receive an access request requesting an access operation in connection with the memory, the access request including an address.

Abstract: A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Abstract: A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

Abstract: An apparatus and method are provided for transmitting data using synchronous dynamic random access memory (SDRAM). In example, the method includes writes data using a first set of SDRAM banks. Data is written using a second set of SDRAM banks, wherein the first set of SDRAM banks and the second set of SDRAM banks write interleaved. Data is read using a third set of SDRAM banks. Data is read using a fourth set of SDRAM banks, wherein the fourth set of SDRAM banks and the third set of SDRAM banks read interleaved.

Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.

Abstract: A nonvolatile semiconductor memory device capable of controlling a single memory chip similar to a plurality of memory chips. The memory chip has a plurality of Electrically Erasable Programmable Read Only Memory circuits, each of which includes a control circuit for carrying out sequential writing control and which EEPROM circuits share a data bus. Each of the EEPROM circuits has a Chip Enable terminal CE and a Ready/Busy terminal RIB, so that data writing processes can be simultaneously carried out in the respective EEPROM circuits in parallel. The activity and inactivity of each of the EEPROM circuits may also be controlled by a logical combination of a master chip enable signal and a chip enable signal of each of the individual EEPROM circuits.

Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.

Abstract: A method and system are disclosed for managing an allocation of a portion of a memory associated with a central processing unit system that can be selectively coupled to a bus of the central processing unit system. In accordance with exemplary embodiments of the present invention, a first portion of the memory is allocated for a first range of addresses. The allocated first portion of the memory is selectively coupled to the bus of the central processing unit system. The selectively coupled first portion of the memory is decoupled from the bus of the central processing unit system. The decoupled first portion of the memory is reallocated for a second range of addresses.

Abstract: A semiconductor memory card stores a plurality of audio objects (AOBs) that compose a plurality of tracks and playlist information showing a reproduction order for the tracks. The semiconductor memory card also stores, as resume information (PLMG_RSM_PL), (1) a Playlist_Number showing which playlist information was used the last time playback was performed for the semiconductor memory card, (2) a Track_Number showing the last track to be played back, and (3) a Playback_Time showing a position at which where playback was stopped as a time expressed in relation to the start of the track.

Abstract: In a microcontroller (100) the command decoder (15) has access to at least one memory (14). The command decoder may thus be adapted to decode at least one conditional command, while the result of decoding the conditional command is dependent on the contents of said memory (14). The microcontroller according to the invention thus provides the possibility of considerably reducing the programming effort so that both the system performance and the code density can be significantly increased with a small additional number of hardware components.

Abstract: A data distribution system suitable for use in a content addressable memory (CAM) search engine have a number of CAM units. A set of bank multiplexers each includes a set of multiplexing constructs that are controllable via respective bank control buses. Input data for storage in the CAM units as file data or for searching against pre-stored file data are provided to the bank multiplexers and the bank control buses direct the multiplexing constructs to selectively pass sub-portions of the input data onward to the CAM units thus distributing some or all of the input data to the CAM units, with the input data configurably ordered as desired, configurably duplicated as desired, or both. Optionally, a configuration register can hold multiple sets of programming data for loading onto the bank control buses to direct the multiplexing constructs, thus facilitating different distributions of the input data to the CAM units.

Abstract: Methods and systems consistent with the present invention allocate memory for program data during fast Fourier transform computation in a way that is favorable for a given access pattern for the program data, and for the memory architecture of a given data processing system. As a result, the overhead associated with accessing the program data is reduced compared to typical memory allocation performed during fast Fourier transform computation. Thus, a fast Fourier transform computing program that manipulates the program data typically runs faster and produces results more quickly.

Abstract: A method and apparatus for load distribution across memory banks with constrained access is accomplished using a bank balancer that ensures that data to be buffered is evenly distributed throughout the various banks of the memory structure. The bank balancer maintains bank depth information relating to each of the banks. The bank balancer receives dequeue and enqueue information, where the dequeue information specifies read operations that will remove data from the various banks, and the enqueue information indicates that there is data to be written to the memory banks. The dequeue information constrains which banks may be utilized to enqueue received data. In order to determine to which banks to enqueue data, the bank balancer sorts the banks by their depth. The bank balancer then eliminates those banks which cannot be used for enqueue operations due to either the dequeue operations or other enqueue operations that have already been determined.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A memory exhaustion condition is handled in a data processing system having first and second regions of physical memory. The memory exhaustion condition is detected while the second region is mirroring at least part of the first region. In response to the memory exhaustion condition, memory mirroring is at least partially deactivated and at least part of the second region is utilized to augment the first region, such that the memory exhaustion condition is eliminated. In an illustrative embodiment, the data processing system compresses real memory into the first region of physical memory, and the memory exhaustion condition arises when the first region lacks sufficient available capacity to accommodate current requirements for real memory. The memory exhaustion condition is eliminated by compressing at least part of the real memory into the second region.

Abstract: The present invention increases efficiency of a binary translation process by correlating selected foreign code to previously translated binary host code. This approach eliminates repetitive translation of foreign code when the foreign code is executed on a host computer system. During the translation process, a database of translated foreign code is populated and thereafter a software layer checks for correspondence between the foreign code and binary code stored in the database. If the database contains corresponding code, that code is transferred to system memory for execution and there is no need to retranslate the foreign code. Minimizing the time spent translating the foreign code results in improved execution speed on the host computer system. The software layer creates an index into the database by hashing the foreign code or by using the storage location of the foreign code. By way of example, the sector of a disk drive where the foreign code is stored determines the index into the database.

Abstract: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

Abstract: A data storage system utilizes a plurality of memory systems, at least one processor, and a mapping system. Each of the memory systems has memory and a memory controller for storing and retrieving data. The processor transmits requests for writing data values. These requests include bus addresses. The mapping system maps the bus addresses into memory addresses. The mapping system maps consecutive bus addresses such that the memory addresses mapped from the consecutive bus addresses are interleaved across a plurality of the memory systems. In response to the foregoing requests from the processor, the mapping system identifies checksum system identifiers that identify locations where checksum values to be updated based on the aforementioned data values are stored.

Abstract: A method of accessing a plurality of memories and a plurality of input/output modules includes providing at least one map table, including a plurality of entries. Each entry includes an entry type identifier and a plurality of entry items. A first logical address including a plurality of address bits is received. An entry in the at least one map table is identified based on a first set of the address bits. A type of the identified entry is determined based on the entry type identifier of the identified entry. An entry item in the identified entry is identified based on a second set of the address bits if the entry type identifier indicates an input/output type entry. An entry item in the identified entry is identified based on a third set of the address bits if the entry type identifier indicates a memory type entry.