In Block-addressed Memory (epo) Patents (Class 711/E12.007)
  • Patent number: 8924625
    Abstract: A method includes implementing, with a memory of a computing device, a memory controller of the memory of the computing device, a storage device coupled to the computing device and/or an external device coupled to the computing device, a scheme for detecting an overlap between a first address range and a second address range. The first address range includes a first starting address and a first ending address, and the second address range includes a second starting address and a second ending address. The method also includes reducing a number of comparators utilized in the address range overlap detection through solely determining whether the first starting address is within the second address range or the second starting address is within the first address range.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 30, 2014
    Assignee: NVIDIA Corporation
    Inventors: Shankara Rao Thejaswi Nanditale, Anand G Shirahatti, Rahul Jain
  • Patent number: 8868852
    Abstract: A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 21, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Chi Kong Lee, Siu-Hung Fred Au, Jungil Park, Hyunsuk Shin
  • Patent number: 8812815
    Abstract: The storage control device of this invention allocates the physical storage area in RAID groups to virtual volumes in units of chunks including multiple pages. To the virtual volume 5, in accordance with write accesses from the host 20, the physical storage area in the pool is allocated. A RAID group 6 in the pool includes multiple chunks 7. Each chunk 7 includes multiple pages 8. To the virtual volume 5, the physical storage area is allocated in units of chunks 7. From the allocated chunks 7, the pages 8 required for writing write data are used.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: August 19, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Koji Iwamitsu, Yoshinori Ohira, Katsuhiro Uchiumi
  • Patent number: 8782332
    Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 15, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chung-Ching Chen, Hsian-Feng Liu, Yu-Lin Chen
  • Patent number: 8751735
    Abstract: A system including a controller in communication with a memory. The memory includes memory cells arranged in memory blocks. Each memory cell is capable of storing a plurality of bits. Each memory block defines a plurality of pages. A page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block. The controller is configured to write data to selected pages in one or more memory blocks. The system includes circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data. The predetermined number is based on one or more of a number of pages in each memory block and a number of bits in the plurality of bits.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 10, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Qun Zhao, Xinhai Kang
  • Patent number: 8751749
    Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian Habermann, Martin Recktenwald, Hans-Werner Tast, Ralf Winkelmann
  • Patent number: 8732385
    Abstract: Disclosed herein is a non-volatile memory, including: a memory cell array to be accessed with data including a data portion and a specific field as a unit of access; a buffer configured to hold the access-unit data read from the memory cell array or the access-unit data to be written to the memory cell array; and a control circuit configured to control access to the memory cell array in accordance with a specified address, a command, and data in the specific field of the access-unit data held in the buffer.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: May 20, 2014
    Assignee: Sony Corporation
    Inventor: Takeshi Ishimoto
  • Patent number: 8732395
    Abstract: In an information recording medium in which storage capacity per recording layer has increased so much that the size of an SBM varies with those of spare areas, there is mutual dependence between a DDS and an SBM and it is difficult to retrieve disc management information as intended. In an information recording medium according to the present invention, if the largest space is allocated to an user data area, the number of blocks to store a space bitmap is Ni (where Ni?2). But if the smallest space is allocated to the user data area, the number of blocks to use is smaller than Ni.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 20, 2014
    Assignee: Panasonic Corporation
    Inventors: Hisae Kato, Yoshihisa Takahashi, Motoshi Ito
  • Publication number: 20140089559
    Abstract: Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventors: Qiong Cai, Nevin Hyuseinova, Serkan Ozdemir, Ferad Zyulkyarov, Marios Nicolaides, Blas Cuesta
  • Publication number: 20140082254
    Abstract: For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin John ASH, Michael Thomas BENHASE, Lokesh Mohan GUPTA, Kenneth Wayne TODD
  • Patent number: 8677065
    Abstract: Aspects of the innovations herein are consistent with a storage system for storing variable sized objects. The storage system may be a transaction-based system that uses variable sized objects to store data. The storage system may be implemented using arrays disks that are arranged in ranks. Each rank may include multiple stripes. Each stripe may be read and written as a convenient unit for maximum performance. A rank manager may be provided to dynamically configure the ranks to adjust for failed and added disks by selectively shortening and lengthening the stripes. The storage system may include a stripe space table that contains entries describing the amount of space used in each stripe. An object map may provide entries for each object in the storage system describing the location (e.g., rank, stripe and offset values), the length and version of the object.
    Type: Grant
    Filed: April 3, 2011
    Date of Patent: March 18, 2014
    Inventor: Robert E. Cousins
  • Publication number: 20140068140
    Abstract: The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventor: Kimmo J. Mylly
  • Publication number: 20140068139
    Abstract: A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Patent number: 8656100
    Abstract: This invention is a system and method for managing provisioning of resources for one or more data storage networks using a new architecture.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: February 18, 2014
    Assignee: EMC Corporation
    Inventors: Bradford B. Glade, David W. Harvey, John Kemeny, Matthew D. Waxman
  • Patent number: 8645609
    Abstract: A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Kung-Ling Ko, Tony Sonthe Nguyen, Joseph Juh-En Cheng, Tuan Van Quach
  • Publication number: 20140006682
    Abstract: A method includes implementing, with a memory of a computing device, a memory controller of the memory of the computing device, a storage device coupled to the computing device and/or an external device coupled to the computing device, a scheme for detecting an overlap between a first address range and a second address range. The first address range includes a first starting address and a first ending address, and the second address range includes a second starting address and a second ending address. The method also includes reducing a number of comparators utilized in the address range overlap detection through solely determining whether the first starting address is within the second address range or the second starting address is within the first address range.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: NVIDIA Corporation
    Inventors: SHANKARA RAO THEJASWI NANDITALE, Anand G Shirahatti, Rahul Jain
  • Publication number: 20140006684
    Abstract: A multi-level storage apparatus includes a first-level storage area to store first information, a second-level storage area to store second information, and a selectively enabled third-level storage area to store information based on different operational states. The third-level storage area stores the first information from the first-level storage area when the third-level storage area is to change from a first state to a second state. The first information in third-level storage area is transferred to the first-level storage area when the third-level storage area is to change from the second state to the first state. The first information is to include page miss information.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventor: Siva RAMAKRISHNAN
  • Publication number: 20130339569
    Abstract: Storage system(s) for providing storing data in physical storage in a recurring manner, method(s) of operating thereof, and corresponding computer program product(s). For example, a possible method can include for each recurrence: generating a snapshot of at least one logical volume; destaging all data corresponding to the snapshot which was accommodated in the cache memory prior to a time of generating the snapshot and which was dirty at the time of generating said snapshot, thus giving rise to destaged data group; and after the destaged data group has been successfully destaged, registering an indication that the snapshot is associated with an order preservation consistency condition for the at least one logical volume, thus giving rise to a consistency snapshot.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: Infinidat Ltd.
    Inventors: Yechiel YOCHAI, Michael DORFMAN, Efri ZEIDNER
  • Patent number: 8612667
    Abstract: A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 17, 2013
    Assignees: Silicon Motion Inc., Silicon Motion Inc.
    Inventors: Ching-Hui Lin, Kuo-Liang Yeh, Ken-Fu Hsu
  • Patent number: 8560759
    Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: October 15, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Curtis E. Stevens, Virgil V. Wilkins
  • Patent number: 8549214
    Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise a flash controller configured to control a multi-level memory cell (MLC) flash memory, wherein the MLC flash memory includes a plurality of memory blocks, wherein each memory block includes a plurality of memory cells defining a plurality of pages, wherein each memory cell spans a group of the pages in one of the memory blocks, and wherein the flash controller comprises circuitry configured to receive data to be written to the MLC flash memory, select only one page, from each group of the pages, in one or to more of the memory blocks, and write the data only to the selected pages.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 1, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Qun Zhao, Xinhai Kang
  • Publication number: 20130246686
    Abstract: A higher-level system of a nonvolatile semiconductor storage device (hereinafter, semiconductor device) displays a GUI (Graphical User Interface), which receives a parameter group (one or more parameters) for controlling the processing of the semiconductor device. The higher-level system stores at least one of the parameters of the parameter group inputted to the GUI, and sends a command comprising the parameter group to the semiconductor device. The semiconductor device stores at least one of the parameters of the parameter group included in this command. The higher-level system and the semiconductor device each execute processing in accordance with the stored parameter. The semiconductor device sends, to the higher-level system, information of a log related to the processing executed in accordance with the stored parameter. The higher-level system displays feedback information on the basis of multiple times of logs. A user can change a desired parameter on the basis of this feedback information.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Inventors: Yoshiyuki Noborikawa, Yoshihiro Oikawa
  • Patent number: 8521987
    Abstract: A storage control device includes a controller managing a plurality of first storage areas provided with a plurality of storage devices and a plurality of second storage areas in a particular first storage area of the plurality of first storage areas. Each of the plurality of first storage areas having a first fixed area size and each of the second plurality of storage areas having a second fixed area size which is smaller than the first fixed area size. The controller is adapted to allocate the particular first storage area to the virtual volume so that data of the write command are written to a particular second storage area of the plurality of second storage areas when a write command to a virtual volume of a plurality of virtual volumes is received.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: August 27, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Iwamitsu, Yoshinori Ohira, Katsuhiro Uchiumi
  • Publication number: 20130145074
    Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: ALTERA CORPORATION
    Inventor: James L. Ball
  • Patent number: 8447935
    Abstract: A computer-implemented method, apparatus, and virtual machine for facilitating the communication between VMs. The method of facilitating the communication between a first VM and a second VM includes: allocating a shared memory segment from within the memory of the physical machine; mapping the requested memory space addresses to the shared memory segments in response to the memory space requests from the VMs; and providing the requested memory space addresses. A method of communication from a first VM to a second VM includes: requesting a memory space in response to a notification that a shared memory segment has been allocated; obtaining the requested memory space address, which has been mapped to the allocated shared memory segment; and accessing communication data in the shared memory segment according to the address. The apparatus and virtual machine executes the steps of the methods.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Zhi Guo Gao, Li Li, Rui Xiong Tian, Qi Ming Tian
  • Patent number: 8447922
    Abstract: A memory controller, a nonvolatile storage device, an access device, and a nonvolatile storage system enable the storage architecture to be changed flexibly for intended use that can be changed variously. A nonvolatile storage system (100) sets a temporary area (23) and a normal access area of a nonvolatile memory (22) based on a use condition designated by a use condition designation unit (11) of an access device (1). This structure enables the nonvolatile storage system (100) to change the temporary area (23) and the normal access area (24) to be prepared in the nonvolatile memory (22) by changing the use condition in accordance with intended use. In other words, the nonvolatile storage system (100) enables the storage architecture to be changed flexibly for intended use that can be changed variously.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Takashi Ogasawara
  • Publication number: 20130120925
    Abstract: Example embodiments include a memory module having a first volatile memory, a second volatile memory, a nonvolatile memory, and a controller configured to control an operation of the second volatile memory, and an operation of the nonvolatile memory. When first write data received from an external controller are written to the first volatile memory in a write operation, the controller receives and writes the first write data to the second volatile memory. The controller is configured to perform backup and restore operations using a buffer, the nonvolatile memory, the first volatile memory, and/or the second volatile memory. Example embodiments include a memory module having a first nonvolatile memory, a second nonvolatile memory, and a third nonvolatile memory, with corresponding backup and restore features. Example embodiments also include methods for processing the data and operating the various components of the memory system.
    Type: Application
    Filed: September 14, 2012
    Publication date: May 16, 2013
    Inventor: Young-Jin Park
  • Publication number: 20130103893
    Abstract: A memory system comprises a storage device and a host. The host classifies pages stored in the storage device into a plurality of data groups according to properties of the pages, and transmits setup information regarding the classified data groups to the storage device.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 25, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Samsung Electronics Co., Ltd.
  • Publication number: 20130103884
    Abstract: A file system including a first memory unit which is non-volatile and has a plurality of blocks, a control unit configured to select one of the plurality of blocks of the first memory unit, determine whether the selected block is a valid block, control a data write with respect to the selected block if the selected block is a valid block, divide the plurality of blocks into valid blocks and bad blocks by checking the plurality of blocks of the first memory unit, generate an address table by mapping the valid blocks and the bad blocks to addresses and control a loading of the address table generated, and a second memory unit which is volatile and stores the address table for the plurality of blocks of the first memory unit.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 25, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Patent number: 8412882
    Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 2, 2013
    Assignee: Microsoft Corporation
    Inventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
  • Patent number: 8402230
    Abstract: Embodiments include a method comprising detecting addition of a new nonvolatile machine-readable medium to a data storage pool of nonvolatile machine-readable media. The method includes preventing from being performed a first operation of a file system that requires a first parameter that identifies a logical indication of a location within the nonvolatile machine-readable media for the file system, until logical indications of locations within the new nonvolatile machine-readable medium for the file system have been stored in the data storage pool. The method includes allowing to be performed, prior to logical indications of locations within the new nonvolatile machine-readable medium being stored in the data storage pool, a second operation of the file system that does not require a second parameter that identifies a logical indication of a location within the nonvolatile machine-readable media, wherein the second operation causes data to be written into the new nonvolatile machine-readable medium.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: David K. Bradford, David J. Craft, Manoj N. Kumar, Grover H. Neuman, Frank L. Nichols, III, Andrew N. Solomon
  • Patent number: 8392687
    Abstract: The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, William E. Benson
  • Publication number: 20130054869
    Abstract: Example methods, apparatus, and articles of manufacture to access data are disclosed. A disclosed example method involves generating a key-value association table in a non-volatile memory to store physical addresses of a data cache storing data previously retrieved from a data structure. The example method also involves storing recovery metadata in the non-volatile memory. The recovery metadata includes a first address of the key-value association table in the non-volatile memory. In addition, following a re-boot process, the locations of the key-value association table and the data cache are retrieved using the recovery metadata without needing to access the data structure to re-generate the key-value association table and the data cache.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Niraj Tolia, Nathan Lorenzo Binkert, Jichuan Chang
  • Publication number: 20130042047
    Abstract: In memory system in which the processing unit (30) performs input/output of data in a plurality of memory circuits (10-0-10-3) through a memory bus (20-0), a memory interface circuit (14) is provided. The memory interface device (14) collects specification information of the plurality of memory circuits (10-0˜10-3), creates and stores a common specification information and is connected to the control bus (22-0) of the processing unit (30).
    Type: Application
    Filed: October 19, 2012
    Publication date: February 14, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Publication number: 20130031296
    Abstract: A method and apparatus for managing address map information are disclosed. In one embodiment, an apparatus may comprise a processor configured to store address map changes to a first data storage medium, save the address map changes to a nonvolatile data storage medium when an abnormal power state is detected, and when the power state is no longer abnormal retrieve the last saved address map information and address map changes and update the address map information using the address map changes. The apparatus may be configured to retrieve the instructions for the processor operation over a network connection.
    Type: Application
    Filed: April 27, 2012
    Publication date: January 31, 2013
    Applicant: Seagate Technology LLC
    Inventor: Se Wook Na
  • Publication number: 20130013847
    Abstract: Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Inventors: Roy E. Scheuerlein, Randhir Thakur, Christopher Moore
  • Publication number: 20130007340
    Abstract: A solid state drive (SSD) including a storage that includes a plurality of flash memories configured to be independently drivable and a controller to receive an input/output (I/O) request from a host, to split the I/O request into a plurality of sub-requests each having a size configured to be capable of being processed independently by each flash memory, and to process the I/O request based on the sub-requests.
    Type: Application
    Filed: May 10, 2012
    Publication date: January 3, 2013
    Inventors: Jin-kyu KIM, Hyung-gyu Lee
  • Publication number: 20120331204
    Abstract: The present disclosure relates to the drift management for a memory device. In at least one embodiment, the memory device of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a memory controller that is capable of implementing drift management to control drift. Other embodiments are described and claimed.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Inventors: Elijah V. Karpov, Gianpaolo Spadini
  • Publication number: 20120317332
    Abstract: Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 13, 2012
    Inventors: Dong-ok Kwak, Sang-sub Song, Sang-ho An, Joon-young Oh, Jeong-sik Yoo
  • Publication number: 20120311227
    Abstract: The information storage system of an aspect of the present invention includes a first differential data storage area which stores differential data of a higher volume from a first point of time to a second point of time, a lower snapshot manager which provides a lower snapshot at the second point of time of the higher volume, and a second differential data storage area which stores differential data of the higher volume after the second point of time. The higher snapshot manager acquires a plurality of generations of higher snapshots from the lower snapshot and the data in the first differential data storage area and acquires a plurality of generations of higher snapshots from the data of the higher volume and the data in the second differential data storage area.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicant: HITACHI, LTD.
    Inventors: Tomoya Anzai, Takahiro Nakano
  • Publication number: 20120311228
    Abstract: Method and apparatus for performing wear-leveling using passive variable resistive memory (PVRM) based write counters are provided. In one example, a method for performing wear-leveling using passive PVRM based write counters is disclosed. The method includes associating a logical address of a memory array with a physical address of the memory array via at least one mapping table. Additionally, the method includes, in response to writing to the physical address of the memory array, incrementally updating at least one PVRM based write counter associated with the physical address of the memory array. The at least one PVRM based write counter may be incrementally updated by varying an amount of resistance stored in the at least one PVRM based write counter.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 6, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Lisa Hsu, Bradford M. Beckmann
  • Publication number: 20120311248
    Abstract: A system that includes a memory, a cache, a purge mechanism, and a memory interface mechanism. The memory includes a failing memory element at a failing memory location. The cache is configured for storing corrected contents of the failing memory element in a locked state, with the corrected contents stored in a first cache line. The purge mechanism is configured for selecting and removing cache lines that are not in the locked state from the cache to make room for new cache allocations. The memory interface mechanism is configured for receiving a request to access the failing memory location, determining that corrected contents of the failing memory location are stored in first cache line in the cache, and accessing the first cache line in the cache.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Benjiman L. Goodman
  • Patent number: 8327068
    Abstract: In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: December 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Tomoaki Izumi, Tetsushi Kasahara, Kazuaki Tamura, Kiminori Matsuno, Manabu Inoue, Masayuki Toyama, Kunihiro Maki
  • Patent number: 8307171
    Abstract: A plurality of CPU cores each have control rights for logical storage areas of one or more types among logical storage areas of a plurality of types. As a source for an area to be assigned to the logical storage areas, a physical storage area which is common to the logical storage areas of the plurality of types is managed. In the case of a data access to a logical storage area corresponding to the control rights of the CPU core, the respective CPU core assigns an area required to store the data from the common physical storage area.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: November 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Junji Ogawa, Yoichi Mizuno, Yoshinori Ohira, Kenta Shiga, Yusuke Nonaka
  • Patent number: 8296496
    Abstract: One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: October 23, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey Clifford Mogul, Eduardo Argollo de Oliveira Dias, Jr., Paolo Faraboschi, Mehul A. Shah
  • Publication number: 20120254499
    Abstract: Provided are a program, a control method, and a control device by which an activation time can be shortened. In a computer system which is equipped with a Memory Management Unit (MMU), with respect to a table of the MMU, page table entries are rewritten so that page faults occur at each page necessary for operation of software. At the time of activating, stored memory images are read page by page for the page faults which occurred in the RAM to be accessed. By reading as described above, reading of unnecessary pages is not performed, and thus, the activation time can be shortened. The present invention can be applied to a personal computer and an electronic device provided with an embedded computer.
    Type: Application
    Filed: March 5, 2010
    Publication date: October 4, 2012
    Applicant: UBIQUITOUS CORPORATION
    Inventors: Kenichi Hashimoto, Tomohiro Masubuchi
  • Publication number: 20120254498
    Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. HATFIELD, Wenjeng KO, Lei LIU
  • Publication number: 20120254527
    Abstract: Embodiments of the present invention provide an approach for dynamic random access memory (DRAM)/SSD-based memory to improve memory usage. Specifically, embodiments of the present invention provide a field programmable gate array (FPGA) (SSD controller) that comprises a PCI-express interface for receiving and converting serial data to 64 bit data; a data/bit converter coupled to the interface for converting the 64 bit data to 128 bit data; and a memory controller coupled to the data converter for receiving and storing the 128 bit data in a set of DRAM units coupled to the memory controller.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventor: Byungcheol Cho
  • Patent number: 8275968
    Abstract: A computing device executing a file system maintains a search tree that includes extents for managing first regions of unallocated storage space and bitmaps for managing second regions of unallocated storage space. For each region of unallocated storage space, the file system determines whether to manage that region using an extent or a bitmap based on one or more space management criteria.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Red Hat, Inc.
    Inventor: Josef Michael Bacik
  • Patent number: 8219746
    Abstract: A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventor: Robert B. Tremaine