Abstract: A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, and each of the plurality of memory bits is associated with a spare memory cell.

Abstract: A system comprising a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including initializing a block family associated with the memory device and measuring an opening temperature of the memory device at initialization of the block family. Responsive to programming a page residing on the memory device, the operations further include associating the page with the block family. The operations further include determining a temperature metric value by integrating, over time, an absolute temperature difference between the opening temperature and an immediate temperature of the memory device. The operations further include closing the block family in response to the temperature metric value being greater than or equal to a specified threshold temperature value.

Abstract: The present disclosure provides a high-performance data lake system and a data storage method. The data storage method includes the following steps: S1: converting a file into a file stream; S2: converting the file stream into an array in which multiple subarrays are nested; and S3: converting the array into a resilient distributed dataset (RDD), and storing the RDD to a storage layer of a data lake. The present disclosure provides a nested field structure, which lays the foundation for parallel processing in reading, and effectively improves read performance. Furthermore, the present disclosure flexibly generates a number of nested subarrays according to hardware cores, such that the data lake achieves better extension performance, and can keep optimal writing efficiency for different users.

Abstract: One example method includes receiving a write request that includes a data structure version to be written, wherein the data structure version is associated with a unique identifier, storing the data structure version in association with the unique identifier, receiving a read request for a most recent version of the data structure and, when the stored data structure version is not the most recent version of the data structure, examining respective unique identifiers of each of a group of other stored data structure versions to determine which stored data structure version is the most recent. Finally, the example method includes returning the most recent data structure version, notwithstanding that one or more other data structure versions existed at the time that the read request was received.

Abstract: A system includes a zoned memory device allocating a zone storing a block belonging to a key-value set, and a processing device, operatively coupled with the zoned memory device, to perform operations including obtaining zone status information associated with the zone, identifying that the zone is a non-filled zone in view of the zone status information, and recovering the non-filled zone to obtain a recovered zone.

Abstract: A memory cell includes a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer is maintained in an amorphous state during a program operation.

Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

Abstract: One example method includes receiving a write request that includes a data structure version to be written, wherein the data structure version is associated with a unique identifier, storing the data structure version in association with the unique identifier, receiving a read request for a most recent version of the data structure and, when the stored data structure version is not the most recent version of the data structure, examining respective unique identifiers of each of a group of other stored data structure versions to determine which stored data structure version is the most recent. Finally, the example method includes returning the most recent data structure version, notwithstanding that one or more other data structure versions existed at the time that the read request was received.

Abstract: In an information-processing device a controller executes a storage process to store a command program in a memory. The command program supports the target device and outputs commands to the target device. In a case where the memory does not store the command program, an OS executes a plug and play process for a target device triggered by connection of the target device to the communication interface, and records in the memory unspecified device information indicating that the target device is unknown. In a case where the memory stores the unspecified device information, the OS does not complete a setup process even if the memory stores the command program. The controller executes, after executing the storage process, a deletion process to delete the unspecified device information from the memory so that the OS can complete the setup process.

Abstract: Inputs to a system under test (SUT) are modeled as a collection of attribute-value pairs. A set of testcases is executed using an initial set of test vectors that provides complete n-wise coverage of the attribute-value pairs. For each execution of the testcases, for each attribute-value pair, a non-binary success rate (SAV) is computed based on the binary execution results. The method further includes outputting, to a user, in response to the success rate SAV of the attribute-value pair being below a predetermined threshold, an identification of one or more testcases that use the attribute-value pair, wherein the one or more testcases are to be used for diagnosing a soft failure associated with the SUT.

Abstract: A method includes implementing, with a memory of a computing device, a memory controller of the memory of the computing device, a storage device coupled to the computing device and/or an external device coupled to the computing device, a scheme for detecting an overlap between a first address range and a second address range. The first address range includes a first starting address and a first ending address, and the second address range includes a second starting address and a second ending address. The method also includes reducing a number of comparators utilized in the address range overlap detection through solely determining whether the first starting address is within the second address range or the second starting address is within the first address range.

Abstract: A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.

Abstract: The storage control device of this invention allocates the physical storage area in RAID groups to virtual volumes in units of chunks including multiple pages. To the virtual volume 5, in accordance with write accesses from the host 20, the physical storage area in the pool is allocated. A RAID group 6 in the pool includes multiple chunks 7. Each chunk 7 includes multiple pages 8. To the virtual volume 5, the physical storage area is allocated in units of chunks 7. From the allocated chunks 7, the pages 8 required for writing write data are used.

Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

Abstract: Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.

Abstract: A system including a controller in communication with a memory. The memory includes memory cells arranged in memory blocks. Each memory cell is capable of storing a plurality of bits. Each memory block defines a plurality of pages. A page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block. The controller is configured to write data to selected pages in one or more memory blocks. The system includes circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data. The predetermined number is based on one or more of a number of pages in each memory block and a number of bits in the plurality of bits.

Abstract: Disclosed herein is a non-volatile memory, including: a memory cell array to be accessed with data including a data portion and a specific field as a unit of access; a buffer configured to hold the access-unit data read from the memory cell array or the access-unit data to be written to the memory cell array; and a control circuit configured to control access to the memory cell array in accordance with a specified address, a command, and data in the specific field of the access-unit data held in the buffer.

Abstract: In an information recording medium in which storage capacity per recording layer has increased so much that the size of an SBM varies with those of spare areas, there is mutual dependence between a DDS and an SBM and it is difficult to retrieve disc management information as intended. In an information recording medium according to the present invention, if the largest space is allocated to an user data area, the number of blocks to store a space bitmap is Ni (where Ni?2). But if the smallest space is allocated to the user data area, the number of blocks to use is smaller than Ni.

Abstract: Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.

Abstract: For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.

Abstract: Aspects of the innovations herein are consistent with a storage system for storing variable sized objects. The storage system may be a transaction-based system that uses variable sized objects to store data. The storage system may be implemented using arrays disks that are arranged in ranks. Each rank may include multiple stripes. Each stripe may be read and written as a convenient unit for maximum performance. A rank manager may be provided to dynamically configure the ranks to adjust for failed and added disks by selectively shortening and lengthening the stripes. The storage system may include a stripe space table that contains entries describing the amount of space used in each stripe. An object map may provide entries for each object in the storage system describing the location (e.g., rank, stripe and offset values), the length and version of the object.

Abstract: A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read.

Abstract: The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.

Abstract: This invention is a system and method for managing provisioning of resources for one or more data storage networks using a new architecture.

Abstract: A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.

Abstract: A multi-level storage apparatus includes a first-level storage area to store first information, a second-level storage area to store second information, and a selectively enabled third-level storage area to store information based on different operational states. The third-level storage area stores the first information from the first-level storage area when the third-level storage area is to change from a first state to a second state. The first information in third-level storage area is transferred to the first-level storage area when the third-level storage area is to change from the second state to the first state. The first information is to include page miss information.

Abstract: A method includes implementing, with a memory of a computing device, a memory controller of the memory of the computing device, a storage device coupled to the computing device and/or an external device coupled to the computing device, a scheme for detecting an overlap between a first address range and a second address range. The first address range includes a first starting address and a first ending address, and the second address range includes a second starting address and a second ending address. The method also includes reducing a number of comparators utilized in the address range overlap detection through solely determining whether the first starting address is within the second address range or the second starting address is within the first address range.

Abstract: Storage system(s) for providing storing data in physical storage in a recurring manner, method(s) of operating thereof, and corresponding computer program product(s). For example, a possible method can include for each recurrence: generating a snapshot of at least one logical volume; destaging all data corresponding to the snapshot which was accommodated in the cache memory prior to a time of generating the snapshot and which was dirty at the time of generating said snapshot, thus giving rise to destaged data group; and after the destaged data group has been successfully destaged, registering an indication that the snapshot is associated with an order preservation consistency condition for the at least one logical volume, thus giving rise to a consistency snapshot.

Abstract: A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.

Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise a flash controller configured to control a multi-level memory cell (MLC) flash memory, wherein the MLC flash memory includes a plurality of memory blocks, wherein each memory block includes a plurality of memory cells defining a plurality of pages, wherein each memory cell spans a group of the pages in one of the memory blocks, and wherein the flash controller comprises circuitry configured to receive data to be written to the MLC flash memory, select only one page, from each group of the pages, in one or to more of the memory blocks, and write the data only to the selected pages.

Abstract: A higher-level system of a nonvolatile semiconductor storage device (hereinafter, semiconductor device) displays a GUI (Graphical User Interface), which receives a parameter group (one or more parameters) for controlling the processing of the semiconductor device. The higher-level system stores at least one of the parameters of the parameter group inputted to the GUI, and sends a command comprising the parameter group to the semiconductor device. The semiconductor device stores at least one of the parameters of the parameter group included in this command. The higher-level system and the semiconductor device each execute processing in accordance with the stored parameter. The semiconductor device sends, to the higher-level system, information of a log related to the processing executed in accordance with the stored parameter. The higher-level system displays feedback information on the basis of multiple times of logs. A user can change a desired parameter on the basis of this feedback information.

Abstract: A storage control device includes a controller managing a plurality of first storage areas provided with a plurality of storage devices and a plurality of second storage areas in a particular first storage area of the plurality of first storage areas. Each of the plurality of first storage areas having a first fixed area size and each of the second plurality of storage areas having a second fixed area size which is smaller than the first fixed area size. The controller is adapted to allocate the particular first storage area to the virtual volume so that data of the write command are written to a particular second storage area of the plurality of second storage areas when a write command to a virtual volume of a plurality of virtual volumes is received.

Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.

Abstract: A memory controller, a nonvolatile storage device, an access device, and a nonvolatile storage system enable the storage architecture to be changed flexibly for intended use that can be changed variously. A nonvolatile storage system (100) sets a temporary area (23) and a normal access area of a nonvolatile memory (22) based on a use condition designated by a use condition designation unit (11) of an access device (1). This structure enables the nonvolatile storage system (100) to change the temporary area (23) and the normal access area (24) to be prepared in the nonvolatile memory (22) by changing the use condition in accordance with intended use. In other words, the nonvolatile storage system (100) enables the storage architecture to be changed flexibly for intended use that can be changed variously.

Abstract: A computer-implemented method, apparatus, and virtual machine for facilitating the communication between VMs. The method of facilitating the communication between a first VM and a second VM includes: allocating a shared memory segment from within the memory of the physical machine; mapping the requested memory space addresses to the shared memory segments in response to the memory space requests from the VMs; and providing the requested memory space addresses. A method of communication from a first VM to a second VM includes: requesting a memory space in response to a notification that a shared memory segment has been allocated; obtaining the requested memory space address, which has been mapped to the allocated shared memory segment; and accessing communication data in the shared memory segment according to the address. The apparatus and virtual machine executes the steps of the methods.

Abstract: Example embodiments include a memory module having a first volatile memory, a second volatile memory, a nonvolatile memory, and a controller configured to control an operation of the second volatile memory, and an operation of the nonvolatile memory. When first write data received from an external controller are written to the first volatile memory in a write operation, the controller receives and writes the first write data to the second volatile memory. The controller is configured to perform backup and restore operations using a buffer, the nonvolatile memory, the first volatile memory, and/or the second volatile memory. Example embodiments include a memory module having a first nonvolatile memory, a second nonvolatile memory, and a third nonvolatile memory, with corresponding backup and restore features. Example embodiments also include methods for processing the data and operating the various components of the memory system.

Abstract: A file system including a first memory unit which is non-volatile and has a plurality of blocks, a control unit configured to select one of the plurality of blocks of the first memory unit, determine whether the selected block is a valid block, control a data write with respect to the selected block if the selected block is a valid block, divide the plurality of blocks into valid blocks and bad blocks by checking the plurality of blocks of the first memory unit, generate an address table by mapping the valid blocks and the bad blocks to addresses and control a loading of the address table generated, and a second memory unit which is volatile and stores the address table for the plurality of blocks of the first memory unit.

Abstract: A memory system comprises a storage device and a host. The host classifies pages stored in the storage device into a plurality of data groups according to properties of the pages, and transmits setup information regarding the classified data groups to the storage device.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments include a method comprising detecting addition of a new nonvolatile machine-readable medium to a data storage pool of nonvolatile machine-readable media. The method includes preventing from being performed a first operation of a file system that requires a first parameter that identifies a logical indication of a location within the nonvolatile machine-readable media for the file system, until logical indications of locations within the new nonvolatile machine-readable medium for the file system have been stored in the data storage pool. The method includes allowing to be performed, prior to logical indications of locations within the new nonvolatile machine-readable medium being stored in the data storage pool, a second operation of the file system that does not require a second parameter that identifies a logical indication of a location within the nonvolatile machine-readable media, wherein the second operation causes data to be written into the new nonvolatile machine-readable medium.

Abstract: The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Abstract: Example methods, apparatus, and articles of manufacture to access data are disclosed. A disclosed example method involves generating a key-value association table in a non-volatile memory to store physical addresses of a data cache storing data previously retrieved from a data structure. The example method also involves storing recovery metadata in the non-volatile memory. The recovery metadata includes a first address of the key-value association table in the non-volatile memory. In addition, following a re-boot process, the locations of the key-value association table and the data cache are retrieved using the recovery metadata without needing to access the data structure to re-generate the key-value association table and the data cache.

Abstract: In memory system in which the processing unit (30) performs input/output of data in a plurality of memory circuits (10-0-10-3) through a memory bus (20-0), a memory interface circuit (14) is provided. The memory interface device (14) collects specification information of the plurality of memory circuits (10-0˜10-3), creates and stores a common specification information and is connected to the control bus (22-0) of the processing unit (30).

Abstract: A method and apparatus for managing address map information are disclosed. In one embodiment, an apparatus may comprise a processor configured to store address map changes to a first data storage medium, save the address map changes to a nonvolatile data storage medium when an abnormal power state is detected, and when the power state is no longer abnormal retrieve the last saved address map information and address map changes and update the address map information using the address map changes. The apparatus may be configured to retrieve the instructions for the processor operation over a network connection.

Abstract: Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.

Abstract: A solid state drive (SSD) including a storage that includes a plurality of flash memories configured to be independently drivable and a controller to receive an input/output (I/O) request from a host, to split the I/O request into a plurality of sub-requests each having a size configured to be capable of being processed independently by each flash memory, and to process the I/O request based on the sub-requests.

Abstract: The present disclosure relates to the drift management for a memory device. In at least one embodiment, the memory device of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a memory controller that is capable of implementing drift management to control drift. Other embodiments are described and claimed.