Abstract: In one example, a flash storage device includes a flash memory and a controller. The flash memory includes non-volatile memory cells organized into blocks. The blocks are switchable between multi-bit mode and single-bit mode for storing data. The blocks in single-bit mode have a lower storage density and a higher write endurance than the blocks in multi-bit mode. The controller is configured to receive a write request from a host, and to determine whether a trigger event has occurred to switch one or more of the blocks from multi-bit mode to single-bit mode. Based on the controller determining that the trigger event has occurred, the controller is further configured to switch the one or more blocks from multi-bit mode to single bit mode, and to store, in single-bit mode, data for the write request in the one or more blocks at the lower data storage density.

Abstract: Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.

Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including a non-volatile storage including a superblock and a controller configured to notify a host of a size of the superblock to a host, determine a stream that aligns with the superblock, write data corresponding to the stream to the superblock, and determine that writing the data correspond to the stream has completed.

Abstract: A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.

Abstract: Techniques are provided for block-level fail atomicity on byte-level non-volatile media. In one technique, an offset table and application data that stores content of a file are stored for a file. The offset table includes multiple entries, each entry being associated with a different offset value and storing a logical block address (LBA) that references a location in the application data. In response to receiving a request, that includes an input buffer and an offset value, to update the file: (a) an entry, in the offset table, that corresponds to the offset value and comprises a first LBA is identified; (b) a second LBA that is considered free is identified; (c) the second LBA is replaced with the first LBA; (d) the input buffer is written to a location, in the application data, that the second LBA references; and (e) the second LBA is added in the entry.

Abstract: A method for managing data in a NAND flash storage system is provided. The method includes one or more of receiving an empty data segment directive at a storage controller, returning a data string including data of a predetermined logic level in response to a read command requesting to read data associated with a logical identifier included in the empty data segment directive, maintaining an index of mapping between the logical identifier and a physical storage location, updating the index to indicate data at the physical storage location does not need to be preserved, monitoring one or more physical storage locations, including the physical storage location, to determine a percentage of the one or more physical storage locations that do not need to be preserved, and initiating garbage collection on the one or more physical storage locations in response to the percentage reaching a threshold. The empty data segment directive includes a logical identifier associated with the physical storage location.

Abstract: A data-compression analyzer can rapidly make a binary decision to compress or not compress an input data block or can use a slower neural network to predict the block's compression ratio with a regression model. A Concentration Value (CV) that is the sum of the squares of the frequencies and a Number of Zero (NZ) symbols are calculated from an un-sorted symbol frequency table. A rapid decision to compress is signaled when their product CV*NZ exceeds a horizontal threshold THH. During training, CV*NZ is plotted as a function of compression ratio C % for many training data blocks. Different test values of THH are applied to the plot to determine true and false positive rates that are plotted as a Receiver Operating Characteristic (ROC) curve. The point on the ROC curve having the largest Youden index is selected as the optimum THH for use in future binary decisions.

Abstract: The disclosed embodiments are directed to improving the lifespan of a memory device. In one embodiment, a system is disclosed comprising: a host processor and a memory device, wherein the host processor is configured to receive a write command from a virtual machine, identify a region identifier associated with the virtual machine, augment the write command with the region identifier, and issue the write command to the memory device, and the memory device is configured to receive the write command, identify a region comprising a subset of addresses writable by the memory device using a region configuration table, and write the data to an address in the subset of addresses.

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: writing data into a plurality of pages of a specific block, and establishes or updates a F2H mapping table based on physical addresses of the plurality of pages and logical addresses of the data; using the F2H mapping table to update a H2F mapping table; initializing a flush-bitmap, wherein the flush-bitmap records a plurality of flush bits corresponding to the physical addresses of the plurality of pages, respectively; receiving a trim command from a host device, wherein the trim command asks to mark at least one of the logical addresses of the data as invalid; updating the H2F mapping data according to the trim command; updating the flush-bitmap according to the trim command; and writing the updated H2F mapping table and the updated flush-bitmap into the flash memory module.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superbkock management based on memory component reliabilities.

Abstract: Coalescing write operations in a cloud-based storage system including receiving, from a storage controller application of the cloud-based storage system, a first plurality of write operations, wherein each of the first plurality of write operations comprises a respective write to a storage volume; coalescing the first plurality of write operations into a plurality of coalesced write operations, wherein each of the coalesced write operations are configured to effect two or more of the first plurality of write operations; and performing the plurality of coalesced write operations on the storage volume.

Abstract: A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

Abstract: A storage device read-disturb-based block read temperature utilization system includes a storage device chassis housing a storage subsystem. A local read temperature utilization subsystem in the storage device chassis determines that data in a first block in the storage subsystem should be moved and, in response determines read disturb information for the first block and uses it to identify relative read temperatures for a plurality of rows in the first block in the storage subsystem. The local read temperature utilization system then moves the data from the first block in the storage subsystem to at least one second block in the storage subsystem based on the relative read temperatures identified for the plurality of rows in the first block in the storage subsystem.

Abstract: A memory system includes a nonvolatile memory including blocks, and a memory controller. The memory controller is configured to set each of the blocks to be in one of a plurality of states, including first, second, third, and fourth states. The memory controller is configured to detect a predetermined condition related to at least one of an amount of data being written into blocks in the first state and state transition of a block, upon detection of the predetermined condition, determine a maximum number of blocks to be in the fourth state based on a length of time during which each block in the fourth state has been in the fourth state, and perform an erase operation to cause one or more blocks in the third state to transition to the fourth state when a current number of blocks in the fourth state is less than the maximum number.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.

Abstract: A data processing system may include a storage device configured to: transmit, to an exterior, prediction information, for each power mode, that indicates a predicted time for performing a background operation for managing a memory device; and perform the background operation in an idle state of the storage device by switching to a corresponding power mode in response to a power mode control signal that is received in the idle state; and a control device configured to: determine a power mode of the storage device and an idle time for the idle state during which the background operation is performed based on the prediction information; transmit the power mode control signal to the storage device; and suspend, during the idle time, execution of a command processing request transmitted to the storage device.

Abstract: A processing-in-memory includes: a memory; a register configured to store offset information; and an internal processor configured to: receive an instruction and a reference physical address of the memory from a memory controller, determine an offset physical address of the memory based on the offset information, determine a target physical address of the memory based on the reference physical address and the offset physical address, and perform the instruction by accessing the target physical address.

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A data storage device includes a non-volatile memory device including one or more memory dies and a controller. The controller is configured to receive a pseudocode file and a search key from one or more external devices and perform an index search based on the received pseudocode and search key. The controller may further determine a data file associated with the performed index search and output the determined data file to the one or more external device.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A multi-stream solid-state device (SSD) includes a normal-access memory associated with a first stream ID, a high-access memory having a higher endurance than the normal-access memory and being associated with a second stream ID, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform identifying a data stream ID of an input data stream as one of the first and second stream IDs, in response to identifying the data stream ID as the first stream ID, storing the input data stream in the normal-access memory, and in response to identifying the data stream ID as the second stream ID, storing the input data stream in the high-access memory.

Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.

Abstract: In a closed-loop garbage collection system a comparator receives a first target time indicating when a first superblock of memory is expected to be filled based on a first write rate for a first write cursor writing data units into the first superblock. The comparator further receives a negative loop feedback based on one or more elements from the garbage collection process. The comparator determines a first garbage collection rate based on the first target time and the negative loop feedback, where the first garbage collection rate is calculated to provide a free empty superblock to the first write cursor within a range of time of the first target time. The comparator sends instructions to a garbage collection manager to perform a garbage collection process at the first garbage collection rate, wherein an outcome of the garbage collection process is incorporated into the negative loop feedback sent to the comparator.

Abstract: The present application discloses a method for fabricating a semiconductor device including providing a first stacking structure comprising a first controller die, and a plurality of first storage dies sequentially stacked on the first controller die; providing a second stacking structure comprising a second controller die, and a plurality of second storage dies sequentially stacked on the second controller die; bonding the first controller die onto a bottom die through a plurality of first interconnect units; and bonding the second controller die onto the bottom die through a plurality of second interconnect units. The plurality of first storage dies respectively comprise a plurality of first storage units configured as a floating array. The plurality of second storage dies comprise a plurality of second storage units respectively comprising an insulator-conductor-insulator structure.

Abstract: A memory system includes a memory and a controller. The memory is configured to store a number of valid data in each of a plurality of logical blocks and a number of valid data for each of a plurality of banks in each of the logical blocks. The controller is configured to: select logical blocks of garbage collection target candidates based on the numbers of valid data in the logical blocks; calculate a maximum value among the numbers of valid data for the banks in each of the logical blocks of the garbage collection target candidates as a respective comparison value; and select one of the logical blocks of the garbage collection targets based on comparing the respective comparison values of the logical blocks of the garbage collection target candidates with each other.

Abstract: A storage device according to the present technology may include a memory device for storing data, a buffer memory configured to temporarily store data to be stored in the memory device, and a memory controller configured to determine a delay time based on a plurality of parameters upon receipt of a write request from a host, and transmit a data request to the host after the delay time has elapsed.

Abstract: The present technology provides a method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells. The method of operating the semiconductor memory device includes selecting a target state in which the threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. Masking to the target state is applied in each of the plurality of sensing operations.

Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.

Abstract: Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

Abstract: A method of operating a controller for controlling a memory device that comprises a plurality of memory cell blocks including outputting block address information based on reliability information for each of the memory cell blocks, providing a patrol read command to the memory device, and controlling the memory device to perform the patrol read operation in response to the patrol read command wherein the block address information comprises an order of the patrol read operation for the memory cell blocks based on the reliability information may be provided.

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

Abstract: Dynamically managing control information in a storage device, including: querying, by an array management module executing on a storage array controller, the storage device for a location of control information for the storage device, the control information describing the state of one or more memory blocks in the storage device; and issuing, by the array management module in dependence upon the location of the control information for the storage device, a request to retrieve the control information for the storage device.

Abstract: A memory management method of a storage device including: programming write-requested data in a memory block; counting an elapse time from a time when a last page of the memory block was programmed with the write-requested data; triggering a garbage collection of the storage device when the elapse time exceeds a threshold value; and programming valid data collected by the garbage collection at a first clean page of the memory block.

Abstract: Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include writing a memory object to a first memory device of a first type of memory medium. The example method can include determining that a size of the memory object meets or exceeds a threshold data size. The example method can include writing the memory object to a second memory device that comprises a second type of memory medium different than the first type. The first memory medium can be a non-volatile memory comprising phase-change memory or resistive random access memory (RAM) and the second memory medium can be NAND Flash or NOR Flash.

Abstract: A method of operating a storage device including a non-volatile memory includes storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes a pre-defined number of blocks of the non-volatile memory, performing a read operation on a first block included in a first super block based on a first read level, storing the first read level as a history read level of the first super block in a history buffer when the read operation on the first block is successful, receiving a read request for a second block of the first super block and an address of the second block from a host, and performing a read operation on the second block based on the history read level stored in the history buffer. The pre-defined number is at least two.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each memory block including memory cells capable of storing multi-bit data, and a controller configured to allocate the plurality of memory blocks for plural zoned namespaces input from an external device and access a memory block allocated for one of the plural zoned namespaces which is input along with a data input/output request. In response to a first request input from the external device, the controller adjusts a number of bits of data stored in a memory cell included in a memory block, which is allocated for at least one zoned namespace among the plural zoned namespaces, and fixes a storage capacity of the at least one zoned namespace.

Abstract: Methods and systems for managing communications is disclosed. A host device and a management controller may communicate via memory mapped communications using shared memory. To improve the security of the memory mapped communications, access requests for shared memory may be monitored. Access controls for the shared memory may be put in place to reduce the likelihood of data being made unavailable before it is processed. The access controls may be lifted when the data stored in shared memory has been read by to complete the memory mapped communications.

Abstract: The present invention relates to the field of digital memory, and in particular to a multiple-time programmable (MTP) memory employing error correction codes (ECC), the MTP memory being made up of one-time programmable (OTP) memory modules. Pointers to the memory address of currently in-use OTP memory blocks in use for each virtual MTP memory block are stored in OTP memory with an error correcting code. The pointers encode the memory addresses according to a scheme that ensure that only bit changes in a single direction are required in both the pointer data and the error correction code when the memory address is incremented.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a deallocation command corresponding to a plurality of deallocation requests, where each of the plurality of deallocation requests corresponds to a logical block address (LBA) range, determine that at least one of the plurality of deallocation requests is an unaligned deallocation request, generate a tag for metadata for the unaligned deallocation request, wherein the tag for the metadata includes a direction bit and a length bit, concatenate the metadata including the tag to an LBA range of the unaligned deallocation request, and complete the deallocation command using the metadata including the tag. Aligned deallocation requests are stored in a buffer. The concatenated unaligned deallocation requests are completed prior to completing the aligned deallocation requests from the buffer.

Abstract: Methods, systems, and devices for suspend operation with data transfer to a host system are described. A host system may transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) indicating for the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a decreased power consumption). Here, the memory system may transmit an image of the memory system stored in volatile memory to the host system and transition the memory system to the second mode. Additionally, the host system may transmit, to the memory system operating in the second mode, a write command including the image and indicating for the memory system to transition to the first mode. Here, the memory system may write the image to the volatile memory and transition to the first mode.

Abstract: The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Abstract: In one embodiment, a multi-tenant computing system includes at least one processor including a plurality of cores on which a plurality of agents of a plurality of tenants of the multi-tenant computing system are to execute, a configuration storage, and a memory execution circuit. The configuration storage includes a first configuration register to store configuration information associated with the memory execution circuit. The first configuration register is to store a mode identifier to identify a mode of operation of the memory execution circuit. The memory execution circuit, in a first mode of operation, is to receive encrypted data of a first tenant of the plurality of tenants, the encrypted data encrypted by the first tenant, generate an integrity value for the encrypted data, and send the encrypted data and the integrity value to a memory, wherein the integrity value is not visible to the software of the multi-tenant computing system.

Abstract: A storage device includes: a memory device including a plurality of memory blocks; a buffer memory device including first and second buffers which temporarily store write data; and a memory controller for controlling the memory device and the buffer memory device to perform a write operation of storing the write data in the memory device. The memory controller allocates a command to a mapping table including mapping information corresponding to a physical address according to a reception order of the command, when the memory controller receives the command from a host, and controls the buffer memory device such that write data is temporarily stored in a corresponding one of the first and second buffers. When write data temporarily stored in the first or second buffer is flushed to the memory device, the memory controller updates the mapping table, using mapping information corresponding to the flushed write data.

Abstract: Methods, systems, and devices for multiple flash translation layers (FTLs) at a memory device are described to support two or more FTLs within a memory device. A first FTL may be configured to support data mapping using a defined granularity and a second FTL may be configured to support data mapping using a smaller granularity than the defined granularity or data that does not match the defined granularity, based on one or more characteristics of the data. A memory device may select between the FTLs to map data based on the one or more characteristics of the data and may write the data to the memory device. The memory device may store logical-to-physical mapping associated with the data, among other information, using the selected FTL.