Abstract: A storage device may include at least one storage medium, and a controller that may include at least one processor configured to perform an update operation associated with a reclaim unit handle that references at least one reclaim unit of the at least one storage medium, read, based on the update operation, data from a first reclaim unit of the at least one storage medium, and write, based on the update operation, the data to a second reclaim unit of the at least one storage medium. Based on the update operation, the second reclaim unit may be associated with the reclaim unit handle. The first reclaim unit may be associated with the reclaim unit handle. The reclaim unit handle may be a first reclaim unit handle, and the first reclaim unit may be associated with a second reclaim unit handle.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Abstract: A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

Abstract: A system analyzes data associated with a failure of an information handling system by evaluating memory addresses found in memory, such as bug check parameters, context register values, or stacks in a memory dump, at the time of a fatal error to determine whether one of the memory addresses has a single-bit error, and modifying a first memory address with the single-bit error to generate a second memory address, wherein the first memory address is one of the memory addresses being evaluated. If a second memory address is mapped to the page table, the system authorizes a repair of the information handling system.

Abstract: A method for dynamically replicating data in a disaggregated distributed storage system includes receiving, by a processor, a request from a controller to replicate data; dynamically selecting, by the processor, a storage node for replicating the data from among a plurality of storage nodes, based on one or more replication parameters associated with each storage node of the plurality of storage nodes, wherein the one or more replication parameters include at least one of a flash factor corresponding to the each storage node, and a latency between the controller and the each storage node; and providing, by the processor, information about the selected storage node to the controller for replicating the data.

Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.

Abstract: Provided is a method for operating a memory device including performing a first setting operation on a first operation, reading map data based on the first setting operation, and performing a second setting operation on a second operation.

Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.

Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services while managing limited hardware resources necessary to provide the services, a hibernation may be performed. To do so, a hibernation manager may facilitate management and storage of hibernation data for use during hibernation and startup of a system. To manage and store the hibernation data, the hibernation manager may identify an allocation of high-performance storage for the hibernation data, obtain a compression pipeline based on the allocation, and stream the hibernation data through the compression pipeline. By doing so, the speed in which the hibernation data is written and read may be increased. Thus, hibernation and startup of the system may be enhanced.

Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

Abstract: A computer-implemented method, according to one embodiment, is for performing garbage collection. The computer-implemented method includes: causing pages in non-volatile memory that are due for garbage collection to be inspected, and causing certain ones of the pages in the non-volatile memory having valid data therein to be identified. Each of the pages of non-volatile memory includes multiple planes, and the valid data is included in one or more of the planes in the respective identified pages. Recirculation requests, that selectively exclude planes in the identified pages that do not include any of the valid data, are further sent to a recirculation pool.

Abstract: A memory system is provided to include a memory device and a memory controller. The memory controller is configured to set, for a first memory die, a state check memory block that is used to check a state of data stored in memory blocks included in the first memory die, and the memory controller is further configured to manage, for each of a plurality of temperature periods that are predetermined, (1) a state check page corresponding to a temperature period and included in the state check memory block and (2) a program memory block list indicating information on certain memory blocks programmed at a time that a temperature of the memory system falls within the temperature period.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to maintain a plurality of virtual pools, wherein each virtual pool corresponds with an logical block address (LBA) range, update a counter of a virtual pool, wherein the counter corresponds to a health of the LBA range, and select, based on the counter, the virtual pool to program data to. The controller is further configured to maintain a counter for each application having data programmed to the virtual pool, where the counter is increased for each write operation to the virtual pool. When the counter equals or exceeds a threshold value, the controller is configured to send a warning to each application associated with the virtual pool having the counter that equals or exceeds the threshold value.

Abstract: A data storage apparatus includes an integrated circuit further including a control unit and a memory array of charge-based memory cells. The memory array includes a first subsection which is operable as a memory, and includes a second subsection which is operable as a dosimeter. The control unit is operable to provide a reference current and to conduct memory access operations to access the memory with reference to the reference current. The control unit is further operable to analyze a statistical distribution of read currents by using memory access operations in the second subsection. Said analysis involves counting of logical read errors of the memory access operations and calibrating the reference current depending on a number of counted logical read errors being indicative also of a Total Ionizing Dose, TID.

Abstract: The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.

Abstract: According to an embodiment, a control device executes control processing based on data stored in a first storage device and a second storage device while performing rewrite in the first storage device. The control device stores a memory image relating to the first storage device at a point of time, at which activation processing is terminated, in a non-limited storage area of the second storage device, the activation processing being based on the data stored in the limited storage area of the second storage device without being based on the data stored in the first storage device. The control device starts the control processing from the point of time, at which the activation processing is terminated, after loading the memory image stored in the non-limited storage area of the second storage device in the first storage device in the activation processing of the control processing.

Abstract: Supporting a stateless controller in a storage system, including: sending, from a storage system controller to a storage device, a request for one or more locations of control information for the storage device, the storage system controller being external to the storage device; receiving, from the storage device, the one or more locations of one or more memory blocks that include the control information; and retrieving, from the storage device, the control information from the one or more memory blocks.

Abstract: A method and an apparatus for dynamically managing a shared memory pool are provided, to determine, based on different service scenarios, a shared memory pool mechanism applicable to a current service scenario, and then dynamically adjust a memory pool mechanism based on the determined result. The method for dynamically managing a shared memory pool includes: determining a first shared memory pool mechanism for the shared memory pool, where the first shared memory pool mechanism is a fixed memory pool mechanism or a dynamic memory pool mechanism; determining a second shared memory pool mechanism suitable for a second service scenario based on the second service scenario, where the second shared memory pool mechanism is a fixed memory pool mechanism or a dynamic memory pool mechanism; and when the second shared memory pool mechanism is different from the first shared memory pool mechanism, adjusting the first shared memory pool mechanism to the second shared memory pool mechanism.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may retrieve, from a solid state drive (SSD), information that includes an original storage size of the SSD, a number of terabytes written, and a number of program/erase (P/E) cycles that occurred within the SSD; determine that a number of terabytes written is not above the threshold value of terabytes written; determine a threshold number of P/E cycles remaining associated with the SSD; determine that a number of P/E cycles remaining of the SSD is above the threshold number of P/E cycles remaining associated with the SSD; determine an overprovisioning percentage, which would produce a write amplification factor at or below a write amplification factor threshold, based at least on the number of P/E cycles remaining; determine configuration data for the SSD; and configure the SSD with the configuration data.

Abstract: A storage device includes a non-volatile memory and a memory controller. The memory controller selects a selection memory block to store data in response to pattern data corresponding to a logical address associated with a write request, and provides, to the non-volatile memory, a physical address of the selection memory block, as well as data and a write command associated with the write request.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. The controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. The controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.

Abstract: Provided herein may be a memory controller and a memory system including the same. The memory controller may include a plurality of control cores configured to control a plurality of zone blocks respectively corresponding to logical address groups provided by a host, a buffer memory configured to store information about a zone group including zone blocks which are controlled by different control cores among the plurality of zone blocks, the information about zone group being generated based on information about an available space in each of the plurality of zone blocks, and a wear-leveling controller configured to control the plurality of control cores to perform a global wear-leveling operation of swapping pieces of data between the zone blocks included in the zone group based on a wear-level of the plurality of zone blocks.

Abstract: Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.

Abstract: SSD service life is extended by monitoring wear-level and prompting relocation of unstable data out of SSDs that have reached a soft wear-level threshold such that those SSDs do not contain unstable data when those SSDs reach a hard wear-level threshold. The progression of SSD wear-level is forecasted using an ARIMA algorithm. Unstable data on SSDs between predicted times of reaching the soft and hard thresholds is replaced by stable data from SSDs that have not reached the soft wear-level threshold. The stable data may be snapshot data and deduplicated data and deduplication hashes characterized based on number of references. SSDs that reach the hard threshold without unstable data can remain in service for read IOs until being replaced.

Abstract: A memory authentication system initiates various memory operations on a memory chip and then assesses the performance of the memory chip in performing such operations in an attempt to identify a signature in the chip's performance that can be used to identify the chip's source. As an example, a partial erase operation may be performed on programmed memory cells in order to drain some charge from the cells but allowing some charge to remain in the cells. Due to process variations during manufacturing, charge should drain from the cells at different rates such that some of the cells may flip to an erase state while other cells remain in a program state. The pattern of bit flips defines a unique signature that may be used to identify the chip's manufacturing source (e.g., the foundry at which the chip was manufactured).

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which store a single compressed value per line with a marker value in a front of the compressed version of the memory line. In some examples, the only value stored in the memory line is the value normally stored therein. This removes the complexity of the prediction tables and the inclusion of invalid values as well as preventing the penalty when those prediction tables are wrong. Furthermore, by inclusion of the marker in the beginning of the memory line, the system can quickly determine the compression status of the memory line without having to read the entire line. That is, it can quickly stop reading the rest of the memory line once the compressed data is read out which saves the memory device from having to read the entire line.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device may include a controller configured to be connected with a host processor and a memory, wherein the controller may be further configured to collect access information indicative of access of the host processor to the memory, and calculate tiering information indicative of accessibility of the host processor to each of a plurality of data units stored in the memory based on the access information.

Abstract: Methods, systems, and devices for techniques for failure management in memory systems are described. A memory system may include one or more non-volatile memory devices. A set of physical blocks of memory cells of the one or more non-volatile memory devices may be grouped into virtual blocks, where each physical block of a virtual may block may be within a different plane of the one or more non-volatile memory devices. The memory system may detect a failure within a physical block of a virtual block and may transfer data from the physical block to one or more other physical blocks within the same virtual block in response to detecting the failure.

Abstract: Techniques for handling data with different lifetime characteristics in stream-aware data storage systems. The data storage systems can include a file system that has a log-based architecture design, and can employ one or more solid state drives (SSDs) that provide log-based data storage, which can include a data log divided into a series of storage segments. The techniques can be employed in the data storage systems to control the placement of data in the respective segments of the data log based at least on the lifetime of the data, significantly reducing the processing overhead associated with performing garbage collection functions within the SSDs.

Abstract: The present technology includes a controller and a method of operating the same. The controller includes a stress manager configured to generate a conversion value according to a number of selected planes during an erase operation and configured to calculate a stress index of a memory block based on the conversion value, a register configured to store the stress index corresponding to the memory block, and a garbage collection manager configured to compare the stress index to a garbage collection reference value to output a garbage collection control signal.

Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.

Abstract: A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Abstract: A namespace among one or more namespaces in a memory system may be manage on the basis of a write pointer and a write count. The namespace may be managed by a memory controller of the memory system. The memory system may set the one or more namespaces, and may set, for each namespace, a write pointer indicating a position where a new data unit is to be written in that namespace and a write count indicating the number of times a data unit has been written or updated in that namespace. The memory system may determine to migrate one or more data units in a namespace based on the write pointer and the write count of that namespace.

Abstract: A method for proactively rebuilding user data in a plurality of storage nodes of a storage cluster in a single chassis is provided. The method includes distributing user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can read the user data, using erasure coding, despite loss of two of the plurality of storage nodes. The method includes determining to rebuild the user data for one of the plurality of storage nodes in the absences of an error condition. The method includes rebuilding the user data for the one of the plurality of storage nodes. A plurality of storage nodes within a single chassis that can proactively rebuild the user data stored within the storage nodes is also provided.

Abstract: Data writing methods and computing devices are provided. An example data writing method is applied to a computer system, and the computer system includes a file system and a flash memory-based storage system. The example data writing method includes obtaining a target logical address, where the target logical address is an address allocated from a first logical block to target data to be written into the flash memory-based storage system, the first logical block is one of multiple logical blocks in the file system, and the flash memory-based storage system includes multiple physical blocks. It is determined that the target logical address belongs to the first logical block. The target data is written into a first physical block based on a correspondence between the first logical block and the first physical block, where the first physical block is one of the multiple physical blocks.

Abstract: A network interface controller (NIC) capable of efficient load balancing among the hardware engines is provided. The NIC can be equipped with a plurality of ordering control units (OCUs), a queue, a selection logic block, and an allocation logic block. The selection logic block can determine, from the plurality of OCUs, an OCU for a command from the queue, which can store one or more commands. The allocation logic block can then determine a selection setting for the OCU, select an egress queue for the command based on the selection setting, and send the command to the egress queue.

Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including determining superblocks, including first and second superblocks, in a non-volatile memory storage. The non-volatile memory storage includes independent locations that may be planes or dies. The first superblock includes first blocks corresponding to first independent locations, and the second superblock includes second blocks corresponding to second independent locations. A first number of the first independent locations is less than a number of the independent locations. A second number of the second plurality of independent locations is less than the number of the independent locations.

Abstract: Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

Abstract: Disclosed herein are systems and methods for launching multiple software virtual appliances inside a single virtual environment. In one aspect, a method includes detecting a base image on which a plurality of virtual appliances are based, wherein each of the plurality of virtual appliances is configured to be launched in a separate virtual environment. The method includes preparing a virtual environment that is compatible with the base image. For each respective virtual appliance in the plurality of virtual appliances, the method includes calculating a differential between the base image and the respective virtual appliance, and including the differential in a patch file. The method includes applying the patch file to the base image to form a final appliance, and launching the final appliance in the virtual environment.

Abstract: Provided are a method and apparatus for processing abnormal power failure of a solid state disk, and an electronic device and a computer-readable storage medium. The method includes: in response to detecting an abnormal power failure of a solid state disk, acquiring a write operation for the solid state disk; in response to the write operation being a cold data write operation, acquiring a write address corresponding to the write operation, and discarding the cold data write operation, wherein the write address points to a cold data block; obtaining the minimum write address of the cold data block by using the write address; and generating, by using the minimum write address, data block information corresponding to the cold data block.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

Abstract: A data storage device includes a non-volatile memory device including a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. A read command is received from an external device and the controller determines whether a read operation associated with the read command is a sequential read operation. One or more relocation operations are performed in response to determining that the read operation is a sequential read operation. The one or more relocation operations are executed in an order based on a priority associated with each of the one or more relocation operations.

Abstract: A method for accelerating reading of a storage medium, a read acceleration hardware module, and a memory are provided. The method includes: receiving logical block address (LBA) information issued from a front end (FE) of a memory; performing a table lookup operation based on a table lookup algorithm fixed in hardware to acquire valid physical media address (PMA) information corresponding to the LBA information; and converting the valid PMA information to Nand physical address (NPA) information based on an address translation algorithm fixed in the hardware, and reading corresponding data from a storage medium of the memory according to the NPA information.

Abstract: A memory device may detect a memory operation that updates a level two volatile (L2V) entry stored in an L2V table. Each L2V entry in the L2V table may indicate a mapping between a respective logical block address (LBA) and a respective user data physical address in non-volatile memory. The memory operation may cause a mapping between an LBA indicated in the L2V entry and a user data physical address indicated in the L2V entry to become invalid. The memory device may store, in a volatile memory log, an indication of an LBA region that includes the LBA. The memory device may detect that an L2 transfer condition, associated with the volatile memory log, is satisfied. The memory device may copy, from volatile memory to non-volatile memory, every L2V entry that indicates an LBA included in the LBA region based on detecting that the L2 transfer condition is satisfied.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, a snapshot create operation of a volume to create a first snapshot. Existing dirty data of the volume for the first snapshot may be flushed from an in-memory cache. New writes to the volume for the first snapshot may be maintained in the in-memory cache as dirty. A snapshot create operation to the volume may be received to create a second snapshot. The new writes to the volume for the first snapshot may be combined as part of the second snapshot.

Abstract: Data being stored in a block of flash memory system may be characterized as being frequently modified or infrequently modified (hot/cold) based on a heuristic. When performing garbage collection, if the data from hot blocks is consolidated and data from cold blocks is separately consolidated by writing the data to different free blocks, the number of write operations to perform the garbage collection may be reduced. The lower “write amplification” contributes to increasing the lifetime of the memory circuit. When the number of blocks in a pool of previously erased blocks is reduced to a threshold value, a block having data previously stored therein may be selected for garbage collection based on a second heuristic.