In Block-erasable Memory, E.g., Flash Memory, Etc. (epo) Patents (Class 711/E12.008)
  • Patent number: 10318200
    Abstract: A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing data, and a plurality of memory blocks each having the pages; and a controller suitable for programming test data to a first memory block among the memory blocks before a first time point, and programming meta-data corresponding to the program of the test data to a second memory block among the memory blocks, in case where the memory system including the memory device is changed from a power-on state to a power-off state at the first time point.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 9293189
    Abstract: Integrated circuits that include SRAM cells having additional read stacks are provided. In accordance with one embodiment an integrated circuit includes a memory storage array of memory cells. The integrated circuit includes a read stack coupled to each memory cell of the memory storage array. Each read stack includes a read pull-down transistor having a first threshold voltage, and a read pass gate transistor coupled in series with the read pull down transistor and having a second threshold voltage greater than the first threshold voltage.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ralf van Bentum, Torsten Klick
  • Patent number: 9043568
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Steven G. Glassen, Kenneth J. Oakes, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 9043541
    Abstract: A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Keiichi Tsutsui, Kenichi Nakanishi, Naohiro Adachi
  • Patent number: 9043533
    Abstract: A method is used in sizing volatile memory (VM) cache based on flash-based cache usage. A user selection for a flash-based cache is received. Based on the selection, configuration and sizing factors are provided, by a flash based cache driver, to VM cache size determination logic. Based on the configuration and sizing factors and a sizing formula and rules, a requested VM cache size is produced by the VM cache size determination logic. Based on the requested VM cache size, the VM cache is caused, via VM cache resizing logic, to be resized to the requested VM cache size.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: May 26, 2015
    Assignee: EMC Corporation
    Inventors: Peter Shajenko, Jr., Kevin S. Labonte, Charles H. Hopkins, Thomas E. Linnell, Feng Zhou
  • Patent number: 9043564
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
  • Patent number: 9037785
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Charles W. Gainey, Jr., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • Patent number: 9037787
    Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 19, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventor: Siamack Nemazie
  • Patent number: 9037784
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Steven G. Glassen, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Harry M. Yudenfriend
  • Patent number: 9032136
    Abstract: A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bing Dai, Chung H. Lam, Jing Li
  • Patent number: 9026723
    Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihisa Fujimoto
  • Patent number: 9026724
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 9021184
    Abstract: In a flash memory device, after an updated value is copied from a first block to a second block, a block management value of the first block is set to an unused state, and maintenance is performed to erase data from the first block. When performing maintenance, the block management value of the first block B1 is rewritten from “$FFF0” to “$FFFF.” When a reset occurs and the power supply is deactivated during the maintenance, the digit of “$0” in the block management value may become “1” to “E” of the hexadecimal system. In this manner, when the block management value includes a single digit of “1” to “E” and three digits of “F,” the reading of an updated value from the block corresponding to the block management value is restricted.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Yosuke Ohashi, Kazunori Arakawa, Tetsuya Egawa, Hidekazu Adachi
  • Patent number: 9021180
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Driever, Steven G. Glassen, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Harry M. Yudenfriend
  • Patent number: 9021226
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Driever, Steven G. Glassen, Kenneth J. Oakes, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 9021179
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Driever, Charles W. Gainey, Jr., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • Patent number: 9015427
    Abstract: A system and method are provided for updating a non-volatile memory (NVM) in an image forming device by employing the programmability of an electronically readable/writable memory module such as a customer replaceable unit monitor (CRUM) associated with a customer replaceable unit (CRU) as a vehicle for completing the needed updates in NVM values at the time of replacement of the CRU. Replacement of the CRU, where such replacement is verified by return of an expended CRU to the manufacturer, provides confirmation of updates to the NVM values. The CRUM provides a secure means to change image output terminal (IOT) set points and CRU related values stored in NVM locations that otherwise would require a manufacturers' customer service personnel visit to update. By providing an NVM location (chain/link), the value to be used and a one-time use authentication string, an automated update to the NVM is performed in a secure manner.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 21, 2015
    Assignee: Xerox Corporation
    Inventors: Heiko Rommelmann, Alberto Rodriguez
  • Patent number: 9015425
    Abstract: An apparatus, system, and method are disclosed for implementing nameless storage operations. Storage clients can access and allocate portions of an address space of a non-volatile storage device to a nameless storage request. The methods include receiving from a storage client, a nameless storage request configured for storing data in an unspecified, available address of a logical block address of a non-volatile storage device, determining whether there exists enough logical capacity in the logical address space to satisfy the nameless storage request, allocating a logical identifier to the nameless storage request, and sending the allocated logical identifier to the storage client. Other embodiments are described.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 21, 2015
    Assignee: Intelligent Intellectual Property Holdings 2, LLC.
    Inventors: David Flynn, David Nellans, Xiangyong Ouyang
  • Patent number: 9015404
    Abstract: In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Ferad Zyulkyarov, Qiong Cai
  • Patent number: 9009390
    Abstract: A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Hyeog Choi, Hong Rak Son, Kyoung Lae Cho, Jun Jin Kong, Sang Hoon Lee
  • Patent number: 9009425
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
  • Patent number: 9009391
    Abstract: Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 14, 2015
    Assignee: Fastor Systems, Inc.
    Inventor: Ajoy Aswadhati
  • Patent number: 9003153
    Abstract: A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 7, 2015
    Assignee: Greenliant LLC
    Inventor: Siamak Arya
  • Patent number: 9003101
    Abstract: A non-volatile storage subsystem is described which identifies performance-sensitive commands and heterogeneous performance characteristics of portions of a non-volatile storage media, and matches the performance sensitivity of the commands with an available physical write address corresponding to performance characteristics appropriate for the performance sensitivity of the command. A command can be considered performance sensitive if it originates from a host or a preferred host among a plurality of hosts, or if the command designates a frequently accessed logical address. Performance characteristics of the storage device can be determined by physical architectures of the storage media such as the distance from the axial center of a disk media, or the architecture technology of a solid-state array. Performance characteristics can also be determined dynamically and heterogeneous performance can be encouraged by internal maintenance policies of the subsystem.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert M. Fallone, William B. Boyle
  • Patent number: 8996791
    Abstract: A flash memory device includes a flash memory unit; and a control unit configured to perform control so that data having a size smaller than a block size of the flash memory unit is sequentially written to the flash memory unit.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Keita Kawamura, Toshifumi Nishiura, Hiroaki Yamazoe
  • Patent number: 8996792
    Abstract: Random sequence data is sequentially generated based on a seed assigned to a selected memory space, and one of access-requested segments of the selected memory space is logically combined with the sequentially generated random sequence data to transfer the access-requested segment. The sequentially generating and the logically combining are iteratively performed until remaining access-requested segments all transferred.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kui-Yon Mun, Heewon Lee
  • Patent number: 8996790
    Abstract: A method, a computer readable medium and a system for managing flash memory. The method may include receiving multiple data sectors from an interface; writing the multiple data sectors into a data buffer that is nonvolatile; creating a pointer in a data management structure that is stored in a metadata buffer that is nonvolatile, for each data sector corresponding to a storage location of the data sector in the data buffer; if a predefined condition is reached, merging data sectors stored in the data buffer with data sectors that are already stored in a sequential nonvolatile portion of the flash memory device, wherein the sequential nonvolatile portion differs from the data buffer.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 31, 2015
    Assignee: DensBits Technologies Ltd.
    Inventors: Avigdor Segal, Hanan Weingarten, Alik Vainerovitch
  • Patent number: 8996784
    Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 31, 2015
    Assignee: Mediatek Inc.
    Inventors: Chung-Hung Tsai, Ming-Shiang Lai
  • Patent number: 8990480
    Abstract: According an embodiment, a semiconductor memory device includes a semiconductor memory chip to store plural pieces of data that are written and read in units of a page and are erased in units of a block including plural pages; a discarding unit to discard, after the data is written in the semiconductor memory chip with a logic address being designated, at least a portion of valid data among the plural pieces of data; a compaction unit to write the valid data excluding the discarded data in a second block among the valid data stored in a first block and erase the first block; and a controller to output, in response to a request for reading the discarded data, a response indicating that the data is unable to be read. When all the valid data included in a block are discarded, the discarding unit erases the block.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Kanno, Kazuhiro Fukutomi
  • Patent number: 8990487
    Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of a partition control area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 24, 2015
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Teruto Hirota
  • Patent number: 8990538
    Abstract: A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: March 24, 2015
    Assignee: Microsoft Corporation
    Inventors: Bruce L. Worthington, Swaroop V. Kavalanekar, Robert P. Fitzgerald, René A. Vega
  • Patent number: 8990536
    Abstract: A constrained computing device is provided. The constrained computing device includes a memory, a processor coupled to the memory, and a journaling component executed by the processor in kernel mode. The journaling component is configured to receive information descriptive of a device control, allocate, in the memory, a variable record structured according to a variable definition associated with the device control, store the information within the variable record, receive updated information descriptive of the device control, allocate, in the memory, an update record structured according to an update variable definition, store the updated information within the update record, and link the variable record to the update record.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Schneider Electric IT Corporation
    Inventor: Sean White
  • Patent number: 8990482
    Abstract: A memory system includes a nonvolatile memory area including a first area in which write-in and read-out actions on data are performed and a second area in which such actions are prohibited, first and second interfaces, and a controller configured to connect to a second host using a first wireless communication configuration when the controller determines a second wireless communication configuration to connect to the second host device is not retained in the first area, the controller controlling the first interface in so that the first host device writes data into the memory area on a basis of a command provided from the second host device. When the controller changes the first wireless communication configuration, the controller connects to the second host device using the second wireless communication configuration, and the first interface notifies an error to the first host device not to write data into the memory area.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kuniaki Ito, Takashi Wakutsu, Yasufumi Tsumagari, Shuichi Sakurai
  • Patent number: 8990476
    Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. The write look ahead information can include information about the location where data would have next been written to a memory system.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 8984207
    Abstract: Disclosed is a method of executing a write operation in a nonvolatile memory system. The method includes receiving a write command indicating the write operation and write data associated with the write operation, and determining a selected merge size for use by a merge operation responsive to the write command by determining a number of free blocks and then determining a selected free block level (FBL) from among a plurality of FBLs in accordance with the number of free blocks.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghyun Han, Mi-Hyang Lee, Jong Youl Lee
  • Patent number: 8977803
    Abstract: A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 10, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Jing Booth, Chandra M. Guda
  • Patent number: 8972651
    Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: March 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Patent number: 8966160
    Abstract: In an embodiment, a command that specifies a logical block to trim in a storage device is acquired. An entry in a logical-to-physical address (L2P) table that contains a physical address that corresponds to the logical block may be set to point to an invalid address. A trim token that specifies the logical block may be generated. The trim token may be stored in a non-volatile storage contained in the storage device.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Anand S. Ramalingam, Richard P. Mangold
  • Patent number: 8959280
    Abstract: A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 17, 2015
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
  • Patent number: 8954652
    Abstract: In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert Haas, Roman Pletka
  • Patent number: 8954708
    Abstract: A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Yeong Kim, Du-Won Hong
  • Patent number: 8954705
    Abstract: A memory space management method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. In the memory space management method, a first area and a second area are configured. An authentication information is received from a host system, and whether the authentication information matches a predetermined authentication information is determined. If the authentication information does not match the predetermined authentication information, a counting value is updated. If the counting value matches a predetermined number, a first procedure is executed. In the first procedure, a third area is configured, wherein the capacity of the third area is a sum of the capacity of the first area and at least a portion of the capacity of the second area. The third area is provided to the host system to be accessed. Thereby, the memory space of the rewritable non-volatile memory module is effectively used.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Phison Electronics Corp.
    Inventor: Ching-Wen Chang
  • Patent number: 8954659
    Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 10, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Sadahiro Sugimoto, Akihiko Araki, Masayuki Yamamoto
  • Patent number: 8947937
    Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventor: Mehdi Asnaashari
  • Patent number: 8949508
    Abstract: Systems and methods are provided for handling temporary data that is stored in a non-volatile memory, such as NAND flash memory. The temporary data may include hibernation data or any other data needed for only one boot cycle of an electronic device. When storing the temporary data in one or more pages of the non-volatile memory, the electronic device can store a temporary marker as part of the metadata in at least one of the pages. This way, on the next bootup of the electronic device, the electronic device can use the temporary marker to determine that the associated page contains unneeded data. The electronic device can therefore invalidate the page and omit the page from its metadata tables.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Nir J. Wakrat, Daniel J. Post
  • Patent number: 8943266
    Abstract: The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Hideyuki Koseki
  • Patent number: 8938574
    Abstract: Methods and systems for using one or more solid-state drives (SSDs) as a shared cache memory for a plurality of storage controllers coupled with the SSDs and coupled with a plurality of storage devices through a common switched fabric communication medium. All controllers share access to the SSDs through the switched fabric and thus can assume control for a failed controller by, in part, accessing cached data of the failed controller in the shared SSDs.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: January 20, 2015
    Assignee: LSI Corporation
    Inventors: Gerald E. Smith, Basavaraj G. Hallyal
  • Patent number: 8935458
    Abstract: Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Robert J. Royer, Jr., Amber D. Huffman
  • Patent number: 8930613
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device, a controller, an extended function section, and an extension register. The controller controls the nonvolatile semiconductor memory device. The extended function section is controlled by the controller. The extension register which is provided with a certain block length capable of defining an extended function of the extended function section. The controller processes a first command to write header data of a command to operate the extended function section to the extended function section through the extension register, and a second command to read header data of a response from the extended function section through the extension register.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Matsukawa, Akihisa Fujimoto
  • Patent number: 8929146
    Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: January 6, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie