Free Address Space Management (epo) Patents (Class 711/E12.006)
  • Patent number: 10289391
    Abstract: A method, apparatus, and computer program product for optimizing software are provided. The software includes a plurality of modules which include at least one controllable module, the method comprises: determining a shared symbol defined by the at least one controllable module, the shared symbol being a symbol used by two or more modules of the software; generating a symbol use file indicating the shared symbol defined by the at least one controllable module; and rebuilding the software based on the symbol use file, so that a symbol table in a controllable module of the rebuilt software only contains the shared symbol indicated in the symbol use file. A number of symbols in the symbol table can be reduced accurately and effectively, thereby time needed for loading the symbol table can be reduced and software execution efficiency can be improved.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Huai Yun Ban, JiuFu Guo, Jinsong Ji, Si Yuan Zhang
  • Patent number: 10282179
    Abstract: A high level programming language provides a nested communication operator that partitions a computational space. An indexable type with a rank and element type defines the computational space. The nested communication operator partitions a specified dimension of an index indexable type into segments specified by a segmentation vector and returns an output indexable type that represents the segments. By doing so, the nested communication operator allows data parallel algorithms to operate on the segments as individual units.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 7, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Paul F. Ringseth
  • Patent number: 10228976
    Abstract: Methods, systems, and computer readable media for balancing incoming connections across multiple cores are disclosed. According to one method, the method occurs at a first processor of a multi-core connection server. The first processor is one of multiple processors of the multi-core connection server configured to receive notification of incoming connection requests associated with a socket and to request the connection requests from a queue. The method includes accepting a first connection request from a queue. The method also includes determining whether a connection quota has been reached. The method further includes in response to determining that the connection quota has been reached, performing an appropriate action based on state information associated with other processors.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: March 12, 2019
    Assignee: KEYSIGHT TECHNOLOGIES SINGAPORE (HOLDINGS) PTE. LTD.
    Inventor: Adrian-Costin Catangiu
  • Patent number: 10203940
    Abstract: Systems and methods for a compiler with type inference is described herein. The compiler includes a computer program having one or more variables and context of the variables. The compiler has a type selector to infer a type of the variable using the context of the variable and dereference the variable using the inferred type. Prior to executing the computer program, the compiler carries out a type check of the variable by accessing a recommended type of the variable and comparing the recommended type and the types associated with the context of the variable.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 12, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darius Amir Hodaei, Triinu Viilup
  • Patent number: 10073759
    Abstract: Provided are techniques for identification and handling of nested breakpoints during debug session. Program code having functions, nested breakpoints, and an indication of whether each of the breakpoints is likely to be reached is displayed, in a visualization. In response to receiving input that selects a function from the functions, a call graph is displayed for the functions in the program code to enable viewing where each of the nested breakpoints is located in the program code with reference to the functions. An option to disable a nested breakpoint of the nested breakpoints for a current execution of the program code is provided. In response to receiving input that selects the option, the nested breakpoint is disabled.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, David M. Koster, Alexander J. Pogue, John M. Santosuosso
  • Patent number: 10067750
    Abstract: An example system for compiling a source file includes an optimizer that identifies a segment of code in a first source file as a potential optimization opportunity. The first source file includes high-level source code. The example system also includes a compiler that identifies a compilation record storing data indicating that the segment of code is an actual optimization opportunity and generates a representation of the high-level source code in accordance with the actual optimization opportunity. The data is based on a previous compilation of a second source file.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Anshuman Das Gupta, Sergei Larin, Matthew Curtis, Ron Lieberman
  • Patent number: 10055335
    Abstract: A method, apparatus, and computer program product to improve testing of web interfaces where each page and point of interaction in the web interfaces are represented by Page Objects. Responsive to a processor receiving code to navigate a path from a first Page Object to a second Page Object in the user interface, the path is identified as a slow path. Responsive to identifying the path as a slow path, a marker is displayed with the code.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kwan Yin Andrew Chau, Smitha Lal, Stephen Pham
  • Patent number: 10048960
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying source code used to build executable. One of the methods includes determining that a first newly created process is a compiler, the compiler being invoked to compile a source code file; after the compiler exits, generating a first hash value of an object file generated by the compiler; generating an object artifact that identifies the source code file and includes the first hash value of contents of the object file generated by the compiler; determining that the second newly created process is a linker, the linker being invoked to generate an executable file from one or more object files; generating a link artifact that includes respective hash values of each of the one or more object files used to generate the executable file; and providing the link artifact and object artifact to a static analysis system.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 14, 2018
    Assignee: Semmle Limited
    Inventor: Peter Cawley
  • Patent number: 9910418
    Abstract: A method and programming system for programming an automation component of an industrial automation arrangement, the automation component being provided with at least one special main memory, such as a cache or a tightly coupled memory, with faster access, wherein a user is provided with an input option for assigning priority values to individual tasks of the automation program when creating the program, all of those program parts which are called when executing at least the task with the highest priority assigned by the user are automatically identified, and the identified program parts being permanently storable in the special main memory such that important program parts and routines are executable in a reproducible manner at high execution speed and with a short latency time.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 6, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventor: Rudolf Mössner
  • Patent number: 9851957
    Abstract: A computer implemented method of refactoring software code to optimize execution performance by consolidating shared resources accesses, comprising: receiving target code containing code entries accessing shared resource(s); automatically creating a dependency record for each shared resource. The dependency record describes dependencies among the code entries accessing shared data items in the shared resource(s); identifying, based on the dependency record, a resource access point for each shared resource(s), wherein the resource access point is located in an execution path of the target code to precede code entries which use the shared data item(s) and follows code entries which define the shared data item(s); automatically refactoring the target code to group together code entries which use the shared data item(s), wherein the group is placed following the resource access point to consolidate shared resource accesses of the code entries to the shared resource(s); and outputting the refactored target code.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Andrei Kirshin, Gabi Zodik
  • Patent number: 9830134
    Abstract: Examples are described for a device to receive intermediate code that was generated from compiling source code of an application. The intermediate code includes information generated from the compiling that identifies a hierarchical structure of lower level sub-routines in higher level sub-routines, and the lower level sub-routines are defined in the source code of the application to execute more frequently than the higher level sub-routines that identify the lower level sub-routines. The device is configured to compile the intermediate code to generate object code based on the information that identifies lower level sub-routines in higher level sub-routines, and store the object code.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Lee Howes
  • Patent number: 9779012
    Abstract: The conventional debugger tool used to debug the Embedded System is limited to JTAG as the standard physical interface and also to specific processor. The commercial debuggers are limited to specific Operating System of the Host machine where the symbol information is being viewed. The Dynamic and Global In-system debugger provides the replacement for the typical debugger still providing the symbol information details in the Embedded System. The debugger is OS agnostic, interface agnostic, processor agnostic and compiler agnostic with optimized algorithm in the extraction of Global symbols from the Executable Binary. The Executable Binary may be encrypted to keep it more secured and Global and In-system debugger decodes the same.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: October 3, 2017
    Assignee: MBIT WIRELESS, INC.
    Inventors: Pravinkumar Muralidaran, Sivakumar Govindassamy, Prakash Neelakandan Malliga
  • Patent number: 9740644
    Abstract: A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: H. Peter Anvin, Gilbert Neiger
  • Patent number: 9742869
    Abstract: A request management subsystem is configured to establish service classes for clients that issue requests for a shared resource on a computer system. The subsystem also is configured to determine the state of the system with respect to bandwidth, current latency, frequency and voltage levels, among other characteristics. Further, the subsystem is configured to evaluate the requirements of each client with respect to latency sensitivity and required bandwidth, among other characteristics. Finally, the subsystem is configured to schedule access to shared resources, based on the priority class of each client, the demands of the application, and the state of the system. With this approach, the subsystem may enable all clients to perform optimally or, alternatively, may cause all clients to experience an equal reduction in performance.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: August 22, 2017
    Assignee: NVIDIA Corporation
    Inventors: Evgeny Bolotin, Zvi Guz, Adwait Jog, Stephen William Keckler, Michael Allen Parker
  • Patent number: 9690553
    Abstract: Embodiments include method, systems and computer program products for identifying dependency relationships in a software product. Aspects include obtaining change history data for the software product and extracting a plurality of change elements from the change history data, each change element including an identifier of a code segment that was changed and a timestamp of the change. Aspects also include creating a dependency graph based on the plurality of change elements, wherein the dependency graph includes nodes that correspond to the code segments and edges that connect nodes that were both updated in a same logical grouping, calculating a weight for each of the edges based on probability that the nodes connected by the edge will be updated together, and outputting the dependency graph.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aharon Brodie, Eitan D. Farchi, Michael E. Gildein, II, Sergey Novikov, Richard D. Prewitt, Jr., Orna Raz-Pelleg
  • Patent number: 9684546
    Abstract: A view of data transformation jobs can be presented by way of a user interface. Related jobs can subsequently be identified automatically after a job is selected based on data dependencies between jobs. Execution status can also be determined and presented such that successful and failed execution of jobs, for example, can be differentiated. Furthermore, selection of a job run that failed to execute successfully can trigger identification of related jobs runs that failed or are predicted to fail to execute successfully.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: June 20, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andrew J. Peacock, Cheryl Couris, Christina Storm, Amir Netz, Chiu Ying Cheung, Michael J. Flasko, Kevin Grealish, Giovanni M. Della-Libera, Sonia P. Carlson, Mark W. Heninger, Paula M. Bach, David J. Nettleton
  • Patent number: 9678727
    Abstract: A method and computer program product for building a multiple layer object-oriented software application with reusable components. The method includes creating business classes containing a business logic for the software application, wherein the business classes are organized into hierarchies identified as namespaces, and then generating executable programming code for the software application. From there, the method may include placing the executable programming code into an at least one assembly structure for an associated layer, wherein a security token is required to access the business classes, and wherein the business classes are created to validate each security token passed by a user interface.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 13, 2017
    Assignee: Open Invention Network, LLC
    Inventor: Mary Ellen Chaffin
  • Patent number: 9672035
    Abstract: A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: June 6, 2017
    Assignee: ARM Limited
    Inventor: Ronny Pedersen
  • Patent number: 9582398
    Abstract: Exemplary embodiments enable debugging executable code using a debugger in a computational device that provides a programming environment including a presentation layer. For example, an exemplary method includes providing a first marshalling function that receives a portion of information manipulated by the executable code and produces a presentation layer representation of the portion of the information. The presentation layer representation is compatible with a debugger that debugs the executable code. An exemplary method also includes debugging the executable code to produce a presentation layer representation of the portion of the information with the first marshalling function so as to display the presentation layer representation of the portion of the information to a user via a display device. The debugging also includes modifying the presentation layer representation of the portion of the information to produce modified information for use by the executable code, a device, or a user.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: February 28, 2017
    Assignee: The MathWorks, Inc.
    Inventors: John Elliott, Frederick Mattsson Smith, Yao Ren
  • Patent number: 9430153
    Abstract: A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction, and/or re-ordering of objects within a heap. One or more of these management tasks improve system performance by limiting movement of pages in and out of virtual memory. The garbage collection technique selectively performs garbage collection such that certain objects, such as old but live, infrequently referenced objects, are not garbage collected each time garbage collection is performed.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas J. Heller, Jr.
  • Patent number: 9372695
    Abstract: Instructions grouped into instruction groups are optimized across group boundaries. Instruction sequences spanning multiple groups are optimized by retaining information relating to an instruction at the end of one instruction group to be co-optimized with an instruction at the beginning of a subsequent instruction group. This retained information is then used in optimization of one or more instructions of the subsequent group. Optimization may be performed across n group boundaries, where n is equal to two or greater. Additionally, optimization of instructions within a group may be performed, in addition to the optimizations across group boundaries.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 21, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Michael K. Gschwind
  • Patent number: 9047333
    Abstract: A system for updating an index into a tuple table of tuples is provided. An indexing system updates an index into a tuple table using fine-grain locking of the index. The index includes a values table with an entry for each index value of an index field that references a value-tuple table that includes, for each tuple with the index value, a row that identifies a tuple of the tuple table with that indexed value. After a new tuple is added to the tuple table with a value, the index is updated by locking the entry in the values table, updating the value-tuple table for the value, and then unlocking the entry. When the index is accessed for locating tuples with a value, the accessor locks the entry in the values table for the value, uses the value-tuple table to locate the tuples, and unlocks the entry.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: June 2, 2015
    Assignee: Cray Inc
    Inventor: David Mizell
  • Patent number: 8996834
    Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Michael Edward Lyons, Bruce G. Mealey, James Bernard Moody
  • Patent number: 8954686
    Abstract: A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment are defined. Configuring a separate environment may include specifying a physical memory usage cap for the separate environment. A global resource capping background service enforces physical memory caps on any separate environments that have specified physical memory caps.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: February 10, 2015
    Assignee: Oracle America, Inc.
    Inventors: Gerald A. Jelinek, Daniel B. Price, David S. Comay, Stephen Frances Lawrence
  • Patent number: 8943259
    Abstract: Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: January 27, 2015
    Assignee: VMware, Inc.
    Inventors: Boris Weissman, Aleksandr V. Mirgorodskiy, Ganesh Venkitachalam, Feng Tian
  • Patent number: 8874838
    Abstract: A network device allocates a particular number of memory blocks in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and creates a list of additional memory blocks in an external TCAM of the network device. The network device also receives, by the external TCAM, a request for an additional memory block to provide one or more rules from one of the multiple databases, and allocates, by the external TCAM and to the requesting database, an additional memory block from the list of additional memory blocks.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 28, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Sandip Shah, Jing Ai
  • Patent number: 8856435
    Abstract: A method, apparatus and computer program product for an external, self-initializing FIFO containing indexes of free CAM memory locations is presented. When data is sent to the CAM for a lookup, this external FIFO provides the CAM with the index of a free memory location within the CAM so that if the data word is not found in the CAM (i.e. a CAM miss), the data can be written to the designated available free entry in the CAM. Thus, if the same data word is searched in the CAM in the following cycle it will result in a hit.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 7, 2014
    Assignee: Oracle America, Inc.
    Inventors: Milton H. Shih, Robert J. Weisenbach
  • Patent number: 8838930
    Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 16, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Maurizio Di Zenzo
  • Patent number: 8775776
    Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, John J. Reilly
  • Patent number: 8762674
    Abstract: Exemplary embodiments for storing data by a processor device in a computing environment are provided. In one embodiment, by way of example only, from a plurality of available data segments, a data segment having a storage activity lower than a predetermined threshold is identified as a colder data segment. A chunk of storage is located to which the colder data segment is assigned. The colder data segment is compressed. The colder data segment is migrated to the chunk of storage. A status of the chunk of storage is maintained in a compression data segment bitmap.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Carol S. Mellgren, Alfred E. Sanchez
  • Patent number: 8725939
    Abstract: A method, computer program product, and computing system for receiving a read request on a first cache system, wherein the read request identifies previously-written content included within a data array. If the previously-written content identified in the read request is stored within the first cache system in a compressed format, and the previously-written content identified in the read request is stored within the data array in an uncompressed format; a determination is made as to if it is less computationally expensive to obtain from the data array the previously-written content in an uncompressed format.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 13, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Alex Veprinsky
  • Patent number: 8719529
    Abstract: Exemplary system and computer program embodiments for storing data by a processor device in a computing environment are provided. In one embodiment, by way of example only, from a plurality of available data segments, a data segment having a storage activity lower than a predetermined threshold is identified as a colder data segment. A chunk of storage is located to which the colder data segment is assigned. The colder data segment is compressed. The colder data segment is migrated to the chunk of storage. A status of the chunk of storage is maintained in a compression data segment bitmap.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Carol S. Mellgren, Alfred E. Sanchez
  • Patent number: 8694753
    Abstract: A computing system determines whether memory data pertaining to a block of dynamically allocated memory within an inferior process memory space satisfies one or more criteria in heuristics data. The computing system identifies a category to assign to the block of dynamically allocated memory based on the determination of whether the memory data satisfies the criteria and generates a reliability score for the block of dynamically allocated memory indicating a level of reliability of the identified category. The computing system categorizes the block of dynamically allocated memory based on a comparison of the reliability score and a previous reliability score of the block of the dynamically allocated memory.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Red Hat, Inc.
    Inventor: David Hugh Malcolm
  • Patent number: 8688895
    Abstract: A data management method includes determining the size of input data, storing the input data in a log block if the size of the input data is determined to be a write unit, and storing the input data in a partial block if the size of the input data is determined to be smaller than the write unit. The log block is a temporary block storing data of same addresses and the partial block is a temporary block storing data regardless of their addresses. The memory system includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The memory controller is configured to temporarily store input data smaller than a write unit in a selected memory block even when the input data have different addresses.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chunsoo Ahn, HeeTak Shin, JaeSung Jung
  • Patent number: 8578120
    Abstract: Described in detail herein are systems and methods for single instancing blocks of data in a data storage system. For example, the data storage system may include multiple computing devices (e.g., client computing devices) that store primary data. The data storage system may also include a secondary storage computing device, a single instance database, and one or more storage devices that store copies of the primary data (e.g., secondary copies, tertiary copies, etc.). The secondary storage computing device receives blocks of data from the computing devices and accesses the single instance database to determine whether the blocks of data are unique (meaning that no instances of the blocks of data are stored on the storage devices). If a block of data is unique, the single instance database stores it on a storage device. If not, the secondary storage computing device can avoid storing the block of data on the storage devices.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: November 5, 2013
    Assignee: CommVault Systems, Inc.
    Inventors: Deepak R. Attarde, Rajiv Kottomtharayil, Manoj K. Vijayan
  • Patent number: 8484432
    Abstract: A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Hatsuda, Daisaburo Takashima, Yasushi Nagadomi
  • Patent number: 8473710
    Abstract: A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ross S. Scouller, Frank K. Baker, Jr., Venkatagiri Chandrasekaran
  • Patent number: 8447922
    Abstract: A memory controller, a nonvolatile storage device, an access device, and a nonvolatile storage system enable the storage architecture to be changed flexibly for intended use that can be changed variously. A nonvolatile storage system (100) sets a temporary area (23) and a normal access area of a nonvolatile memory (22) based on a use condition designated by a use condition designation unit (11) of an access device (1). This structure enables the nonvolatile storage system (100) to change the temporary area (23) and the normal access area (24) to be prepared in the nonvolatile memory (22) by changing the use condition in accordance with intended use. In other words, the nonvolatile storage system (100) enables the storage architecture to be changed flexibly for intended use that can be changed variously.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakanishi, Takashi Ogasawara
  • Publication number: 20130054923
    Abstract: Memory leak detection can be automated by assigning and recording an increasing sequence number to each memory allocation requested by an action. Call stacks associated with the action are also recorded. Several repetitions of the action can be executed. Allocations that occur in each action and that have similar or matching callstacks are defined as leaks. Allocations that do not have matches can be ignored.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Benjamin W. Bradley, Calvin Hsia
  • Publication number: 20130054926
    Abstract: The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: MICROSOFT CORPORATION
    Inventor: Calvin Hsia
  • Patent number: 8356134
    Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: January 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Ito, Hidetaka Tsuji
  • Publication number: 20130007403
    Abstract: A computing system determines whether memory data pertaining to a block of dynamically allocated memory within an inferior process memory space satisfies one or more criteria in heuristics data. The computing system identifies a category to assign to the block of dynamically allocated memory based on the determination of whether the memory data satisfies the criteria and generates a reliability score for the block of dynamically allocated memory indicating a level of reliability of the identified category. The computing system categorizes the block of dynamically allocated memory based on a comparison of the reliability score and a previous reliability score of the block of the dynamically allocated memory.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventor: David Hugh Malcolm
  • Publication number: 20120317388
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Charles W. Gainey, JR., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • Patent number: 8332611
    Abstract: The present invention relates to methods for managing memory. More particularly, but not exclusively, the present invention relates to methods for managing memory across a plurality of partitions. A first method is disclosed which allocates memory across a plurality of partitions and includes the steps of: establishing a pool of free memory 27; allocating some of the free memory 30 to a target partition when required; identifying memory 40 within one or more source partitions to replace the allocated free memory; cleaning 42 the identified memory; and adding the cleaned memory to the pool 50. A second method for allocating memory across a plurality of partitions is also disclosed.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: December 11, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Muppirala Kishore Kumar
  • Patent number: 8321638
    Abstract: System, method and computer program product for allocating physical memory to processes. The method includes enabling a kernel to free memory in a physical memory space corresponding to arbitrarily sized memory allocations released by processes or applications in a virtual memory space. After freeing the memory, the system determines whether freed physical memory in the physical memory space spans one or more fixed size memory units (e.g., page frames). The method further includes designating a status of the one or more page frames as available for reuse; the freed page frames marked as available for reuse being available for backing a new process without requiring the kernel to delete data included in the freed memory released by the process.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: November 27, 2012
    Assignee: Red Hat, Inc.
    Inventors: Henri Han van Riel, Adriaan DM van de Ven
  • Patent number: 8281103
    Abstract: A method and apparatus for allocating storage addresses are disclosed. The method includes: receiving a storage address allocation request; searching a level-2 bitmap in a hierarchical bitmap in bidirectional mode; outputting an idle bit according to the result of searching in the level-2 bitmap; obtaining a storage address according to the output idle bit, and allocating the storage address. The apparatus includes: a first receiving module, configured to receive a storage address allocation request; a first searching module, configured to search a level-2 bitmap in a hierarchical bitmap in bidirectional mode for an idle bit, wherein the hierarchical bitmap includes N level-1 bitmaps and the level-2 bitmap; and an allocating module, configured to: obtain a storage address according to the output idle bit in the level-2 bitmap, and allocate the obtained storage address.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: October 2, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xinwei Han, Wan Lam, Naidong Ning
  • Patent number: 8214577
    Abstract: A method of memory management includes allocating a portion of a memory as a memory heap including a plurality of segments, each segment having a segment size; performing one or more memory allocations for objects in the memory heap; creating a free list array and class-size array in a metadata section of the memory heap, the class-size array being created such that each element of the size-class array is related a particular one of the plurality of segments and the free list array being created such that each element of the free list array is related to a different size class; and initializing the heap when it is determined that the heap may be destroyed, initializing including clearing the free list array.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Inoue, Hideaki Komatsu
  • Patent number: 8180956
    Abstract: A method controlling a memory card including a nonvolatile semiconductor memory including plural write areas. The method: formats the plural write areas; creates a temporary file entry describing a reserved region size including a free part of the plural write areas and a start position of the reserved region; writes a file in the reserved region from the start position after creating the temporary file entry; when the file has been completely written, determines size of the file written and writes a final file entry describing the start position and file size; when the file has not been completely written, references the temporary file entry to recognize the start position; detects a final position in the reserved region; determines size of the unfinished file using the start position and final position; changes the temporary file entry to a final entry describing the start position and unfinished file size.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 15, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Ito, Hiroyuki Sakamoto
  • Patent number: 8166243
    Abstract: A problem to be solved is to enable the user to read out data stored in a logical unit in a power saving state in a short time in a storage system having a power saving function such as stopping the spindle of the HDD. To solve the problem, candidate document file information is read out according to the keywords inputted by the user from a search system, a predetermined number of document file names are extracted from the highest candidates in the candidate document file information, and the power saving function of the logical units actually storing the extracted document files is controlled (switch the state from the power saving state to the normal operation state).
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: April 24, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Tsunehiro Tobita
  • Patent number: 8145870
    Abstract: The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending said storage map to an application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating a cache map. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating an indication of one or more storage locations that have been allocated to store information for the application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating the storage map in response to receiving a request for the storage map from the application.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Diane Garza Flemming