Abstract: A method for performing data compression in a multi-core processor comprises retrieving a chunk of data from a data array of a cache slice, wherein the cache slice is comprised within a cache associated with the multi-core processor, wherein the cache is distributed between a plurality of cache slices, and wherein each core of the multi-core processor can access each of the plurality of cache slices. The method further comprises calculating a bit mask for the chunk of data and, using the bit mask, shifting out elements in the chunk of data corresponding to zero values, wherein zero value elements in the chunk of data are shifted out and non-zero value elements in the chunk of data are retained. Finally, the method comprises writing the bit mask and the non-zero value elements to a memory.

Abstract: Provided is an image processing method, which includes: determining whether the number of written rows of source image data in a DDR is a preset number of rows or a stop write number of rows, the preset number of rows being an integer multiple of the number of rows of an image block determined according to a compression condition, and the image block being any image block in an image block matrix determined on the basis of an entire frame of image; if yes, reading the source image data of the current image block from the DDR on the basis of a first read address of the current image block, the number of rows, and the number of columns; and performing compression on the source image data of the current image block to obtain compressed data, and writing the compressed data to the DDR.

Abstract: A storage usage management system includes a storage usage management subsystem coupled to first and second storage devices. The storage usage management subsystem collects first write usage data from use of the first storage device by a host mapped to the first storage device, determines that second write usage data from use of the first storage device by the host exceeds first metric(s) associated with the first write usage data by a first threshold, and collects the second write usage data and third write usage data from immediately subsequent use of the first storage device by the host. If the storage usage management subsystem determines that the second and third write usage data exceed second metric(s) associated with the first write usage data by a second threshold, it uses the second and third write usage data to determine whether to remap the host to the second storage device.

Abstract: A method, computer program product, and computer system for identifying, by a computing device, a first amount of storage space reserved by RAID for a RAID rebuild of a failed drive. A second amount of the storage space reserved by a file system may be identified, wherein the storage space may be shared between the RAID and the file system. The RAID rebuild of the failed drive may be performed. The first amount of the storage space may be allocated to the RAID from the second amount of the storage space reserved by the file system.

Abstract: A method for data processing implemented by computer means and comprises: for a plurality of objects of the data processing, conducting an analysis of a computer code of the data processing defining a use of said objects in the data processing, on the basis of the analysis of the computer code (COD), allocating each object to one of a plurality of memory areas for the construction and then the destruction of each object in the corresponding memory area during the data processing, in such a way that, during the data processing, each memory area exhibits stack operation.

Abstract: In order to reduce the number of instructions that the compiler generates to load the address of a global variable into a register, the compiler uses a technique that analyzes the global variables used in each function in order to estimate which global variables will be located within the same memory page and having a common base address. A base global variable is selected for each function whose address is fully resolved. The address of each subsequent global variable is constructed using an offset relative to the address of the base global variable that is based on the subsequent global variable's position in a global variable order list.

Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface.

Abstract: In one embodiment, a search engine may generate and store a plurality of search index segments such that each of the search index segments is stored in a corresponding one of a plurality of heaps of memory. The plurality of search index segments may include inverted index segments mapping content to documents containing the content. A garbage collection module may release one or more heaps of the memory.

Abstract: Techniques and methods for generating and implementing multiple layers of redundancy coded data are disclosed. For example, a redundancy coding scheme may include data elements that include data that is unencoded relative to the input, yet may still fully participate in providing redundancy to any data element in a given set. In a layered scheme, the input may include a bundle or group of encoded (or unencoded) data elements, thereby nesting two or more layers of redundancy coding. The specific amount of redundancy generated by such a scheme may be adjusted and adapted to failure characteristics of the entity on which the data elements are stored.

Abstract: Provided are techniques for identification and handling of nested breakpoints during debug session. In a visualization, program code having functions, nested breakpoints, and an indication of whether each of the breakpoints is likely to be reached is displayed. In response to receiving input that selects a function from the functions, a call graph is displayed for the functions in the program code to enable viewing where each of the nested breakpoints is located in the program code with reference to the functions. An option to disable a nested breakpoint of the nested breakpoints for a current execution of the program code is provided. In response to receiving input that selects the option, the nested breakpoint is disabled.

Abstract: Methods and computer-readable media are disclosed herein for generating asynchronous runtime compatible applications from non-asynchronous applications. In embodiments, source code for the application that is not compatible with asynchronous processing is examined. The source code is parsed in order to identify unsafe functions that will cause failures of the application when processed in an asynchronous runtime. The source code corresponding to those unsafe functions is modified by adding asynchronous functions and commands to the source code and restructuring the source code. The modified source code may then be provided to an asynchronous runtime environment as the application is now compatible with asynchronous processing.

Abstract: The present invention discloses a process management method and apparatus, and pertains to the field of computer technologies. The method includes: obtaining benchmark duration for interface switching; determining, after interface switching, switching duration of the interface switching; and stopping, according to a preset process priority, a process having a lower priority, if the switching duration is longer than the benchmark duration, and a difference between the switching duration and the benchmark duration is greater than a preset threshold. By means of the present invention, process management efficiency can be improved.

Abstract: A compiler and library provide the ability to compile a programming language according to a defined language model into a programming language independent, machine independent intermediate representation, for conversion into an executable on a target programmable device. The language model allows writing programs that perform data-parallel graphics and non-graphics tasks.

Abstract: A method, apparatus, and computer program product for optimizing software are provided. The software includes a plurality of modules which include at least one controllable module, the method comprises: determining a shared symbol defined by the at least one controllable module, the shared symbol being a symbol used by two or more modules of the software; generating a symbol use file indicating the shared symbol defined by the at least one controllable module; and rebuilding the software based on the symbol use file, so that a symbol table in a controllable module of the rebuilt software only contains the shared symbol indicated in the symbol use file. A number of symbols in the symbol table can be reduced accurately and effectively, thereby time needed for loading the symbol table can be reduced and software execution efficiency can be improved.

Abstract: A high level programming language provides a nested communication operator that partitions a computational space. An indexable type with a rank and element type defines the computational space. The nested communication operator partitions a specified dimension of an index indexable type into segments specified by a segmentation vector and returns an output indexable type that represents the segments. By doing so, the nested communication operator allows data parallel algorithms to operate on the segments as individual units.

Abstract: Methods, systems, and computer readable media for balancing incoming connections across multiple cores are disclosed. According to one method, the method occurs at a first processor of a multi-core connection server. The first processor is one of multiple processors of the multi-core connection server configured to receive notification of incoming connection requests associated with a socket and to request the connection requests from a queue. The method includes accepting a first connection request from a queue. The method also includes determining whether a connection quota has been reached. The method further includes in response to determining that the connection quota has been reached, performing an appropriate action based on state information associated with other processors.

Abstract: Systems and methods for a compiler with type inference is described herein. The compiler includes a computer program having one or more variables and context of the variables. The compiler has a type selector to infer a type of the variable using the context of the variable and dereference the variable using the inferred type. Prior to executing the computer program, the compiler carries out a type check of the variable by accessing a recommended type of the variable and comparing the recommended type and the types associated with the context of the variable.

Abstract: Provided are techniques for identification and handling of nested breakpoints during debug session. Program code having functions, nested breakpoints, and an indication of whether each of the breakpoints is likely to be reached is displayed, in a visualization. In response to receiving input that selects a function from the functions, a call graph is displayed for the functions in the program code to enable viewing where each of the nested breakpoints is located in the program code with reference to the functions. An option to disable a nested breakpoint of the nested breakpoints for a current execution of the program code is provided. In response to receiving input that selects the option, the nested breakpoint is disabled.

Abstract: An example system for compiling a source file includes an optimizer that identifies a segment of code in a first source file as a potential optimization opportunity. The first source file includes high-level source code. The example system also includes a compiler that identifies a compilation record storing data indicating that the segment of code is an actual optimization opportunity and generates a representation of the high-level source code in accordance with the actual optimization opportunity. The data is based on a previous compilation of a second source file.

Abstract: A method, apparatus, and computer program product to improve testing of web interfaces where each page and point of interaction in the web interfaces are represented by Page Objects. Responsive to a processor receiving code to navigate a path from a first Page Object to a second Page Object in the user interface, the path is identified as a slow path. Responsive to identifying the path as a slow path, a marker is displayed with the code.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying source code used to build executable. One of the methods includes determining that a first newly created process is a compiler, the compiler being invoked to compile a source code file; after the compiler exits, generating a first hash value of an object file generated by the compiler; generating an object artifact that identifies the source code file and includes the first hash value of contents of the object file generated by the compiler; determining that the second newly created process is a linker, the linker being invoked to generate an executable file from one or more object files; generating a link artifact that includes respective hash values of each of the one or more object files used to generate the executable file; and providing the link artifact and object artifact to a static analysis system.

Abstract: A method and programming system for programming an automation component of an industrial automation arrangement, the automation component being provided with at least one special main memory, such as a cache or a tightly coupled memory, with faster access, wherein a user is provided with an input option for assigning priority values to individual tasks of the automation program when creating the program, all of those program parts which are called when executing at least the task with the highest priority assigned by the user are automatically identified, and the identified program parts being permanently storable in the special main memory such that important program parts and routines are executable in a reproducible manner at high execution speed and with a short latency time.

Abstract: A computer implemented method of refactoring software code to optimize execution performance by consolidating shared resources accesses, comprising: receiving target code containing code entries accessing shared resource(s); automatically creating a dependency record for each shared resource. The dependency record describes dependencies among the code entries accessing shared data items in the shared resource(s); identifying, based on the dependency record, a resource access point for each shared resource(s), wherein the resource access point is located in an execution path of the target code to precede code entries which use the shared data item(s) and follows code entries which define the shared data item(s); automatically refactoring the target code to group together code entries which use the shared data item(s), wherein the group is placed following the resource access point to consolidate shared resource accesses of the code entries to the shared resource(s); and outputting the refactored target code.

Abstract: Examples are described for a device to receive intermediate code that was generated from compiling source code of an application. The intermediate code includes information generated from the compiling that identifies a hierarchical structure of lower level sub-routines in higher level sub-routines, and the lower level sub-routines are defined in the source code of the application to execute more frequently than the higher level sub-routines that identify the lower level sub-routines. The device is configured to compile the intermediate code to generate object code based on the information that identifies lower level sub-routines in higher level sub-routines, and store the object code.

Abstract: The conventional debugger tool used to debug the Embedded System is limited to JTAG as the standard physical interface and also to specific processor. The commercial debuggers are limited to specific Operating System of the Host machine where the symbol information is being viewed. The Dynamic and Global In-system debugger provides the replacement for the typical debugger still providing the symbol information details in the Embedded System. The debugger is OS agnostic, interface agnostic, processor agnostic and compiler agnostic with optimized algorithm in the extraction of Global symbols from the Executable Binary. The Executable Binary may be encrypted to keep it more secured and Global and In-system debugger decodes the same.

Abstract: A request management subsystem is configured to establish service classes for clients that issue requests for a shared resource on a computer system. The subsystem also is configured to determine the state of the system with respect to bandwidth, current latency, frequency and voltage levels, among other characteristics. Further, the subsystem is configured to evaluate the requirements of each client with respect to latency sensitivity and required bandwidth, among other characteristics. Finally, the subsystem is configured to schedule access to shared resources, based on the priority class of each client, the demands of the application, and the state of the system. With this approach, the subsystem may enable all clients to perform optimally or, alternatively, may cause all clients to experience an equal reduction in performance.

Abstract: A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.

Abstract: Embodiments include method, systems and computer program products for identifying dependency relationships in a software product. Aspects include obtaining change history data for the software product and extracting a plurality of change elements from the change history data, each change element including an identifier of a code segment that was changed and a timestamp of the change. Aspects also include creating a dependency graph based on the plurality of change elements, wherein the dependency graph includes nodes that correspond to the code segments and edges that connect nodes that were both updated in a same logical grouping, calculating a weight for each of the edges based on probability that the nodes connected by the edge will be updated together, and outputting the dependency graph.

Abstract: A view of data transformation jobs can be presented by way of a user interface. Related jobs can subsequently be identified automatically after a job is selected based on data dependencies between jobs. Execution status can also be determined and presented such that successful and failed execution of jobs, for example, can be differentiated. Furthermore, selection of a job run that failed to execute successfully can trigger identification of related jobs runs that failed or are predicted to fail to execute successfully.

Abstract: A method and computer program product for building a multiple layer object-oriented software application with reusable components. The method includes creating business classes containing a business logic for the software application, wherein the business classes are organized into hierarchies identified as namespaces, and then generating executable programming code for the software application. From there, the method may include placing the executable programming code into an at least one assembly structure for an associated layer, wherein a security token is required to access the business classes, and wherein the business classes are created to validate each security token passed by a user interface.

Abstract: A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation.

Abstract: Exemplary embodiments enable debugging executable code using a debugger in a computational device that provides a programming environment including a presentation layer. For example, an exemplary method includes providing a first marshalling function that receives a portion of information manipulated by the executable code and produces a presentation layer representation of the portion of the information. The presentation layer representation is compatible with a debugger that debugs the executable code. An exemplary method also includes debugging the executable code to produce a presentation layer representation of the portion of the information with the first marshalling function so as to display the presentation layer representation of the portion of the information to a user via a display device. The debugging also includes modifying the presentation layer representation of the portion of the information to produce modified information for use by the executable code, a device, or a user.

Abstract: A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction, and/or re-ordering of objects within a heap. One or more of these management tasks improve system performance by limiting movement of pages in and out of virtual memory. The garbage collection technique selectively performs garbage collection such that certain objects, such as old but live, infrequently referenced objects, are not garbage collected each time garbage collection is performed.

Abstract: Instructions grouped into instruction groups are optimized across group boundaries. Instruction sequences spanning multiple groups are optimized by retaining information relating to an instruction at the end of one instruction group to be co-optimized with an instruction at the beginning of a subsequent instruction group. This retained information is then used in optimization of one or more instructions of the subsequent group. Optimization may be performed across n group boundaries, where n is equal to two or greater. Additionally, optimization of instructions within a group may be performed, in addition to the optimizations across group boundaries.

Abstract: A system for updating an index into a tuple table of tuples is provided. An indexing system updates an index into a tuple table using fine-grain locking of the index. The index includes a values table with an entry for each index value of an index field that references a value-tuple table that includes, for each tuple with the index value, a row that identifies a tuple of the tuple table with that indexed value. After a new tuple is added to the tuple table with a value, the index is updated by locking the entry in the values table, updating the value-tuple table for the value, and then unlocking the entry. When the index is accessed for locating tuples with a value, the accessor locks the entry in the values table for the value, uses the value-tuple table to locate the tuples, and unlocks the entry.

Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester.

Abstract: A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment are defined. Configuring a separate environment may include specifying a physical memory usage cap for the separate environment. A global resource capping background service enforces physical memory caps on any separate environments that have specified physical memory caps.

Abstract: Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.

Abstract: A network device allocates a particular number of memory blocks in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and creates a list of additional memory blocks in an external TCAM of the network device. The network device also receives, by the external TCAM, a request for an additional memory block to provide one or more rules from one of the multiple databases, and allocates, by the external TCAM and to the requesting database, an additional memory block from the list of additional memory blocks.

Abstract: A method, apparatus and computer program product for an external, self-initializing FIFO containing indexes of free CAM memory locations is presented. When data is sent to the CAM for a lookup, this external FIFO provides the CAM with the index of a free memory location within the CAM so that if the data word is not found in the CAM (i.e. a CAM miss), the data can be written to the designated available free entry in the CAM. Thus, if the same data word is searched in the CAM in the following cycle it will result in a hit.

Abstract: Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager. The power savings manager may also be configured to determine whether physical memory blocks should be active or inactive. Furthermore, the memory management system may include a driver configured to activate or deactivate a memory block in response to a system call from the power savings manager.

Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).

Abstract: Exemplary embodiments for storing data by a processor device in a computing environment are provided. In one embodiment, by way of example only, from a plurality of available data segments, a data segment having a storage activity lower than a predetermined threshold is identified as a colder data segment. A chunk of storage is located to which the colder data segment is assigned. The colder data segment is compressed. The colder data segment is migrated to the chunk of storage. A status of the chunk of storage is maintained in a compression data segment bitmap.

Abstract: A method, computer program product, and computing system for receiving a read request on a first cache system, wherein the read request identifies previously-written content included within a data array. If the previously-written content identified in the read request is stored within the first cache system in a compressed format, and the previously-written content identified in the read request is stored within the data array in an uncompressed format; a determination is made as to if it is less computationally expensive to obtain from the data array the previously-written content in an uncompressed format.

Abstract: Exemplary system and computer program embodiments for storing data by a processor device in a computing environment are provided. In one embodiment, by way of example only, from a plurality of available data segments, a data segment having a storage activity lower than a predetermined threshold is identified as a colder data segment. A chunk of storage is located to which the colder data segment is assigned. The colder data segment is compressed. The colder data segment is migrated to the chunk of storage. A status of the chunk of storage is maintained in a compression data segment bitmap.

Abstract: A computing system determines whether memory data pertaining to a block of dynamically allocated memory within an inferior process memory space satisfies one or more criteria in heuristics data. The computing system identifies a category to assign to the block of dynamically allocated memory based on the determination of whether the memory data satisfies the criteria and generates a reliability score for the block of dynamically allocated memory indicating a level of reliability of the identified category. The computing system categorizes the block of dynamically allocated memory based on a comparison of the reliability score and a previous reliability score of the block of the dynamically allocated memory.

Abstract: A data management method includes determining the size of input data, storing the input data in a log block if the size of the input data is determined to be a write unit, and storing the input data in a partial block if the size of the input data is determined to be smaller than the write unit. The log block is a temporary block storing data of same addresses and the partial block is a temporary block storing data regardless of their addresses. The memory system includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The memory controller is configured to temporarily store input data smaller than a write unit in a selected memory block even when the input data have different addresses.

Abstract: Described in detail herein are systems and methods for single instancing blocks of data in a data storage system. For example, the data storage system may include multiple computing devices (e.g., client computing devices) that store primary data. The data storage system may also include a secondary storage computing device, a single instance database, and one or more storage devices that store copies of the primary data (e.g., secondary copies, tertiary copies, etc.). The secondary storage computing device receives blocks of data from the computing devices and accesses the single instance database to determine whether the blocks of data are unique (meaning that no instances of the blocks of data are stored on the storage devices). If a block of data is unique, the single instance database stores it on a storage device. If not, the secondary storage computing device can avoid storing the block of data on the storage devices.

Abstract: A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.

Abstract: A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section.