For Peripheral Storage Systems, E.g., Disc Cache, Etc. (epo) Patents (Class 711/E12.019)
  • Patent number: 12032499
    Abstract: A hybrid printed circuit board (PCB) topology is provided. A non-volatile storage system may include a PCB, a first non-volatile storage device attached to a first side of the PCB, a second non-volatile storage device attached to a second side of the PCB, and a storage controller coupled to the first and second non-volatile storage devices by a shared channel. The two devices may be placed in a clamshell configuration but have different capacities. The shared channel may have a first signal route to a first pin of the first non-volatile storage device and a second signal route to a second pin of the second non-volatile storage device. The first pin may have a pin capacitance that is smaller than that of the second pin. The first signal route has an extra resistor in series compared to the second signal route.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: July 9, 2024
    Assignee: InnoGrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Lin Chen
  • Patent number: 12026129
    Abstract: Systems and methods for caching file system collections atomically. The systems and methods perform operations comprising: receiving a request to access a collection of data comprising a plurality of files stored on a storage device; in response to receiving the request, transferring the collection of data from the storage device to a first subfolder in a cache associated with the storage device; generating a lock file comprising a reference to the first subfolder in the cache; and atomically controlling access to the collection of data in the first subfolder and removal of the collection of data in the first subfolder from the cache via the lock file.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 2, 2024
    Assignee: Snowflake Inc.
    Inventors: Selcuk Aya, Ju-yi Kuo, Jonathan Lee Leang, Nitya Kumar Sharma, Igor Zinkovsky
  • Patent number: 12019872
    Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: June 25, 2024
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 12003384
    Abstract: According to one example embodiment, a method may include receiving, by a repository entity, first information on data related to a network entity. The method may further include storing, by the repository entity, second information related to the network entity based on the first information. The second information may include at least one of an identifier of the network entity and an identifier of a data acquiring entity having acquired the data.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: June 4, 2024
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Yannick Lair, Anja Jerichow, Laurent Thiebaut
  • Patent number: 11989449
    Abstract: A method of performing a full data reconstruction in a redundant array of independent disks (RAID) system with a protection pool of storage units includes determining that a physical disk of a storage cluster has been removed from service. The physical disk includes a set of physical extents and at least one physical extent of the set of physical extents is associated with an array of physical extents distributed across physical disks of the storage cluster. The method further includes transmitting a message to one or more array groups of the physical disks, to allocate replacement physical extents and assign the replacement physical extents to the array of physical extents and initiating reconstruction of data from the set of physical extents of the physical disk to the replacement physical extents.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 21, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Paul Nehse, Michael B. Thiels, Devendra V. Kulkarni
  • Patent number: 11983436
    Abstract: A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: May 14, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngsuk Moon, Jaegeun Park, Jongin Lee, Sangmuk Hwang
  • Patent number: 11977759
    Abstract: A method for operating a cache memory having a set having multiple memory blocks configured for storing data blocks. In a write process of a data block into a memory block of the set, the data block is written into the memory block, a relevance rank value of the data block and a first access time rank value are determined. Rank data associated with the memory block are determined using a write rank mapping from the relevance rank value and the first access time rank value, and the determined rank data are stored. If no memory block of the set is free, a memory block that is to be overwritten is selected from the memory blocks of the set based on the rank data, which are associated with the memory blocks, and the data block to be stored is written into the selected memory block by using the write process.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: May 7, 2024
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arne Hamann, Dakshina Narahari Dasari, Dirk Ziegenbein, Falk Rehm, Michael Pressler
  • Patent number: 11977778
    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry, Lakshmi Kalpana Vakati
  • Patent number: 11973815
    Abstract: Network assistance is provided for the streaming of data from a user equipment (UE) (14) to an ingestion point (12) in a network. The network assistance may include establishing an uplink network assistance (UNA) session with a network assistance service of the network; while streaming of the data and for each segment of the data or each UNA period of the data, receiving from the network assistance service an indication of a recommended highest bit rate estimate with which the data may be streamed under current network conditions. The UE may adjust content of the data stream in accordance with the indication of the recommended highest bit rate estimation.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 30, 2024
    Assignee: Sony Group Corporation
    Inventors: Paul Szucs, Rickard Ljung
  • Patent number: 11966581
    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Manu Awasthi, Robert Brennan
  • Patent number: 11960448
    Abstract: Techniques are provided for implementing a unified object format. The unified object format is used to format data in a performance tier (e.g., infrequently accessed data, snapshot data, etc.) into objects that are stored into an object store for low cost, scalable, long term storage compared to storage of the performance tier. With the unified object format, compression of the data may be retained when the data is stored as the objects into the object store. Additional compression may also be provided for the data in the objects. The unified object format includes slot header metadata used to track the location of the data within the object notwithstanding the data being compressed and/or stored at non-fixed boundaries. The slot header metadata may be cached at the performance tier for improved read performance and may be repaired by a repair subsystem (a slot header repair subsystem).
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 16, 2024
    Assignee: NetApp, Inc.
    Inventors: Palak Sharma, Dibyasri Nandi, Sindhushree K N, Cheryl Marie Thompson, Qinghua Zheng, Venkateswarlu Tella, Debanjan Paul, Dinakaran Narayanan
  • Patent number: 11947418
    Abstract: A computer system and a method implementing a remote access array are provided. A first drawer includes a first processor chip. A first main memory region is operatively connected to the first processor chip. A first non-addressable memory region is operatively connected to the first processor chip and includes the first remote access array. The first remote access array is configured to track data portions that are stored in the first main memory region and for which copies were created and sent to an external node. The first remote access array is backed up in the first main memory region. The first remote access array includes one or more entries and is configured to update all of the entries in response to a multi-drawer working partition being reduced to fit within the first drawer.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ram Sai Manoj Bamdhamravuri, Robert J Sonnelitter, III, Ulrich Mayer, Chad G. Wilson, Avery Francois
  • Patent number: 11941257
    Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Futurewei Technologies, Inc.
    Inventor: Yiren Huang
  • Patent number: 11943296
    Abstract: An example method may include receiving, in a virtualized execution environment, a data access request from a storage system, identifying, in view of a virtualized execution image associated with the virtualized execution environment, an application running in the virtualized execution environment, generating a cache classification that specifies whether data accessed by the application is suitable for cache compression, including, in the data access request, a tag indicating whether cached data is to be accessed in a compressed-memory cache, wherein the tag is determined in view of the cache classification, and sending, to a server of the storage system, the data access request. The application can be identified in view of metadata included in the virtualized execution image, where the metadata comprises one or more of an application name or an application version.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 26, 2024
    Assignee: Red Hat, Inc.
    Inventors: Gabriel Zvi BenHanokh, Orit Wasserman, Yehoshua Salomon
  • Patent number: 11914517
    Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 27, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
  • Patent number: 11914519
    Abstract: Aspects described herein relate to a method comprising: receiving a request to write data to a persistent storage device, the request comprising data; determining an affinity of the data; writing the request to a cache line of a cache; associating the cache line with the affinity of the data; and reporting the data as having been written to the persistent storage device.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Nyriad, Inc.
    Inventors: Stuart John Inglis, Cameron Ray Simmonds, Dmitry Lapik, Chia-Chi Hsu, Daniel James Nicholas Stokes, Adam Gworn Kit Fleming
  • Patent number: 11907156
    Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: February 20, 2024
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics France
    Inventors: Michael Soulie, Thomas Martin
  • Patent number: 11899630
    Abstract: A method, computer program product, and computer system for controlling, by a computing device, access to a non-volatile memory using a non-volatile lock as a reader of the non-volatile memory. Metadata (MD) non-volatile memory commits may be throttled until capacity of the non-volatile memory is at a threshold capacity.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: February 13, 2024
    Assignee: EMC IP Holding Company, LLC
    Inventors: Ami Sabo, Vladimir Shveidel, Dror Zalstein
  • Patent number: 11899591
    Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: February 13, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Cagdas Dirik, Robert M. Walker
  • Patent number: 11861224
    Abstract: The present disclosure generally relates to efficient data transfer. Rather than processing each command, the data storage device fetches part of the host buffers and then makes a determination regarding the attributes of the fetched buffers. Upon the determination, the command is classified as optimized, not-optimized, or somewhere in between. Optimized commands are permitted to retrieve data out of order while non-optimized commands remain in a strict in order data retrieval process. In between commands can be processed with some out of order data retrieval. In so doing, data transfers are effectively managed and optimized data by taking into account the current attributes of the host buffers per command.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11861326
    Abstract: An example method of flow control between remote hosts and a target system over a front-end fabric, the target system including a nonvolatile memory (NVM) subsystem coupled to a back end fabric having a different transport than the front-end fabric is described. The method includes receiving commands from the remote hosts at a controller in the target system for the NVM subsystem. The method further includes storing the commands in a first-in-first-out (FIFO) shared among the remote hosts and implemented in memory of the target system. The method further includes updating virtual submission queues for the remote hosts based on the commands stored in the FIFO. The method further includes providing the commands to the NVM subsystem from the FIFO.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 2, 2024
    Assignee: XILINX, INC.
    Inventors: Santosh Singh, Deboleena M. Sakalley, Ramesh R. Subramanian, Pankaj V. Kumbhare, Ravi K. Boddu
  • Patent number: 11853424
    Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: December 26, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan
  • Patent number: 11842073
    Abstract: The present disclosure relates to a memory controller and a method of operating the memory controller. The memory controller controlling a memory device including a plurality of planes includes a central processing unit (CPU) generating a command corresponding to a request from a host, a command queue storing the command, counter logic assigning to the command, number information corresponding to an order in which the command is generated and flag information indicating a level at which an operation corresponding to the command is performed, and a command queue controller controlling the command queue to transfer the command stored in the command queue to one of the plurality of planes corresponding to the command on the basis of the number information and the flag information.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventor: Min Hwan Moon
  • Patent number: 11822798
    Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: November 21, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang
  • Patent number: 11809560
    Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: November 7, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan
  • Patent number: 11809729
    Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kulachet Tanpairoj, Jianmin Huang, Kishore Kumar Muchherla
  • Patent number: 11797570
    Abstract: A computer-implemented method for a crash recovery for linked databases may be provided. The linked databases comprise a source and related target database. Selected queries of the source database are transferred to the target database. The method comprises synchronizing selected portions of the source database with tables of an in-memory portion of target database and, storing persistently applied changes to the in-memory target database portion asynchronously and persistently. Upon a database crash of the target database system, the method also comprises restoring, the in-memory target database portion with the latest snapshot available, and applying, changes from the source database recovery log file that have a later timestamp than the latest snapshot available in the persistent target database storage of the in-memory target database portion.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: October 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Felix Beier, Dennis Butterstein, Einar Lueck, Sabine Perathoner-Tschaffler
  • Patent number: 11797209
    Abstract: Example implementations described herein are directed to a method and a system for storage allocation from a storage pool, the method involving, for receipt of a request for storage through an orchestrator communicatively coupled to a management system managing the storage pool, the request comprising user information and request characteristics information, the request characteristics information indicative of a use type for the request, determining a storage tier from the storage pool for the request based on the user information and the request characteristics information; and allocating a pool name and the storage tier in response to the request.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: October 24, 2023
    Assignee: HITACHI, LTD.
    Inventor: Hiroyuki Osaki
  • Patent number: 11789632
    Abstract: In a storage system including a first tier and a second tier a method includes: storing access statistics per object; obtaining a request to perform a write operation; calculating a recency factor to the first object based on the access statistics; and writing the first object to one of the first tier and the second tier, depending on the recency factor. Performing garbage collection process on the second tier may include: reading metadata of an object stored in the second tier; determining whether the object is valid based on the metadata; if the object is invalid, discarding the object; and if the second object is valid: calculating a recency factor for the object based on the access statistics of the object; and moving the object to the first tier or leaving the object in the second tier, depending on the recency factor of the second object.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: October 17, 2023
    Assignee: LIGHTBITS LABS LTD.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Ofer Hayut, Eran Kirzner, Alexander Shpiner, Roy Shterman, Maor Vanmak
  • Patent number: 11775210
    Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Narendhiran Chinnaanangur Ravimohan, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy
  • Patent number: 11762999
    Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: September 19, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan
  • Patent number: 11755489
    Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 12, 2023
    Assignee: Apple Inc.
    Inventors: Rohit K. Gupta, Rohit Natarajan, Jurgen M. Schulz, Harshavardhan Kaushikkar, Connie W. Cheung
  • Patent number: 11757838
    Abstract: Disclosed herein are enhancements for operating a web application firewall to reduce load. In one implementation, a method of operating a content server for a web application comprising running a web accelerator with a plurality of threads on the content server. The method further provides receiving a request for content which will be provided to a web application, filtering the request and determining that the content will be requested from a second server. After determining that the content will be requested from a second server, reviewing the request with a web application firewall operating at a network layer 7, forwarding the request, receiving the content, and providing the content. Further, the web application firewall is controlled by a plurality of sets of rules, which can be updated without restarting the web accelerator.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: September 12, 2023
    Assignee: Fastly, Inc.
    Inventors: Artur Bergman, Sean Leach, Tyler McMullen, Christian Peron, Federico Schwindt, Eric Hodel
  • Patent number: 11748279
    Abstract: A system on chip, an access command routing method, and a terminal are disclosed. The system on chip includes an IP core and a bus. The IP core is configured to: obtain, based on an access address corresponding to an access command, an address range configuration identifier corresponding to the access address; and transmit the access command and the address range configuration identifier to the bus, where the address range configuration identifier is used by the bus to route the access command. The bus is configured to route the access command to a system cache or an external memory based on the address range configuration identifier.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: September 5, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shiming He, Bo Sun, Wenmin Zhou, Zhiqiang Zhang
  • Patent number: 11743359
    Abstract: The present invention discloses a service caching method for a cross-border service network, wherein the method includes: a cache space of a service switch node is divided into a resident area, a change area, a pre-reclaimed area and a maintenance index area; among them, a cache hit frequency is: a resident area>a change area>a pre-reclaimed area, and the maintenance index area is used for separate storage services call path. when a service call is generated, a cache content in the cache space is replaced according to a cache value of a missed cache or a hit cache; a service router and service switch nodes in the corresponding area jointly form a hierarchical cache mode. When the cache space of any node in the service switch node is insufficient, the service switch nodes in the same area perform collaborative cache and store them in other cache space of the service switch node through indexing.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: August 29, 2023
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Jianwei Yin, Bangpeng Zheng, Shuiguang Deng, Huan Zhang, Shengye Pang, Yucheng Guo, Maolin Zhang
  • Patent number: 11740983
    Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: August 29, 2023
    Assignee: VMware, Inc.
    Inventors: Pratap Subrahmanyam, Rajesh Venkatasubramanian, Kiran Tati, Qasim Ali
  • Patent number: 11714566
    Abstract: A tiering service enables a client to custom specify service level agreements for data items to be tiered and automatically promotes and demotes the data items amongst a warm tier, a plurality of intermediate tiers, and a cold tier to ensure the service level agreement commitments are met. In some embodiments, a client specifies segmentation criteria for defining multiple segments of data items included in a data scope or table and assigns latency targets to the segments in order to define the service level agreement. Also, in some embodiments, a plurality of intermediate tiers are implemented on common underlying hardware by varying metadata management to implement intermediate tiers that have progressively increasing latencies.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: August 1, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Binu Kuttikkattu Idicula, Nagarathan M, Akshi Raina, Jaya Talreja
  • Patent number: 11698756
    Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Patrick A. La Fratta
  • Patent number: 11698752
    Abstract: A method and system for retransmitting messages in a memory subsystem are described. A message is transmitted to a host system. A response message is expected to be received from the host system in response to the message. A determination that the response message was not received prior to detecting an indication of a processing of a number of commands from the host system is performed. The message is retransmitted to the host system in response to the determination.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 11, 2023
    Assignee: MICRON TEHCNOLOGY, INC.
    Inventor: Binbin Huo
  • Patent number: 11670385
    Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 6, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fran├žois Tailliet, Chama Ameziane El Hassani
  • Patent number: 11669247
    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 6, 2023
    Inventors: Manu Awasthi, Robert Brennan
  • Patent number: 11663174
    Abstract: A manager file system (MFS) runs as a user space file system. The MFS, implemented using an OS process, exposes a mount point as a communication endpoint to the single process. Mounting, unmounting, and changing configuration of individual database file systems (DBFSs) are done by overloading extended attributes on the mount point. The MFS services all DBFSs mounted at different mount points registered to the single process of the MFS and ensures optimal resource utilization among the DBFSs in the single process while guaranteeing resource isolation. Multiple MFSs may be created to manage sets of DBFSs.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: May 30, 2023
    Assignee: Oracle International Corporation
    Inventors: Parthasarathy Elangadu Raghunathan, Shishir Mathur, Shubha Bose, Aurosish Mishra
  • Patent number: 11650843
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
  • Patent number: 11640239
    Abstract: Cost conscious garbage collection, including: selecting one or more storage classes from among a plurality of storage classes of one or more data storage services for storing one or more data objects; determining, for the one or more data objects stored in the one or more data storage services, an estimated quantity of data eligible for garbage collection; and initiating, after determining that resources for continued storage of the one or more data objects exceed resources for performing garbage collection on the data eligible for garbage collection and based upon an expected cost savings based on storage cost savings from performing garbage collection compared against access cost expenses for performing one or more cloud-based operations to perform the garbage collection, garbage collection on the one or more data objects in the one or more data storage services.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 2, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Dirk Meister, Subramaniam Periyagaram, Reese Robertson, Prudhvi Lokireddy
  • Patent number: 11636114
    Abstract: The subject technology receives first metadata corresponding to a set of micro-partitions. The subject technology stores a first data structure and a second data structure in storage as a first file and a second file, first data structure including the first metadata and a second data structure including second metadata, the first metadata corresponding to a set of micro-partitions, the second metadata for a grouping of the first metadata, the second data structure including information associating the second metadata to the first metadata. The subject technology stores third metadata for a table, the third metadata comprising information about data stored in a micro-partition of the table.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: April 25, 2023
    Assignee: Snowflake Inc.
    Inventors: Benoit Dageville, Yi Fang, Martin Hentschel, Ashish Motivala, Spyridon Triantafyllis, Yizhi Zhu
  • Patent number: 11637944
    Abstract: An image processing apparatus comprises a generation unit configured to generate, based on print data, pieces of information to be used for generating intermediate data based on the print data, and store the pieces of information in an external storage device connected to the image processing apparatus, and a rendering unit configured to generate the intermediate data using the pieces of information, and generate a raster image by performing rendering based on the generated intermediate data.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 25, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takashi Miyanomae
  • Patent number: 11636041
    Abstract: A system includes memory and one or more processors programmed to operate a logical layer, a media link layer, and a slot layer. The logical layer is configured to send and receive object data to a host according to an object storage protocol. The media link layer is configured to map the object data to virtual media addresses. The slot layer is configured to map the virtual media addresses to physical addresses of data storage devices.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: April 25, 2023
    Assignee: Seagate Technology LLC
    Inventors: Deepak Nayak, Hemant Mohan
  • Patent number: 11630656
    Abstract: A communication apparatus includes: a memory that stores, first data on firmware before update, second data on firmware after the update, and a table in which the first data or the second data is associated with an address where the first data or the second data is positioned; and a processor that executes processing based on the first data or the second data positioned at the address defined in the table.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 18, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Takumi Harada, Manabu Yoshino, Junichi Kani
  • Patent number: 11625189
    Abstract: Storage devices can be configured to utilize one or more memory buffers located within a host-computing device. These host buffers may allow for faster access to some data, including control pages. However, host buffers are susceptible to fragmentation issues similarly to standard user memory arrays. As the data stored within the host buffers becomes more fragmented, performance can suffer. This performance loss in storage devices becomes more pronounced as the desired performance levels of these storage devices increase. Therefore, various methods and systems described herein manage fragmentation within host buffers by conducting one or more operations. These operations may include locating a continuous portion of allocated or unallocated memory within the host buffer and either swap or copy high-usage or high-priority data to those continuous portions. When continuous portions of host buffer memory are not available, relevant portions of data may be cashed within the storage device to increase performance.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 11, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11620067
    Abstract: According to various aspects of the present disclosure, methods, systems, and media for data migration are provided. In some embodiments, the systems may include: at least one computer-readable storage medium including a set of instructions for migrating data records; and at least one processor in communication with the computer-readable storage medium, wherein when executing the set of instructions, the at least one processor is directed to: query data in a data storage system comprising a plurality of slave nodes; determine, from a plurality of data records in the slave nodes, at least one candidate data record that satisfies a first condition; identify, from the slave nodes, at least one candidate slave node that satisfies a second condition; and in response to determining that the number of the at least one candidate slave node is not less than a threshold value, migrate the candidate data record to a target slave node.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: April 4, 2023
    Assignee: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Le Huang, Xun Liu