Abstract: A computer-implemented process for estimating user experience of online gaining, including the step of monitoring the flow of network packets of an online game at a monitoring location between a client gaining device and a game server to generate estimates of at least one of latency and jitter in the flow of network packets of the online game as a measure of user experience of the online game.

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

Abstract: A storage command is received that is directed to a distributed storage system. Based on the storage command, a metadata update is targeted to a logical block address of metadata storage of the distributed storage system. The metadata update includes a chunk of metadata that is smaller than a block addressed by the logical block address. An atomic write command is sent to a block device interface. The command includes the chunk of metadata, the logical block address, and an offset within the block defining where the chunk of metadata is to be stored. Via the block device interface, the atomic write command is stored in a non-volatile buffer that has faster performance than the metadata storage. The chunk of metadata of the atomic write command is written from the non-volatile buffer to the block in the metadata storage via a background process using an atomic read-modify-write command.

Abstract: Systems and methods are disclosed for load-store pipeline selection for vectors. For example, an integrated circuit (e.g., a processor) for executing instructions includes an L1 cache that provides an interface to a memory system; an L2 cache connected to the L1 cache that implements a cache coherency protocol with the L1 cache; a first store unit configured to write data to the memory system via the L1 cache; a second store unit configured to bypass the L1 cache and write data to the memory system via the L2 cache; and a store pipeline selection circuitry configured to: identify an address associated with a first beat of a store instruction with a vector argument; select between the first store unit and the second store unit based on the address associated with the first beat of the store instruction; and dispatch the store instruction to the selected store unit.

Abstract: A memory system is provided to include a memory device including a plurality of memory blocks and a controller for dynamically changing a size of a write buffer based on whether a current workload is a sequential workload or a mixed workload. The controller includes a workload detecting unit suitable for changing current workload from the sequential workload to the mixed workload based on a read count, or from the mixed workload to the sequential workload based on a write count and a write buffer managing unit suitable for reducing the size of the write buffer when the current workload is changed to the mixed workload.

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

Abstract: In some embodiments, there is provided a system which allows data to be received into a placement intelligence. After the data is analyzed, the data is written to a persistent storage device. Subsequently, the data may be written. Periodically, self-optimization may occur to improve read speeds or other metrics.

Abstract: The memory device includes a plurality of memory cells arranged in a plurality of blocks, which are arranged in at least one plane. A controller is in electrical communication with the plurality of memory cells. The controller is configured to define a multi-block group that includes at least two blocks to be erased. The controller is further configured to simultaneously apply at least one erase pulse to the multi-block group. The controller is further configured to individually and sequentially apply a verify pulse to the blocks. In response to all blocks passing verify, the controller is configured to complete the erase operation. In response to at least one of the blocks not passing verify, the controller is configured to individually and sequentially apply an erase pulse and then a verify pulse to the at least one block that did not pass verify.

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

Abstract: A hybrid printed circuit board (PCB) topology is provided. A non-volatile storage system may include a PCB, a first non-volatile storage device attached to a first side of the PCB, a second non-volatile storage device attached to a second side of the PCB, and a storage controller coupled to the first and second non-volatile storage devices by a shared channel. The two devices may be placed in a clamshell configuration but have different capacities. The shared channel may have a first signal route to a first pin of the first non-volatile storage device and a second signal route to a second pin of the second non-volatile storage device. The first pin may have a pin capacitance that is smaller than that of the second pin. The first signal route has an extra resistor in series compared to the second signal route.

Abstract: Systems and methods for caching file system collections atomically. The systems and methods perform operations comprising: receiving a request to access a collection of data comprising a plurality of files stored on a storage device; in response to receiving the request, transferring the collection of data from the storage device to a first subfolder in a cache associated with the storage device; generating a lock file comprising a reference to the first subfolder in the cache; and atomically controlling access to the collection of data in the first subfolder and removal of the collection of data in the first subfolder from the cache via the lock file.

Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.

Abstract: According to one example embodiment, a method may include receiving, by a repository entity, first information on data related to a network entity. The method may further include storing, by the repository entity, second information related to the network entity based on the first information. The second information may include at least one of an identifier of the network entity and an identifier of a data acquiring entity having acquired the data.

Abstract: A method of performing a full data reconstruction in a redundant array of independent disks (RAID) system with a protection pool of storage units includes determining that a physical disk of a storage cluster has been removed from service. The physical disk includes a set of physical extents and at least one physical extent of the set of physical extents is associated with an array of physical extents distributed across physical disks of the storage cluster. The method further includes transmitting a message to one or more array groups of the physical disks, to allocate replacement physical extents and assign the replacement physical extents to the array of physical extents and initiating reconstruction of data from the set of physical extents of the physical disk to the replacement physical extents.

Abstract: A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.

Abstract: A method for operating a cache memory having a set having multiple memory blocks configured for storing data blocks. In a write process of a data block into a memory block of the set, the data block is written into the memory block, a relevance rank value of the data block and a first access time rank value are determined. Rank data associated with the memory block are determined using a write rank mapping from the relevance rank value and the first access time rank value, and the determined rank data are stored. If no memory block of the set is free, a memory block that is to be overwritten is selected from the memory blocks of the set based on the rank data, which are associated with the memory blocks, and the data block to be stored is written into the selected memory block by using the write process.

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

Abstract: Network assistance is provided for the streaming of data from a user equipment (UE) (14) to an ingestion point (12) in a network. The network assistance may include establishing an uplink network assistance (UNA) session with a network assistance service of the network; while streaming of the data and for each segment of the data or each UNA period of the data, receiving from the network assistance service an indication of a recommended highest bit rate estimate with which the data may be streamed under current network conditions. The UE may adjust content of the data stream in accordance with the indication of the recommended highest bit rate estimation.

Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

Abstract: Techniques are provided for implementing a unified object format. The unified object format is used to format data in a performance tier (e.g., infrequently accessed data, snapshot data, etc.) into objects that are stored into an object store for low cost, scalable, long term storage compared to storage of the performance tier. With the unified object format, compression of the data may be retained when the data is stored as the objects into the object store. Additional compression may also be provided for the data in the objects. The unified object format includes slot header metadata used to track the location of the data within the object notwithstanding the data being compressed and/or stored at non-fixed boundaries. The slot header metadata may be cached at the performance tier for improved read performance and may be repaired by a repair subsystem (a slot header repair subsystem).

Abstract: A computer system and a method implementing a remote access array are provided. A first drawer includes a first processor chip. A first main memory region is operatively connected to the first processor chip. A first non-addressable memory region is operatively connected to the first processor chip and includes the first remote access array. The first remote access array is configured to track data portions that are stored in the first main memory region and for which copies were created and sent to an external node. The first remote access array is backed up in the first main memory region. The first remote access array includes one or more entries and is configured to update all of the entries in response to a multi-drawer working partition being reduced to fit within the first drawer.

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: An example method may include receiving, in a virtualized execution environment, a data access request from a storage system, identifying, in view of a virtualized execution image associated with the virtualized execution environment, an application running in the virtualized execution environment, generating a cache classification that specifies whether data accessed by the application is suitable for cache compression, including, in the data access request, a tag indicating whether cached data is to be accessed in a compressed-memory cache, wherein the tag is determined in view of the cache classification, and sending, to a server of the storage system, the data access request. The application can be identified in view of metadata included in the virtualized execution image, where the metadata comprises one or more of an application name or an application version.

Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.

Abstract: Aspects described herein relate to a method comprising: receiving a request to write data to a persistent storage device, the request comprising data; determining an affinity of the data; writing the request to a cache line of a cache; associating the cache line with the affinity of the data; and reporting the data as having been written to the persistent storage device.

Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

Abstract: A method, computer program product, and computer system for controlling, by a computing device, access to a non-volatile memory using a non-volatile lock as a reader of the non-volatile memory. Metadata (MD) non-volatile memory commits may be throttled until capacity of the non-volatile memory is at a threshold capacity.

Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

Abstract: The present disclosure generally relates to efficient data transfer. Rather than processing each command, the data storage device fetches part of the host buffers and then makes a determination regarding the attributes of the fetched buffers. Upon the determination, the command is classified as optimized, not-optimized, or somewhere in between. Optimized commands are permitted to retrieve data out of order while non-optimized commands remain in a strict in order data retrieval process. In between commands can be processed with some out of order data retrieval. In so doing, data transfers are effectively managed and optimized data by taking into account the current attributes of the host buffers per command.

Abstract: An example method of flow control between remote hosts and a target system over a front-end fabric, the target system including a nonvolatile memory (NVM) subsystem coupled to a back end fabric having a different transport than the front-end fabric is described. The method includes receiving commands from the remote hosts at a controller in the target system for the NVM subsystem. The method further includes storing the commands in a first-in-first-out (FIFO) shared among the remote hosts and implemented in memory of the target system. The method further includes updating virtual submission queues for the remote hosts based on the commands stored in the FIFO. The method further includes providing the commands to the NVM subsystem from the FIFO.

Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB.

Abstract: The present disclosure relates to a memory controller and a method of operating the memory controller. The memory controller controlling a memory device including a plurality of planes includes a central processing unit (CPU) generating a command corresponding to a request from a host, a command queue storing the command, counter logic assigning to the command, number information corresponding to an order in which the command is generated and flag information indicating a level at which an operation corresponding to the command is performed, and a command queue controller controlling the command queue to transfer the command stored in the command queue to one of the plurality of planes corresponding to the command on the basis of the number information and the flag information.

Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB.

Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

Abstract: A computer-implemented method for a crash recovery for linked databases may be provided. The linked databases comprise a source and related target database. Selected queries of the source database are transferred to the target database. The method comprises synchronizing selected portions of the source database with tables of an in-memory portion of target database and, storing persistently applied changes to the in-memory target database portion asynchronously and persistently. Upon a database crash of the target database system, the method also comprises restoring, the in-memory target database portion with the latest snapshot available, and applying, changes from the source database recovery log file that have a later timestamp than the latest snapshot available in the persistent target database storage of the in-memory target database portion.

Abstract: Example implementations described herein are directed to a method and a system for storage allocation from a storage pool, the method involving, for receipt of a request for storage through an orchestrator communicatively coupled to a management system managing the storage pool, the request comprising user information and request characteristics information, the request characteristics information indicative of a use type for the request, determining a storage tier from the storage pool for the request based on the user information and the request characteristics information; and allocating a pool name and the storage tier in response to the request.

Abstract: In a storage system including a first tier and a second tier a method includes: storing access statistics per object; obtaining a request to perform a write operation; calculating a recency factor to the first object based on the access statistics; and writing the first object to one of the first tier and the second tier, depending on the recency factor. Performing garbage collection process on the second tier may include: reading metadata of an object stored in the second tier; determining whether the object is valid based on the metadata; if the object is invalid, discarding the object; and if the second object is valid: calculating a recency factor for the object based on the access statistics of the object; and moving the object to the first tier or leaving the object in the second tier, depending on the recency factor of the second object.

Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.

Abstract: A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB.

Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

Abstract: Disclosed herein are enhancements for operating a web application firewall to reduce load. In one implementation, a method of operating a content server for a web application comprising running a web accelerator with a plurality of threads on the content server. The method further provides receiving a request for content which will be provided to a web application, filtering the request and determining that the content will be requested from a second server. After determining that the content will be requested from a second server, reviewing the request with a web application firewall operating at a network layer 7, forwarding the request, receiving the content, and providing the content. Further, the web application firewall is controlled by a plurality of sets of rules, which can be updated without restarting the web accelerator.

Abstract: A system on chip, an access command routing method, and a terminal are disclosed. The system on chip includes an IP core and a bus. The IP core is configured to: obtain, based on an access address corresponding to an access command, an address range configuration identifier corresponding to the access address; and transmit the access command and the address range configuration identifier to the bus, where the address range configuration identifier is used by the bus to route the access command. The bus is configured to route the access command to a system cache or an external memory based on the address range configuration identifier.

Abstract: The present invention discloses a service caching method for a cross-border service network, wherein the method includes: a cache space of a service switch node is divided into a resident area, a change area, a pre-reclaimed area and a maintenance index area; among them, a cache hit frequency is: a resident area>a change area>a pre-reclaimed area, and the maintenance index area is used for separate storage services call path. when a service call is generated, a cache content in the cache space is replaced according to a cache value of a missed cache or a hit cache; a service router and service switch nodes in the corresponding area jointly form a hierarchical cache mode. When the cache space of any node in the service switch node is insufficient, the service switch nodes in the same area perform collaborative cache and store them in other cache space of the service switch node through indexing.

Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.

Abstract: A tiering service enables a client to custom specify service level agreements for data items to be tiered and automatically promotes and demotes the data items amongst a warm tier, a plurality of intermediate tiers, and a cold tier to ensure the service level agreement commitments are met. In some embodiments, a client specifies segmentation criteria for defining multiple segments of data items included in a data scope or table and assigns latency targets to the segments in order to define the service level agreement. Also, in some embodiments, a plurality of intermediate tiers are implemented on common underlying hardware by varying metadata management to implement intermediate tiers that have progressively increasing latencies.

Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.

Abstract: A method and system for retransmitting messages in a memory subsystem are described. A message is transmitted to a host system. A response message is expected to be received from the host system in response to the message. A determination that the response message was not received prior to detecting an indication of a processing of a number of commands from the host system is performed. The message is retransmitted to the host system in response to the determination.

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.