In Hierarchically Structured Memory Systems, E.g., Virtual Memory Systems, Etc. (epo) Patents (Class 711/E12.016)

  • Patent number: 11144600
    Abstract: An application on a device may interact with a document service that provides access to a document service. The interaction may occur in a variety of contexts, such as a device context (e.g., the document service and the application provided on the same device), a local context (e.g., via a LAN), and a remote context (e.g., over the Internet). It may be advantageous to adapt the interaction to the current context, while also providing a consistent application interface that alleviates the application from context-specific implementations, and also achieving this adaptation in a performant manner. These considerations may be achieved in a balanced manner by providing a set of runtimes, where each runtime mediates the application/document service interaction between the application and the document service in a contextually adapted manner. The device may automatically detect the context of the interaction and select a contextually suitable runtime to service the application.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 12, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dharma Shukla, Karthik Raman
  • Publication number: 20150149733
    Abstract: Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from a cache. The at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line. Further, the plurality of state indicators is operable to indicate a state of a corresponding cache line of the cache lines.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 28, 2015
    Inventors: Guillermo Rozas, Alexander Klaiber, David Dunn, Paul Serris, Lacky Shah
  • Patent number: 9015414
    Abstract: A method of load balancing can include segmenting data from a plurality of servers into usage patterns determined from accesses to the data. Items of the data can be cached in one or more servers of the plurality of servers according to the usage patterns. Each of the plurality of servers can be designated to cache items of the data of a particular usage pattern. A reference to an item of the data cached in one of the plurality of servers can be updated to specify the server of the plurality of servers within which the item is cached.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventor: Kenneth S. Sabir
  • Patent number: 9015444
    Abstract: A method used in an access module that uses a file system to manage a nonvolatile memory of an information recording module enables an available storage space to be calculated in a short time before file data is recorded, and shortens the time required from initialization of the file system to recording. An access module (1) manages information about area management of the file system configured in an information recording module in units of fixed-length blocks. A divisional available storage space calculation unit (103) performs an available storage space calculation process in units of the fixed-length blocks, and completes preparations for recording when detecting a minimum required storage space for recording file data and enables recording of the file data. This shortens the time required from initialization of the file system to recording.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: April 21, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takuji Maeda, Tsutomu Mori, Masafumi Nosaka, Takeshi Umemoto
  • Patent number: 9009385
    Abstract: At least one virtual machine implemented on a given physical machine in an information processing system is able to detect the presence of one or more other virtual machines that are also co-resident on that same physical machine. More particularly, at least one virtual machine is configured to avoid usage of a selected portion of a memory resource of the physical machine for a period of time, and to monitor the selected portion of the memory resource for activity during the period of time. Detection of a sufficient level of such activity indicates that the physical machine is also being shared by at least one other virtual machine. The memory resource of the physical machine may comprise, for example, a cache memory, and the selected portion of the memory resource may comprise one or more randomly selected sets of the cache memory.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 14, 2015
    Assignee: EMC Corporation
    Inventors: Ari Juels, Alina M. Oprea, Michael Kendrick Reiter, Yinqian Zhang
  • Patent number: 9009443
    Abstract: A storage management application determines that a source virtual tape requires reclamation, identifies all block addresses for active data of a source virtual tape and sorts the block addresses in an ascending order, identifies a target virtual tape which has sufficient free capacity to store the active data of said source virtual tape and the last written block address on said target virtual tape, and sends a command to the VTL-system instructing it to perform reclamation including information about said source and said target virtual tape, the sorted list of block addresses denoting active data on the source virtual tape and the starting block address on the target virtual tape. The reclamation logic references the active data host blocks of said source volume to said target virtual tape starting at said starting block address by just updating the host block to disk block mapping table.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Stefan Neff
  • Patent number: 9009438
    Abstract: An approach to efficient space reclamation in multi-layered thinly provisioned systems. A parent storage volume is thinly provisioned, and uses one or more child storage volumes that are also thinly provisioned for storage. A reclamation command sent to the device providing the parent thinly provisioned storage volume identifies that data has been released, and that the physical storage storing that data can be placed in a free pool and used to satisfy future write requests in the parent storage volume. An identify module identifies which child storage volumes supporting the parent storage volume are thinly provisioned. The data is released at the level of the parent storage volume, and the reclamation command is sent to the child storage volumes supporting the parent storage volume and that are themselves thinly provisioned. The storage is thus released by all affected thinly provisioned storage volumes, and not just the parent storage volume that received the reclamation command.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul M. Fiske, Carl E. Jones, Subhojit Roy
  • Patent number: 8996841
    Abstract: The present disclosure relates to a data storage device having a hypervolume accessible by a plurality of servers operating on two or more data storage systems, a first physical volume, associated with the hypervolume, located at a first data storage system, and a second physical volume, associated with the hypervolume, located at a second storage system. The hypervolume directs input/output (I/O) from the servers to a primary physical volume comprising either the first or second physical volume, and the primary physical volume may be changed, transparently to the servers, to the other of the first or second physical volume. The present disclosure, in another embodiment, relates to a method for moving operation of a storage device from one data storage location to a second data storage location. A hypervolume is used to redirect input/output (I/O) from the a plurality of servers from the one physical volume to another.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 31, 2015
    Assignee: Compellent Technologies
    Inventors: Doug Kuligowski, Mark Mansee
  • Patent number: 8984226
    Abstract: A method of load balancing can include segmenting data from a plurality of servers into usage patterns determined from accesses to the data. Items of the data can be cached in one or more servers of the plurality of servers according to the usage patterns. Each of the plurality of servers can be designated to cache items of the data of a particular usage pattern. A reference to an item of the data cached in one of the plurality of servers can be updated to specify the server of the plurality of servers within which the item is cached.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventor: Kenneth S. Sabir
  • Patent number: 8972673
    Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
  • Patent number: 8935457
    Abstract: A physical host executes a hypervisor or virtual machine monitor (VMM) that instantiates at least one virtual machine (VM) and a virtual input/output server (VIOS). The VIOS determines by reference to a policy data structure a disposition of a packet of network communication with the VM, where the disposition includes one of dropping the packet and forwarding the packet. Thereafter, the determined disposition is applied to a subsequent packet in a same packet flow as the packet.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey J. Feng, Terry J. Hoffman, Shawn P. Mullen, Bhargavi B. Reddy
  • Patent number: 8880774
    Abstract: One embodiment of the present invention is a system including: (a) plural virtualization systems configured in a cluster; (b) storage accessible to each virtualization system of the cluster, wherein for each virtual machine operative in a virtualization system of the cluster, the storage maintains a representation of virtual machine state that includes at least a description of a hardware system virtualized and an image of virtualized memory state for the virtual machine; and (c) a failover system that, responsive to an interruption of, or on, a particular one of the virtualization systems, transitions at least one affected virtual machine to another virtualization system of the cluster and resumes computations of the transitioned virtual machine based on state encoded by a corresponding one of the virtual machine states represented in the storage.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 4, 2014
    Assignee: VMWare, Inc.
    Inventors: Rene W. Schmidt, Sridhar Rajagopal
  • Patent number: 8880797
    Abstract: A data de-duplication application de-duplicates redundant data on the primary storage read/write pathway of a virtualized server environment. The virtualized server environment comprises one or more server applications operating on a virtualization layer provided on a computer architecture that includes memory (e.g., RAM, cache memory) for temporarily storing data and storage (e.g., disk storage) for persistently storing data. The one or more server applications use the read-write pathway to read data into memory from storage and to write data to storage from memory. The de-duplication application identifies redundant data in memory, storage, or both, and replaces the redundant data with one or more pointers pointing to a single copy of the data. The de-duplication application can operate on fixed or variable size blocks of data and can de-duplicate data either post-process or in-line.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 4, 2014
    Assignee: EMC Corporation
    Inventor: Jedidiah Yueh
  • Patent number: 8874823
    Abstract: Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 28, 2014
    Assignee: Intellectual Property Holdings 2 LLC
    Inventors: Vikram Joshi, Yang Luan, Manish R. Apte, Hrishikesh A. Vidwans, Michael F. Brown
  • Patent number: 8868880
    Abstract: A computing system includes virtualization software including a guest operating system (OS). A method maintains, by the virtualization software layer, a first shadow page table for use in a kernel mode and a second shadow page table for use in a user mode. The virtualization software switches between using the first shadow page table and the second shadow page table when the guest OS switches between operating in the kernel mode and the user mode.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: October 21, 2014
    Assignee: VMware, Inc.
    Inventors: Scott W. Devine, Lawrence S. Rogel, Prashanth P. Bungale, Gerald A. Fry
  • Patent number: 8862858
    Abstract: A computer-implemented method and apparatus manages block mapping. The block mapping maps physical blocks in a block storage device to virtual blocks of a virtual address space. The method involves assigning a generation number from a net of generation numbers to each block mapping entry, where the block mapping entry correlates a physical block with a virtual block. A maximum generation number of the set of generation numbers is increased and a first block mapping entry is marked dirty in response to an update of a correlated first virtual block. A generation number of the first block mapping entry is set to the maximum generation number. Finally, a generation number of a second block mapping entry having a lowest generation number is set to a generation number of the first block mapping entry.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 14, 2014
    Assignee: EMC Corporation
    Inventor: Kadir Ozdemir
  • Patent number: 8843706
    Abstract: Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Heil, Robert A. Shearer
  • Patent number: 8838916
    Abstract: A method uses a record of I/O priorities in a determination of a storage medium of a hybrid storage system in which to store a file. The method maintains the record of I/O priorities by assigning an I/O temperature value to each request for access to the file based upon an I/O priority level of the process making the request. The method marks the file as hot if the file temperature value is greater than a threshold value. The method stores files marked as hot in a lower latency storage medium of the hybrid storage medium.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mingming Cao, Ben Chociej, Scott R. Conor, Steven M. French, Matthew R. Lupfer, Steven L. Pratt
  • Patent number: 8838913
    Abstract: A system and method for locating a memory page in a guest virtual machine are provided. An execution event is triggered, in response to a request to allocate a first memory page in a virtual machine. A processor sends an indication to a hypervisor that the first memory page has been allocated in the virtual machine, in response to the triggering of the execution event. Responsive to receiving the indication, a security virtual machine appropriates control, via the hypervisor, of the first memory page allocated in the virtual machine and inserts program code in the first memory page. The processor executes the program code. The security virtual machine relinquishes control of the first memory page allocated in the virtual machine, in response to determining the program code has completed execution.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 16, 2014
    Assignee: Symantec Corporation
    Inventor: Matthew Conover
  • Patent number: 8832377
    Abstract: Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks. A determination is made of tracks to demote from a first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are to a second stride in the second cache having an occupancy count indicating the stride is empty. A determination is made of a target stride in the second cache based on the occupancy counts of the strides in the second cache. A determination is made of at least two source strides in the second cache having valid tracks based on the occupancy counts of the strides in the second cache. The target stride is populated with the valid tracks from the source strides.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 8825957
    Abstract: Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks. A determination is made of tracks to demote from a first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are to a second stride in the second cache having an occupancy count indicating the stride is empty. A determination is made of a target stride in the second cache based on the occupancy counts of the strides in the second cache. A determination is made of at least two source strides in the second cache having valid tracks based on the occupancy counts of the strides in the second cache. The target stride is populated with the valid tracks from the source strides.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 8825956
    Abstract: Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 8825966
    Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: September 2, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventor: Peter Gillingham
  • Patent number: 8825953
    Abstract: Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 8819345
    Abstract: Method, apparatus, and computer program product embodiments of the invention are disclosed for efficient communication between processor units in a multi-core processor integrated circuit architecture. In example embodiments of the invention, a method comprises: storing with a shared inter-core communication unit in a multi-core processor, first data produced by a producer processor core, in a first token memory located at a first memory address of a memory address space; and connecting with the shared inter-core communication unit, the first token memory to a consumer processor core of the multi-core processor, to load the first data from the first token memory into the consumer processor core, in response to a first-type command from the producer processor core.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Nokia Corporation
    Inventors: Tommi Juhani Zetterman, Kalle August Raiskila, Harri Hirvola
  • Patent number: 8788754
    Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses and available to said hosts and characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to a configuration or I/O request addressed to the logical block addresses, to translate said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage devices, operable to represent an available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS), addresses in PVAS having corresponding address in IVAS. The second virtual layer is operable to translate said respective IVAS addresses into addresses in the physical address space.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 22, 2014
    Assignee: Infinidat Ltd.
    Inventors: Yechiel Yochai, Leo Corry, Haim Kopylovitz
  • Patent number: 8782338
    Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Patent number: 8769183
    Abstract: A method for mirroring virtual machines from a primary host to a secondary host. The method includes tracking changes for each of a plurality of memory pages and processor states for one or more primary host virtual machines. Responsive to an occurrence of a checkpoint, the primary host virtual machines are stopped. A determination is made if each of the memory pages is frequently changed. In response to the memory page being frequently changed, the frequently changed memory page is marked as being writeable and copied to a buffer. In response to the memory page being infrequently changed, the infrequently changed memory page is marked as being read only. The one or more primary host virtual machines are resumed. A copy of the memory pages, the buffer and changes to the processor states are transmitted to the secondary host.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Graham Hunter, James Mulcahy
  • Patent number: 8756361
    Abstract: A disk drive is disclosed comprising a head actuated over a rotatable disk. A write operation is processed to write data on the disk using the head, wherein prior to writing the data on the disk, logical-to-physical mapping information is stored in a circular buffer, wherein the logical-to-physical mapping information identifies locations on the disk to write the data. A plurality of metadata files are written on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk. When the write operation is aborted, the logical-to-physical mapping information in the circular buffer is modified to identify the locations on the disk actually written.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: June 17, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marcus A. Carlson, David C. Pruett
  • Patent number: 8756383
    Abstract: A mechanism for random cache line selection in virtualization systems is disclosed. A method includes maintaining a secondary data structure representing a plurality of memory pages, the secondary data structure indexed by a subset of each memory page, determining an index of a received new memory page by utilizing a subset of the new memory page that is a same size and at a same offset as the subset of each memory page, comparing the index of the new memory page with the indices of the secondary data structure for a match, utilizing a main data structure to perform a full page memory comparison with the new memory page if a match is found in the secondary data structure, and updating at least one of the size of the subset, the number of subsets, and the offsets of the subsets used to index the memory page.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: June 17, 2014
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 8751752
    Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Eric C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Gilbert Neiger, Richard Uhlig
  • Patent number: 8745311
    Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 3, 2014
    Assignee: Spansion LLC
    Inventor: Tzungren Allan Tzeng
  • Patent number: 8738850
    Abstract: Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 27, 2014
    Assignee: Oracle International Corporation
    Inventors: SangCheol Lee, BongSoo Ko, HyungGook Yoo, SongHee Kang
  • Patent number: 8738881
    Abstract: Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: May 27, 2014
    Assignee: NEC Corporation
    Inventors: Noriaki Suzuki, Sunao Torii, Junji Sakai
  • Patent number: 8732431
    Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin L. Culley, Troy A. Manning, Troy D. Larsen
  • Publication number: 20140136782
    Abstract: An operating system is configured to receive a request to store an object that does not specify the location at which the object should be stored. The request might also include an optimization factor and one or more object location factors. The operating system might also generate object location factors or retrieve object location factors from one or more external locations. Object location factors might also be utilized that are based upon properties of the object to be stored. Utilizing the object location factors, and the optimization factor if provided, the operating system dynamically selects an appropriate storage tier for storing the object. The tiers might include a local storage tier, a local network storage tier, a remote network storage tier, and other types of storage tiers. The object is then stored on the selected storage tier. The object may be retrieved from the storage tier at a later time.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: Amazon Technologies, Inc.
    Inventor: Amazon Technologies, Inc.
  • Patent number: 8725963
    Abstract: A computer system has a random access memory (RAM) that stores currently used memory pages and SWAP storage for storing memory page that is not in use. If the process requires memory page stored on the SWAP storage, a corresponding page is loaded to RAM. If the page in RAM is not currently in use, it is moved to the SWAP storage. The computer system has a number of Virtual Environments (i.e., Containers) that run their own processes, a VE/Container RAM and a virtual SWAP storage. The Container processes have access to a VE/Container RAM. When the Container process request OS for memory, the memory manager allocates memory pages in the RAM and also allocates memory pages for the Container process in the VE/Container RAM. If no free virtual RAM is available, the process data is moved to the virtual SWAP storage.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: May 13, 2014
    Assignee: Parallels IP Holdings GmbH
    Inventors: Pavel Emelianov, Kirill Korotaev, Alexander G. Tormasov
  • Publication number: 20140122800
    Abstract: A device for use in monitoring operation of a system asset includes an interface for receiving sensor data representative of an operating condition of the system asset, a memory device for storing the sensor data, and a processor coupled to the interface and to the memory device. The processor is configured to create a hierarchy of sensor data within the memory device, wherein the hierarchy comprises a first tier and a second tier, store a first level of the sensor data in the first tier, and store a second level of the sensor data in the second tier.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventor: Scott Terrell Williams
  • Publication number: 20140095789
    Abstract: Embodiments relate to a system and computer program product for data management. An aspect includes a method for assigning storage types to data based on access frequency. Past or historical data associated with current data usage is also considered prior to assignment. Once data frequency access is determined, the current data is assigned to a first tier of a plurality of hierarchical ordered tiers, each tier corresponding to at least one class of storage. In one embodiment, there may be a condition that overrides the assignment with option to override it. The tier assignment may also be preserved so that the current data can be appropriately assigned in the future.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Patent number: 8688953
    Abstract: A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hubertus Franke, Benjamin Herrenschmidt, Jon K. Kriegel, Andrew M. Theurer, James Xenidis
  • Patent number: 8683125
    Abstract: A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jichuan Chang, Kevin T Lim, Parthasarathy Ranganathan
  • Publication number: 20140082307
    Abstract: Arbitrating memory access between a central processing unit CPU and a peripheral device to main memory. The memory access to and from the main memory by the CPU and memory access to and from the main memory by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level. An arbitration module is provided externally to the CPU, to the peripheral device and to the memory controller. The arbitration module receives the peripheral device priority level. When the CPU priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module outputs to the memory controller a new CPU priority level less than the highest available priority level.
    Type: Application
    Filed: September 17, 2012
    Publication date: March 20, 2014
    Applicant: MOBILEYE TECHNOLOGIES LIMITED
    Inventors: Yosef Kreinin, Yosi Arbeli
  • Patent number: 8677063
    Abstract: This disclosure relates to parity declustered storage device arrays having partition groups. In an exemplary embodiment, the storage system includes a storage device array, such as disk array. Each storage device is divided into partitions. Each partition includes stripe units, such as hundreds or thousands of stripe units in exemplary embodiments. The storage system also includes a physical array controller coupled to the storage device array. In an exemplary embodiment, the array controller includes a partition group lookup table and stores and retrieves data and parity in the storage devices based on the partition group lookup table. In this exemplary embodiment, the array controller also includes a stripe lookup table and/or a log. In an exemplary embodiment, the partition group lookup table and the stripe lookup table take up less memory (e.g., by an order of magnitude) than a single-level stripe map conveying the same information.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ralph A Becker-Szendy, Veera Deenadhayalan, D. Scott Guthridge, James Christopher Wyllie
  • Publication number: 20140068204
    Abstract: A tracking buffer apparatus is disclosed. A tracking buffer apparatus includes lookup logic configured to locate entries having a transaction identifier corresponding to a received request. The lookup logic is configured to determine which of the entries having the same transaction identifier has a highest priority and thus cause a corresponding entry from a data buffer to be provided. When information is written into the tracking buffer, write logic writes a corresponding transaction identifier to the first free entry. The write logic also writes priority information in the entry based on other entries having the same transaction identifier. The entry currently being written may be assigned a lower priority than all other entries having the same transaction identifier. The priority information for entries having a common transaction identifier with one currently being read are updated responsive to the read operation.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Inventor: Shu-Yi Yu
  • Patent number: 8661205
    Abstract: A communication apparatus has plural processors to perform pipeline processing on communication data. A first processor among the plural processors transfers information, used by a second processor to perform post-stage processing of the first processor, from a first memory to a second memory.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: February 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masami Shimakura, Yuta Masuda
  • Patent number: 8656096
    Abstract: A method for concurrently converting a standard volume to a thin-provisioned volume includes initially establishing metadata for a thin-provisioned volume. The method then updates the metadata for the thin-provisioned volume to point to extents residing in a standard volume. The method then suspends I/O to metadata for the standard volume. Upon suspending the I/O, the method migrates control of the extents in the standard volume from a standard-volume control algorithm to a thin-provisioned-volume control algorithm. The method then resumes the I/O to the metadata for the thin-provisioned volume. Using this technique, standard volumes may be rapidly converted to thin-provisioned volumes while minimally disrupting I/O to the volumes. A corresponding apparatus and computer program product are also disclosed and claimed herein.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mario Francisco Acedo, Paul Anthony Jennas, II, Jason Lee Peipelman, Richard Anthony Ripberger, Matthew John Ward
  • Patent number: 8656136
    Abstract: In the computer system, a storage system provides a storage level virtual volume based on thin provisioning technology, to a physical server on which a virtual machine is defined. The storage system releases the area of the logical volume corresponding to the storage level virtual volume accessed by a virtual machine which is specified to be deleted, on the basis of storage level virtual volume conversion information which is managed by the storage system.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Yamamoto, Masataka Innan, Nobuhiko Ando, Takato Kusama, Nobuo Beniyama, Yoshiki Fukui, Katsutoshi Asaki
  • Patent number: 8656102
    Abstract: A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: February 18, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: St├ęphane Guyetant, St├ęphane Chevobbe
  • Publication number: 20140047201
    Abstract: The present application is directed to a memory-access-multiplexing memory controller that can multiplex memory accesses from multiple hardware threads, cores, and processors according to externally specified policies or parameters, including policies or parameters set by management layers within a virtualized computer system. A memory-access-multiplexing memory controller provides, at the physical-hardware level, a basis for ensuring rational and policy-driven sharing of the memory-access resource among multiple hardware threads, cores, and/or processors.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: VMware, Inc,
    Inventor: Bhavesh MEHTA
  • Patent number: 8645646
    Abstract: A mechanism is provided in a computing system for controlling virtualized storage operable to communicate with a host and with mapped and unmapped storage resource pools. A selection component selects a target for a destructive data storage operation from the mapped storage resource pool. Responsive to the selection of the target, a virtual targeting component creates a virtual target from the unmapped storage resource pool to represent the target. Responsive to the selection of the target, a storage move component moves the target to a protected storage resource pool. Responsive to the creation of the virtual target from the unmapped storage resource pool, storage move component, moves the virtual target to the used storage resource pool. The computing system then performs the destructive data storage operation on the virtual target.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Christopher B. Beeken, Carlos F. Fuente, Simon Walsh