Addressing Of Memory Level In Which Access To Desired Data Or Data Block Requires Associative Addressing Means, E.g., Cache, Etc. (epo) Patents (Class 711/E12.017)

  • Patent number: 10387157
    Abstract: An instruction set conversion system and method is provided, which can convert guest instructions to host instructions for processor core execution. Through configuration, instruction sets supported by the processor core are easily expanded. A method for real-time conversion between host instruction addresses and guest instruction addresses is also provided, such that the processor core can directly read out the host instructions from a higher level cache, reducing the depth of a pipeline.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 20, 2019
    Assignee: SHANGHAI XINHAO MICROELECTRONICS CO. LTD.
    Inventor: Kenneth Chenghao Lin
  • Patent number: 10089196
    Abstract: A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 2, 2018
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Xueshi Yang
  • Patent number: 9990207
    Abstract: A semiconductor device with improved operating speed is provided. A semiconductor device including a memory circuit has a function of storing a start-up routine in the memory circuit and executing the start-up routine, a function of operating the memory circuit as a buffer memory device after executing the start-up routine, and a function of loading the start-up routine into the memory circuit from outside before the semiconductor device is powered off.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 5, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9792989
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a command managing unit, a command issuing unit, a data control unit and a command monitoring unit. The command issuing unit issues a command received by the command managing unit to the nonvolatile memory. The data control unit controls a reading or writing of data to the nonvolatile memory. The command monitoring unit monitors the command managing unit and outputs a receipt signal to the data control unit when the command managing unit receives the command. The data control unit interrupts the reading or writing when receiving the receipt signal, issues the command from the command issuing unit to the nonvolatile memory, and resumes the reading or writing after issuing the command.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: October 17, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tatsuhiro Suzumura
  • Patent number: 9600360
    Abstract: An aspect includes receiving a fetch request for a data block at a cache memory system that includes cache memory that is partitioned into a plurality of cache data ways including a cache data way that contains the data block. The data block is fetched and it is determined whether the in-line ECC checking and correcting should be bypassed. The determining is based on a bypass indicator corresponding to the cache data way. Based on determining that in-line ECC checking and correcting should be bypassed, returning the fetched data block to the requestor and performing an ECC process for the fetched data block subsequent to returning the fetched data block to the requestor. Based on determining that in-line ECC checking and correcting should not be bypassed, performing the ECC process for the fetched data block and returning the fetched data block to the requestor subsequent to performing the ECC process.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F. Fee, Pak-kin Mak, Arthur J. O'Neill, Jr., Deanna Postles Dunn Berger
  • Patent number: 9600361
    Abstract: An aspect includes receiving a fetch request for a data block at a cache memory system that includes cache memory that is partitioned into a plurality of cache data ways including a cache data way that contains the data block. The data block is fetched and it is determined whether the in-line ECC checking and correcting should be bypassed. The determining is based on a bypass indicator corresponding to the cache data way. Based on determining that in-line ECC checking and correcting should be bypassed, returning the fetched data block to the requestor and performing an ECC process for the fetched data block subsequent to returning the fetched data block to the requestor. Based on determining that in-line ECC checking and correcting should not be bypassed, performing the ECC process for the fetched data block and returning the fetched data block to the requestor subsequent to performing the ECC process.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F. Fee, Pak-kin Mak, Arthur J. O'Neill, Jr., Deanna Postles Dunn Berger
  • Patent number: 9384091
    Abstract: A memory 10 stores a data block comprising a plurality of data values DV. An error code, such as an error correction code ECC, is associated with the memory and has a value dependent upon the plurality of data values which form the data block stored within the memory. If a partial write is performed on a data block, then the ECC information becomes invalid and is marked with an ECC_invalid flag. The intent is avoiding the need to read all data values to compute the ECC and thus save time and energy. The memory may be a cache line 28 within a level 1 cache memory 10. Memory scrub control circuitry 38 performs periodic memory scrub operations which trigger flushing of partially written cache lines back to main memory.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: July 5, 2016
    Assignee: ARM Limited
    Inventor: Luc Orion
  • Patent number: 9323669
    Abstract: A computer-executable method, system, and computer program product for managing a data storage system, wherein the data storage system includes a cache and a data storage array, the computer-executable method, system, and computer program product comprising receiving initialization information, analyzing the initialization information to determine which portions of the data storage array related to the initialization information, and managing the data storage system based on the determined portion of the data storage array.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: April 26, 2016
    Assignee: EMC Corporation
    Inventors: Guido A. DiPietro, Michael J. Cooney, Gerald E. Cotter, Philip Derbeko
  • Patent number: 9043570
    Abstract: Methods and apparatuses for implementing a system cache with quota-based control. Quotas may be assigned on a group ID basis to each group ID that is assigned to use the system cache. The quota does not reserve space in the system cache, but rather the quota may be used within any way within the system cache. The quota may prevent a given group ID from consuming more than a desired amount of the system cache. Once a group ID's quota has been reached, no additional allocation will be permitted for that group ID. The total amount of allocated quota for all group IDs can exceed the size of system cache, such that the system cache can be oversubscribed. The sticky state can be used to prioritize data retention within the system cache when oversubscription is being used.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 26, 2015
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Shinye Shiu, James Wang
  • Patent number: 8990500
    Abstract: In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first least significant byte. The first most significant byte is stored at a first storage location and the first least significant byte is stored at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses. If the first most significant byte does not equal zero, the indicator is set to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero. The character array comprises the first most significant byte and the first least significant byte.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeremy A. Arnold, Scott A. Moore, Gregory A. Olson, Eric J. Stec
  • Patent number: 8966204
    Abstract: Migrating data may include determining to copy a first data block in a first memory location to a second memory location and determining to copy a second data block in the first memory location to the second memory location based on a migration policy.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: February 24, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jichuan Chang, Justin James Meza, Parthasarathy Ranganathan
  • Patent number: 8954672
    Abstract: The present disclosure relates to a method and system for mapping cache lines to a row-based cache. In particular, a method includes, in response to a plurality of memory access requests each including an address associated with a cache line of a main memory, mapping sequentially addressed cache lines of the main memory to a row of the row-based cache. A disclosed system includes row index computation logic operative to map sequentially addressed cache lines of a main memory to a row of a row-based cache in response to a plurality of memory access requests each including an address associated with a cache line of the main memory.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: February 10, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Mark D. Hill
  • Patent number: 8954677
    Abstract: In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an inbound request is received, a serialized object received in the request is compared to the serialization cache. If the serialized byte stream is present in the serialization cache, then the equivalent object is retrieved from the object cache, thereby avoiding deserialization of the received serialized object. If the serialized byte stream is not present in the serialization cache, then the serialized byte stream is deserialized, the deserialized object is cached in the object cache, and the serialized object is cached in the serialization cache.
    Type: Grant
    Filed: June 15, 2014
    Date of Patent: February 10, 2015
    Assignee: Open Invention Network, LLC
    Inventors: Deren George Ebdon, Robert W. Peterson
  • Patent number: 8949530
    Abstract: Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mvv A. Krishna, Shaul Yifrach
  • Patent number: 8943271
    Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: January 27, 2015
    Assignee: Microsoft Corporation
    Inventors: Muralidhar Krishnaprasad, Anil K. Nori, Subramanian Muralidhar
  • Patent number: 8935476
    Abstract: Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Paul H. Muench, Cheng-Chung Song
  • Patent number: 8935477
    Abstract: Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Paul H. Muench, Cheng-Chung Song
  • Patent number: 8930626
    Abstract: A method and computer program product for dividing a cache memory system into a plurality of cache memory portions. Data to be written to a specific address within an electromechanical storage system is received. The data is assigned to one of the plurality of cache memory portions, thus defining an assigned cache memory portion. Association information for the data is generated, wherein the association information defines the specific address within the electromechanical storage system. The data and the association information is written to the assigned cache memory portion.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 6, 2015
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Kiran Madnani, David W. DesRoches
  • Patent number: 8930630
    Abstract: The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 6, 2015
    Assignee: Sejong University Industry Academy Cooperation Foundation
    Inventor: Gi Ho Park
  • Patent number: 8924645
    Abstract: Data storage apparatus and methods are disclosed. A disclosed example data storage apparatus comprises a cache layer and a processor in communication with the cache layer. The processor is to dynamically enable or disable the cache layer via a cache layer enable line based on a data store access type.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: December 30, 2014
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Jichuan Chang, Parthasarathy Ranganathan, David Andrew Roberts, Mehul A. Shah, John Sontag
  • Patent number: 8909869
    Abstract: A controlling a cache memory includes: a data receiving unit to receive a sensor ID and data detected by the sensor; an attribute information acquiring unit to acquire attribute information corresponding to the sensor ID, from an attribute information memory, the attribute information memory storing the attribute information of the sensor mapped to the sensor ID; a sensor information memory to store information of a storage period, the sensor information memory including a cache memory storing the attribute information; and a cache memory control unit to acquire the attribute information from the attribute information acquiring unit when the attribute information is not stored in the cache memory, and store the acquired attribute information corresponding to the sensor ID in the cache memory during the storage period.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Limited
    Inventor: Masahiko Murakami
  • Patent number: 8909864
    Abstract: Techniques for implementing a multicast write command are described. A data block may be destined for multiple targets. The targets may be included in a list. A multicast write command may include the list. Write commands may be sent to each target in the list.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Joseph David Black, Michael G Myrah, Balaji Natrajan
  • Patent number: 8874846
    Abstract: Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Ashish Jagmohan, John P. Karidis, Luis A. Lastras-Montano, Moinuddin K. Qureshi
  • Patent number: 8874847
    Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 28, 2014
    Assignee: IP Cube Partners (IPC) Co., Ltd.
    Inventor: Moon J. Kim
  • Patent number: 8862800
    Abstract: A dispersed storage (DS) unit includes a processing module and a plurality of hard drives. The processing module is operable to maintain states for at least some of the plurality of hard drives. The processing module is further operable to receive a memory access request regarding an encoded data slice and identify a hard drive of the plurality of hard drives based on the memory access request. The processing module is further operable to determine a state of the hard drive. When the hard drive is in a read state and the memory access request is a write request, the processing module is operable to queue the write request, change from the read state to a write state in accordance with a state transition process, and, when in the write state, perform the write request to store the encoded data slice in the hard drive.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, S. Christopher Gladwin
  • Patent number: 8862825
    Abstract: A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwon Taek Kwon
  • Patent number: 8856443
    Abstract: According to the teaching disclosed herein there is provided at least a method, system and device for managing a cache memory of a storage system. The storage system is associated with at least one physical storage device and, responsive to a read request, comprising information indicative of a logical address of at least one requested data unit, to obtain a storage physical address associated with the logical address, search the cache memory for a data unit associated with the storage physical address and service the request from the cache in case the data unit is found in the cache memory.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: October 7, 2014
    Assignee: Infinidat Ltd.
    Inventors: Julian Satran, Israel Gold, Efraim Zeidner, Yechiel Yochai, Sivan Tal
  • Patent number: 8849966
    Abstract: Embodiments of the invention provide a solution to optimize/minimize the total capacity of Gold Image within the entire datacenter which utilizes a scale-out type of storage systems. A method of server image provisioning comprises checking whether a gold image exists in a first storage system, the gold image being one of a real gold image or a virtual gold image; if no gold image exists in the first storage system, searching a remainder of the storage systems until a real gold image is found in a second storage system; after finding the real gold image in the second storage system, creating a virtual gold image in the first storage system, the virtual gold image in the first storage system being associated with the real gold image in the second storage system; and creating a snapshot volume in the first storage system based on the virtual gold image.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: September 30, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Atsushi Murase
  • Patent number: 8850121
    Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Matthew W. Ashcraft, John Gregory Favor, David A. Kruckemyer
  • Patent number: 8850135
    Abstract: Embodiments of the present disclosure provide methods and systems for securely installing software on a computing device, such as a mobile device. In one embodiment, the device executes an installer that securely installs the software. In order to perform installations securely, the installer configures one or more secure containers for the software and installs the software exclusively in these containers. In some embodiments, the installer randomly determines the identifiers for the containers. These identifiers remain unknown to the software to be installed. Instead, an installation framework maintains the correspondence between an application and its container. Other methods and apparatuses are also described.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 30, 2014
    Inventors: Dallas De Atley, Simon Cooper
  • Patent number: 8843705
    Abstract: A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jian Li, Ramakrishnan Rajamony, William E. Speight, Lixin Zhang
  • Patent number: 8838897
    Abstract: Technologies are generally described for exploiting program phase behavior to duplicate most recently and/or frequently accessed tag entries in a Tag Replication Buffer (TRB) to protect the information integrity of tag arrays in a processor cache. The reliability/effectiveness of microprocessor cache performance may be further improved by capturing/duplicating tags of dirty cache lines, exploiting the fact that detected error-corrupted clean cache lines can be recovered by L2 cache. A deterministic TRB replacement triggered early write-back scheme may provide full duplication and recovery of single-bit errors for tags of dirty cache lines.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 16, 2014
    Assignee: New Jersey Institute of Technology
    Inventors: Jie Hu, Shuai Wang
  • Patent number: 8838896
    Abstract: The present patent application discloses a method and apparatus for using external and internal memory for cancelling traffic interference comprising storing data in an external memory; and processing the data samples on an internal memory, wherein the external memory is low bandwidth memory; and the internal memory is high bandwidth on board cache. The present method and apparatus also comprises caching portions of the data on the internal memory, filling the internal memory by reading the newest data from the external memory and updating the internal memory; and writing the older data back to the external memory from the internal memory, wherein the data is incoming data samples.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Senthil Govindaswamy, Jeffrey A. Levin, Raghu Sagar Madala, Sharad Deepak Sambhwani
  • Patent number: 8832414
    Abstract: Technologies are generally described herein for determining a profitability of direct fetching in a multicore processor. The multicore processor may include a first and a second tile. The first tile may include a first core and a first cache. The second tile may include a second core, a second cache, and a fetch location pointer register (FLPR). The multicore processor may migrate a thread executing on the first core to the second core. The multicore processor may store a location of the first cache in the FLPR. The multicore processor may execute the thread on the second core. The multicore processor may identify a cache miss for a block in the second cache. The multicore processor may determine whether a profitability of direct fetching of the block indicates direct fetching or directory-based fetching. The multicore processor may perform direct fetching or directory-based fetching based on the determination.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: September 9, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 8806145
    Abstract: Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 12, 2014
    Assignee: Oracle America, Inc.
    Inventors: Zoran Radovic, Erik Martin Roland Karlsson
  • Patent number: 8806137
    Abstract: An apparatus for performing data caching comprises at least one cache memory including multiple cache lines arranged into multiple segments, each segment having a subset of the cache lines associated therewith. The apparatus further includes a first plurality of counters, each of the counters being operative to track a number of active cache lines associated with a corresponding one of the segments. At least one controller included in the apparatus is operative to receive information relating to the number of active cache lines associated with a corresponding segment from the first plurality of counters and to implement a cache segment replacement policy for determining which of the segments to replace as a function of at least the information relating to the number of active cache lines associated with a corresponding segment.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Alexander Rabinovitch, Leonid Dubrovin
  • Patent number: 8799576
    Abstract: A system for caching data in a distributed data processing system allows for the caching of user-modifiable data (as well as other types of data) across one or multiple entities in a manner that prevents stale data from being improperly used.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 5, 2014
    Assignee: Amazon Technologies, Inc.
    Inventors: Jonathan A. Jenkins, Mark S. Baumback, Ryan J. Snodgrass
  • Patent number: 8793435
    Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 29, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Matthew W. Ashcraft, John Gregory Favor, David A. Kruckemyer
  • Patent number: 8782338
    Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Patent number: 8775738
    Abstract: To increase the efficiency of a running application, it is determined whether using a cache or directly a storage is more efficient block size-specifically; and the determined memory type is used for a data stream having a corresponding block size.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 8, 2014
    Assignee: Tuxera Inc
    Inventor: Szabolcs Szakacsits
  • Patent number: 8769204
    Abstract: A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: July 1, 2014
    Assignee: Marvell International Ltd.
    Inventors: Joseph Delgross, Sujat Jamil, R. Frank O'Bleness, Tom Hameenanttila, David E. Miner
  • Patent number: 8769203
    Abstract: In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an inbound request is received, a serialized object received in the request is compared to the serialization cache. If the serialized byte stream is present in the serialization cache, then the equivalent object is retrieved from the object cache, thereby avoiding deserialization of the received serialized object. If the serialized byte stream is not present in the serialization cache, then the serialized byte stream is deserialized, the deserialized object is cached in the object cache, and the serialized object is cached in the serialization cache.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: July 1, 2014
    Assignee: Open Invention Network, LLC
    Inventors: Deren George Ebdon, Robert W. Peterson
  • Patent number: 8762641
    Abstract: A method is described for use when a cache is accessed. Before all valid array entries are validated, a valid array entry is read when a data array entry is accessed. If the valid array entry is a first array value, access to the cache is treated as being invalid and the data array entry is reloaded. If the valid array entry is a second array value, a tag array entry is compared with an address to determine if the data array entry is valid or invalid. A valid control register contains a first control value before all valid array entries are validated and a second control value after all valid array entries are validated. After the second control value is established, reads of the valid array are disabled and the tag array entry is compared with the address to determine if a data array entry is valid or invalid.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: June 24, 2014
    Assignee: Qualcomm Incorporated
    Inventor: Arthur Joseph Hoane, Jr.
  • Patent number: 8756374
    Abstract: Some described embodiments provide a system that performs stores in a memory system. During operation, the system receives a store for a first thread. The system then creates an entry for the store in a store queue for the first thread. While creating the entry, the system requests a store-mark for a cache line for the store, wherein the store-mark for the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. The system then receives a response to the request for the store-mark, wherein the response indicates that the cache line for the store is store-marked. Upon receiving the response, the system updates a set of ordered records for the first thread by inserting data for the store in the set of ordered records, wherein the set of ordered records include store-marked stores for the first thread.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: June 17, 2014
    Assignee: Oracle International Corporation
    Inventors: Robert E. Cypher, Haakan E. Zeffer
  • Patent number: 8751766
    Abstract: A storage system including: a plurality of storage devices; a volatile memory which temporarily stores data; a nonvolatile memory; a battery saving power; a cache control unit which sets, according to battery charging rate of the battery, a part of the data stored in the volatile memory as save target data which are to be saved to the nonvolatile memory when power interruption occurs, and saves the part of the data, which is set as the save target data, to the nonvolatile memory by using power of the battery when power interruption occurs.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 10, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Inoue, Yasuyuki Nagasoe
  • Patent number: 8725971
    Abstract: A drop in the access performance to a source volume is prevented by executing various control methods according to the snapshot usage method. A storage apparatus comprises one or more storage devices which provide storage areas; and a controller which creates a logical volume in the storage area provided by the one or more storage devices, and which reads and writes data from/to the logical volume according to a request from a host, wherein the controller acquires one or more snapshots which are data images at certain time points of the logical volume, wherein the controller determines whether the logical volume is subject to abrupt load fluctuations on the basis of performance information of the logical volume and the snapshots, and wherein, if the logical volume is subject to abrupt load fluctuations, the controller executes predetermined control processing according to usage cases of the snapshots.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: May 13, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yasuaki Nakamura, Tomohiko Suzuki, Tetsuya Abe, Akemi Sanada
  • Patent number: 8719506
    Abstract: In an embodiment, a memory port controller (MPC) is coupled to a memory port and receives transactions from processors and a coherency port (ACP) used by one or more peripheral devices that may be cache coherent. The transactions include various quality of service (QoS) parameters. If a high priority QoS transaction is received on the ACP, the MPC may push previous (lower priority) transactions until the high priority transaction may be completed. The MPC may maintain a count of outstanding high priority QoS transactions. The L2 interface controller and ACP controller may push increment and decrement events based on processing the high priority QoS transactions, and the MPC may push the memory transactions when the count is non-zero. In an embodiment, the MPC may continue pushing transactions until the L2 interface controller informs the MPC that the earlier transactions have been completed.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: May 6, 2014
    Assignee: Apple Inc.
    Inventor: Jason M. Kassoff
  • Patent number: 8719508
    Abstract: Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Miguel Comparan, Robert A. Shearer
  • Patent number: 8719499
    Abstract: Embodiments of the invention provide a method, system, and computer program product for cache-line based notification. An embodiment of the method comprises injecting a cache-line including notification information into a cache of a processing unit, marking the cache-line as having the notification information, and using the notification information to notify a processing thread of the presence of the cache-line in the cache. In an embodiment, the cache-line identifies a thread affiliation. In an embodiment, a multitude of threads operate in the processing unit, and the using includes notifying a plurality of these threads of the presence of the cache-line in the cache, and analyzing the cache-line to identify this plurality of threads. The cache may include a plurality of cache-lines, each of which includes a notification, and the processing unit thread uses these notifications to form a linked list of at least some of the cache-lines.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventor: Florian Alexander Auernhammer
  • Patent number: 8719507
    Abstract: Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Miguel Comparan, Robert A. Shearer