Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.

Abstract: The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface.

Abstract: A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.

Abstract: A system can include a microprocessor having a prefetch queue including a plurality of slots configured to store program counter values (PCVs) and instructions, a pipeline configured to receive instructions from the prefetch queue, and a select circuit coupled to the prefetch queue. The select circuit may selectively freeze a first slot of the plurality of slots and selectively output a frozen PCV and a frozen instruction from the first slot while frozen. The microprocessor can include write logic coupled to the prefetch queue and a comparator circuit coupled to the prefetch queue and the select circuit. The write logic may load data into unfrozen slots of the prefetch queue. The comparator circuit may compare a target PCV with the frozen PCV to determine a match. The select circuit indicates, to the pipeline, whether the frozen instruction is valid based on the comparing.

Abstract: A method and system for assessing sequentiality of a data stream is disclosed. Specifically, the method and system disclosed herein may entail receiving an incoming request to access a page in a cache memory, wherein the page is identified by a page address of an address space in a main memory; identifying, in a memory, a bin corresponding to an address range including the page address of the page of the incoming request, wherein the bin includes k address ranges of the address space of the main memory; determining whether to update an occupation count of the bin in the memory; locating the bin in a heuristics table to obtain an estimated total number of expected proximal accesses based on an updated occupation count of the bin; and determining, based on the estimated total number of expected proximal accesses, sequentiality of the data stream to device in order to generate a policy for the cache memory.

Abstract: Memory transactions in a computing device may be scheduled by forming subsets of a set of memory transactions corresponding to memory transaction requests directed to a DRAM. Each subset may include transactions identified by the same combination of direction (read or write) and DRAM rank as each other. The transactions selected for inclusion in each subset may be determined based on efficiency. One of the subsets may be selected based on a metric applied to each subset, and the transactions in the selected subset may be sent to the DRAM.

Abstract: A content delivery system comprising one or more one management servers comprising one or more processors for executing a code of one or more management agent instances. The code comprising code instructions to monitor a plurality of delivery servers of a distributed network to update dynamically a content record listing a plurality of content objects according to availability parameter(s) of each delivery server, code instructions to receive a content request from (user) client device to retrieve requested content object(s), code instructions to select preferred delivery server(s) from the delivery servers to provide the requested content object(s) to the client device according to analysis of the availability parameter(s) of each delivery server and code instructions to provide the client device with an IP address of the selected delivery server(s) to allow the client device to retrieve the requested content object(s) via a transmission session established with the selected delivery server(s).

Abstract: Data records of a data set can be stored in a plurality of main part fragments retained in on-disk storage. A size of the data set can be compared to an available size of main system memory. All of the plurality of main part fragments can be fully loaded into the main system memory when the available size of the main system memory is larger than the size of the data set. Alternatively, one or more of the of main part fragments can be paged into the main system memory on demand in response to a data access request when the available size of the main system memory is smaller than the size of the data set and the data access request can be satisfied by providing access to a subset of the main part fragments, or access can be provided directly to the on-disk main part fragments when the data access request involves random access for projection in the data set and the available size of the main system memory is smaller than the size of the data set.

Abstract: A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

Abstract: A storage system includes a first storage device, and a second storage device retrieving stored data at higher speeds than the first storage device. The storage system further includes a feature calculation unit calculating feature data based on a data content of storage target data, a data management unit storing the storage target data and managing a storing position thereof based on the feature data calculated from the storage target data, and a duplication determination unit determining whether or not the same storage target data as the storage target data to be newly stored is already stored in the first storage device. In a case that the same storage target data as the storage target data to be newly stored is already stored in the first storage device, the data management unit stores the storage target data already stored in the first storage device into the second device.

Abstract: The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose heat metric is equal to or greater than the heat metric threshold. The adjustment of the heat metric threshold is determined by comparing a reference metric related to hits of data most recently inserted into the secondary data storage cache, to a reference metric related to hits of data most recently evicted from the secondary data storage cache; if the most recently inserted reference metric is greater than the most recently evicted reference metric, decrementing the threshold; and if the most recently inserted reference metric is less than the most recently evicted reference metric, incrementing the threshold.

Abstract: The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose heat metric is equal to or greater than the heat metric threshold. The adjustment of the heat metric threshold is determined by comparing a reference metric related to hits of data most recently inserted into the secondary data storage cache, to a reference metric related to hits of data most recently evicted from the secondary data storage cache; if the most recently inserted reference metric is greater than the most recently evicted reference metric, decrementing the threshold; and if the most recently inserted reference metric is less than the most recently evicted reference metric, incrementing the threshold.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: Embodiments disclosed herein provide a high performance content delivery system in which versions of content are cached for servicing web site requests containing the same uniform resource locator (URL). When a page is cached, certain metadata is also stored along with the page. That metadata includes a description of what extra attributes, if any, must be consulted to determine what version of content to serve in response to a request. When a request is fielded, a cache reader consults this metadata at a primary cache address, then extracts the values of attributes, if any are specified, and uses them in conjunction with the URL to search for an appropriate response at a secondary cache address. These attributes may include HTTP request headers, cookies, query string, and session variables. If no entry exists at the secondary address, the request is forwarded to a page generator at the back-end.

Abstract: Systems and methods for invalidating and regenerating pages. In one embodiment, a method can include detecting content changes in a content database including various objects. The method can include causing an invalidation generator to generate an invalidation based on the modification and communicating the invalidation to a dependency manager. A cache manager can be notified that pages in a cache might be invalidated based on the modification via a page invalidation notice. In one embodiment, a method can include receiving a page invalidation notice and sending a page regeneration request to a page generator. The method can include regenerating the cached page. The method can include forwarding the regenerated page to the cache manager replacing the cached page with the regenerated page. In one embodiment, a method can include invalidating a cached page based on a content modification and regenerating pages which might depend on the modified content.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). A first execution time needed to execute commands in a NVSM command queue is estimated, and a second execution time needed to execute commands in a disk command queue is estimated. An access command is inserted into a selected one of the NVSM command queue and the disk command queue in response to the first and second execution times, and one of the first and second execution times is updated in response to an estimated execution time of the access command.

Abstract: Embodiments of the invention relate to optimizing the storage of data in a multi-cache level environment. In one aspect, data is classified into primary and secondary cache sections. Data is differentiated based on an inherent sharing characteristic of the data within a system comprising virtual machines. The data is then placed into the classified sections of the cache storage layer and/or persistent data, reflective of how the data is shared among virtual disk images access by virtual machines.

Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.

Abstract: Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that specifies a memory address from which to retrieve data. In response to the instance of the instruction, the execution core retrieves data from the memory address and stores it in the data in the data cache, regardless of whether the data corresponding to that particular memory address is already stored in the data cache. In this manner, the data cache may be used as a prefetch buffer for data in memory buffers where coherence has not been maintained.

Abstract: A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

Abstract: An interface controller of a storage device configured to manage a write cache of the storage device responsive to changes in a voltage supply provided to the storage device. In one implementation, the interface controller reduces the size of the write cache responsive to the voltage supply dropping at or below a first threshold. The interface controller further disables write permissions to the write cache responsive the voltage supply dropping at or below a second threshold, wherein the second threshold is lower in magnitude that the first threshold. The interface controller periodically receives the voltage supply responsive to transmitting sequential requests to a servo firmware of the storage device.

Abstract: A system, method, and computer-readable medium that facilitate efficient use of cache memory in a massively parallel processing system are provided. A residency time of a data block to be stored in cache memory or a disk drive is estimated. A metric is calculated for the data block as a function of the residency time. The metric may further be calculated as a function of the data block size. One or more data blocks stored in cache memory are evaluated by comparing a respective metric of the one or more data blocks with the metric of the data block to be stored. A determination is then made to either store the data block on the disk drive or flush the one or more data blocks from the cache memory and store the data block in the cache memory. In this manner, the cache memory may be more efficiently utilized by storing smaller data blocks with lesser residency times by flushing larger data blocks with significant residency times from the cache memory.

Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Abstract: In a storage apparatus using AW technology, deterioration in I/O performance accompanying saving of data for creating a snapshot is suppressed as much as possible. When saving a snapshot image after returning a write completion response to a host computer, a storage apparatus according to the present invention performs the saving preferentially for a storage area with a low priority of snapshot image deletion.

Abstract: A storage system is migrated without stopping service provision by a host computer. By this means, in a migration-source storage system, data of the cache memory is destaged, and, next, data received from the host computer is directly written in a logical unit by bypassing the cache memory. On the other hand, in a migration-destination storage system, communication with the migration-source storage system is performed to set setting information of a logical unit of the migration object into a logical unit management table and set a writing mode for the cache memory to a cache-bypass mode. After that, the migration-source storage system blocks a path to the host computer. The migration-destination storage system receives a report of the path block from the migration-source storage system and then opens a path between the own system and the host computer.

Abstract: A method, system, and computer program product for data transfer to memory over an input/output (I/O) interconnect are provided. The method includes reading a mailbox stored on an I/O adapter in response to a request to initiate an I/O transaction. The mailbox stores a directive that defines a condition under which cache injection for data values in the I/O transaction will not be performed. The method also includes embedding a hint into the I/O transaction when the directive in the mailbox matches data received in the request, and executing the I/O transaction. The execution of the I/O transaction causes a system chipset or I/O hub for a processor receiving the I/O transaction, to directly store the data values from the I/O transaction into system memory and to suppress the cache injection of the data values into a cache memory upon presence of the hint in a header of the I/O transaction.

Abstract: In described embodiments, compressed cache storage acceleration employs compression and caching together in a combination to provide a performance gain. A layered file system includes a filter layer for the file system that selectively identifies and compresses data with the knowledge of the file structure before being stored in local cache memory or on a storage medium. Selection of compressed and uncompressed data for relatively immediate access is determined by monitoring access patterns and generating an access profile. The compressed and uncompressed data is locally stored and accessed in the cache, which might be Flash memory, to provide the performance gain.

Abstract: Systems and methods for managing cached content are disclosed. More particularly, embodiments disclosed herein may allow cached content to be updated (e.g. regenerated or replaced) in response to a notification. Specifically, embodiments disclosed herein may process a notification pertaining to content stored in a cache. Processing the notification may include locating cached content associated with the notification. After the cached content which corresponds to the notification is found, an appropriate action may be taken. For example, the cached content may be flushed from the cache or a request may be regenerated. As a result of the action, new content is generated. This new content is then used to replace or update the cached content.

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract: Based on a count of the number of dirty pages in a cache memory, the dirty pages are written from the cache memory to a storage array at a rate having a component proportional to the rate of change in the number of dirty pages in the cache memory. For example, a desired flush rate is computed by adding a first term to a second term. The first term is proportional to the rate of change in the number of dirty pages in the cache memory, and the second term is proportional to the number of dirty pages in the cache memory. The rate component has a smoothing effect on incoming I/O bursts and permits cache flushing to occur at a higher rate closer to the maximum storage array throughput without a significant detrimental impact on client application performance.

Abstract: A storage controller comprises a cache storage used as a cache of an external storage and a control processor coupled to the cache storage. The control processor comprises an internal access function and an external access function. The internal access function transmits a read command to the cache storage. The cache storage determines whether the read target data complying with the read command is stored in a physical storage device or not. If the result of the determination is negative, the external access function is executed while, if the result of the determination is positive, the external access function is not executed because the cache storage transmits the read target data to the internal access function without issuing a request to the external access function.

Abstract: Systems and methods for invalidating and regenerating pages. In one embodiment, a method can include detecting content changes in a content database including various objects. The method can include causing an invalidation generator to generate an invalidation based on the modification and communicating the invalidation to a dependency manager. A cache manager can be notified that pages in a cache might be invalidated based on the modification via a page invalidation notice. In some embodiments, the content change can affect a set of objects which can be defined by an attribute of the objects. The content change can be the creation or deletion of some object(s) in the content database. The cached page can be regenerated during which various dependencies of the regenerated page can be discovered.

Abstract: Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored.

Abstract: A method and structure for processing an application program on a computer. In a memory of the computer executing the application, an in-memory cache structure is provided for normally temporarily storing data produced in the processing. An in-memory storage outside the in-memory cache structure is provided in the memory, for by-passing the in-memory cache structure for temporarily storing data under a predetermined condition. A sensor detects an amount of usage of the in-memory cache structure used to store data during the processing. When it is detected that the amount of usage exceeds the predetermined threshold, the processing is controlled so that the data produced in the processing is stored in the in-memory storage rather than in the in-memory cache structure.

Abstract: Systems and methods for invalidating and regenerating pages. In one embodiment, a method can include detecting content changes in a content database including various objects. The method can include causing an invalidation generator to generate an invalidation based on the modification and communicating the invalidation to a dependency manager. A cache manager can be notified that pages in a cache might be invalidated based on the modification via a page invalidation notice. In one embodiment, a method can include receiving a page invalidation notice and sending a page regeneration request to a page generator. The method can include regenerating the cached page. The method can include forwarding the regenerated page to the cache manager replacing the cached page with the regenerated page. In one embodiment, a method can include invalidating a cached page based on a content modification and regenerating pages which might depend on the modified content.

Abstract: A method of providing history based done logic includes receiving a cache line in a L2 cache; determining if the cache line has a history of access at least three times on a previous call into the L2 cache; providing the cache line directly to a processor if the history of access was less then the at least three times; and loading the cache line into an L1 cache if the history of access was the at least three times.

Abstract: An apparatus and method are described for implementing an exclusive lower level cache (LLC) policy within a computer processor. For example, one embodiment of a computer processor comprises: a mid-level cache circuit (MLC) for storing a first set of cache lines containing instructions and/or data; a lower level cache circuit (LLC) for storing a second set of cache lines of instructions and/or data; and an insertion circuit for implementing a policy for inserting or replacing cache lines within the LLC based on values of use recency and use frequency associated with the lines.

Abstract: According to method of data processing in a multiprocessor data processing system, in response to a processor request to modify a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a data-claim-partial request that requests permission to promote only the target granule of the target cache line to a unique copy with an intent to modify the target granule. In response to a combined response to the data-claim-partial request indicating success (the combined response representing a system-wide response to the data-claim-partial-request), the processing unit promotes only the target granule of the target cache line to a unique copy by updating a coherency state of the target granule and retaining a coherency state of at least one other granule of the target cache line.

Abstract: A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract: A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed.

Abstract: A method includes determining if a data processing instruction is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a cache.

Abstract: A method, system, computer program product, and computer program storage device for receiving and processing I/O requests from a host device and providing data consistency in both a primary site and a secondary site, while migrating a SRC (Synchronous Peer to Peer Remote Copy) from a backend storage subsystem to a storage virtualization appliance. While transferring SRC from the backend storage subsystem to the storage virtualization appliance, all new I/O requests are saved in both a primary cache memory and a secondary cache memory, allowing a time window during which the SRC at the backend storage subsystem can be stopped and the secondary storage device is made as a readable and writable medium. The primary cache memory and secondary cache memory operates separately on each I/O request in write-through, read-write or no-flush mode.

Abstract: A host device is provided comprising an interface configured to communicate with a storage device having a public memory area and a private memory area, wherein the public memory area stores a virtual file that is associated with content stored in the private memory area. The host device also comprises a cache, a host application, and a server. The server is configured to receive a request for the virtual file from the host application, send a request to the storage device for the virtual file, receive the content associated with the virtual file from the private memory area of the storage device, wherein the content is received by bypassing the cache, generate a response to the request from the host application, the response including the content, and send the response to the host application. In one embodiment, the server is a hypertext transfer protocol (HTTP) server.

Abstract: According to one embodiment, an information reproducing apparatus includes a memory, a decoder, an intermediate memory which is disposed between the memory and the decoder and which temporarily stores, in succession, the data that are supplied from the memory and then outputs the data to the decoder, switching circuit for switching an output of the memory to one of the decoder and the intermediate memory, memory management circuit for managing arrangement information of the data that are stored in the memory, determination circuit for determining whether the data that are stored in the memory are arranged in physically discontinuous memory areas of the memory, and switching control circuit for switching, in a case where the determination circuit determines that the data are arranged in the physically divided memory areas, the switching circuit in a manner to input the data output from the memory to the decoder via the intermediate memory.

Abstract: A computer-implemented method for controlling initialization of a fingerprint cache for data deduplication associated with a single-instance-storage computing subsystem may comprise: 1) detecting a request to store a data selection to the single-instance-storage computing subsystem, 2) leveraging a client-side fingerprint cache associated with a previous storage of the data selection to the single-instance-storage computing subsystem to initialize a new client-side fingerprint cache, and 3) utilizing the new client-side fingerprint cache for data deduplication associated with the request to store the data selection to the single-instance-storage computing subsystem. Other exemplary methods of controlling initialization of a fingerprint cache for data deduplication, as well as corresponding exemplary systems and computer-readable-storage media, are also disclosed.

Abstract: A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. Accordingly, the time taken in programming can be reduced without increasing a unit of program in a multilevel flash memory, thereby improving performance in a multilevel program of a nonvolatile semiconductor memory device.

Abstract: A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.