Distributed Directories, E.g., Linked Lists Of Caches, Etc. (epo) Patents (Class 711/E12.03)
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Patent number: 8843691Abstract: Methods and systems for the prioritized erasure of data blocks in a flash storage device are provided. A data block in the flash storage device is selected for erasure based upon the number of valid data segments therein, thereby minimizing the number of data segments that are carried over to another data block before erasing the selected data block. The overhead of write operations in the flash storage device is therefore greatly reduced, and the overall performance thereof greatly increased. A method for managing memory operations in a flash storage device having a plurality of data blocks comprises the steps of selecting one of the plurality of data blocks for erasure based upon a number of valid data segments therein, and erasing the selected one of the plurality of data blocks.Type: GrantFiled: December 23, 2008Date of Patent: September 23, 2014Assignee: STEC, Inc.Inventors: William Calvert, Stephen Russell Boorman, Simon Mark Haynes
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Patent number: 8762651Abstract: Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.Type: GrantFiled: June 23, 2010Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Michael A. Blake, Garrett M. Drapala, Pak-Kin Mak, Vesselina K. Papazova, Craig R. Walters
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Patent number: 8677068Abstract: Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.Type: GrantFiled: June 17, 2011Date of Patent: March 18, 2014Assignee: LSI CorporationInventors: Timothy Lawrence Canepa, Carlton Gene Amdahl
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Patent number: 8316210Abstract: The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address.Type: GrantFiled: April 8, 2010Date of Patent: November 20, 2012Assignee: Silicon Motion, Inc.Inventor: Jen-Wen Lin
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Patent number: 8180970Abstract: A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.Type: GrantFiled: February 22, 2008Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Arthur J. O'Neill, Jr., Michael F. Fee, Pak-kin Mak
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Patent number: 8151062Abstract: Systems and methods that designate read/write consistency models based on requirements of a distributed store to increase performance or scale. Such sever loads can be determined via a plurality of mechanisms, including delays in responses by the primary node; setting predetermined threshold limits that if exceeded results in contacting secondary nodes; polling services of the distributed cache periodically and maintaining track of loads on the servers, and the like. The weak or scalable read can occur when read requests are directed to a secondary node, and upon over loading of the primary node.Type: GrantFiled: April 30, 2009Date of Patent: April 3, 2012Assignee: Microsoft CorporationInventors: Muralidhar Krishnaprasad, Anil K. Nori, Amit Kumar Yadav
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Patent number: 7996604Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.Type: GrantFiled: October 25, 2005Date of Patent: August 9, 2011Assignee: Xilinx, Inc.Inventors: Gautam Nag Kavipurapu, Sweatha Rao, Chris Althouse
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Patent number: 7853760Abstract: A method for managing a memory system for large data volumes includes providing a central memory management system comprising a memory management interface between applications and a memory of a programmed computer, maintaining a global priority list of data buffers allocated by the applications, storing decompressed data of the data buffers into a cache which is managed by the central memory management system using a separate priority list, and accessing the decompressed data of the data buffers in the cache.Type: GrantFiled: July 10, 2007Date of Patent: December 14, 2010Assignee: Siemens CorporationInventors: Gianluca Paladini, Thomas Moeller
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Patent number: 7822929Abstract: The invention facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.Type: GrantFiled: April 27, 2004Date of Patent: October 26, 2010Assignee: Intel CorporationInventor: Ling Cen
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Patent number: 7802066Abstract: An efficient memory management method for handling large data volumes, comprising a memory management interface between a plurality of applications and a physical memory, determining a priority list of buffers accessed by the plurality of applications, providing efficient disk paging based on the priority list, ensuring sufficient physical memory is available, sharing managed data buffers among a plurality of applications, mapping and unmapping data buffers in virtual memory efficiently to overcome the limits of virtual address space.Type: GrantFiled: February 8, 2006Date of Patent: September 21, 2010Assignee: Siemens Medical Solutions USA, Inc.Inventors: Gianluca Paladini, Thomas Moeller
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Publication number: 20100106914Abstract: Systems and methods that designate read/write consistency models based on requirements of a distributed store to increase performance or scale. Such sever loads can be determined via a plurality of mechanisms, including delays in responses by the primary node; setting predetermined threshold limits that if exceeded results in contacting secondary nodes; polling services of the distributed cache periodically and maintaining track of loads on the servers, and the like. The weak or scalable read can occur when read requests are directed to a secondary node, and upon over loading of the primary node.Type: ApplicationFiled: April 30, 2009Publication date: April 29, 2010Applicant: Microsoft CorporationInventors: Muralidhar Krishnaprasad, Anil K. Nori, Amit Kumar Yadav