Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

Abstract: A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface.

Abstract: A data processing apparatus includes an operation unit, a writable and readable volatile register, a writable and readable nonvolatile memory, first and second writing units and a write-back unit. The operation unit performs an arithmetic operation and a logical operation. The writable and readable volatile register stores data used in the operations performed by the operation unit. The writable and readable nonvolatile memory stores the data in parallel with the volatile register. The data stored in the nonvolatile memory is the data stored in the volatile register. The first writing unit writes the data in the volatile register. The second writing unit writes the data in the nonvolatile memory in parallel with the first writing unit every time the data is written in the volatile register. The write-back unit writes back the data stored in the nonvolatile memory to the volatile register when a power supply is turned on.

Abstract: A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses.

Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.

Abstract: A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.

Abstract: Separate buffers store snoop writes and direct memory access writes. A multiplexer selects one of these for input to a FIFO buffer. The FIFO buffer is split into multiple FIFOs including: a command FIFO; an address FIFO; and write data FIFO. Each snoop command is compared with an allocated line set and way and deleted on a match to avoid data corruption. Each snoop command is also compared with a victim address. If the snoop address matches victim address logic redirects the snoop command to a victim buffer and the snoop write is completed in the victim buffer.

Abstract: Embodiments that facilitate the fair and dynamic distribution of disk input/output (IO) bandwidth are disclosed. In accordance with one embodiment, the method includes organizing one or more disk IO time intervals into one or more queues. The method further includes allocating a disk IO time interval to each queue. The allocation of a disk IO time interval to each queue is accomplished by equally distributing a disk IO cycle based on the number of queues. The one or more disk IO requests are then processed during the corresponding disk IO time interval.

Abstract: The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.

Abstract: In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

Abstract: A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. A page is reserved in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid and contain the corresponding address of the reserved page.

Abstract: To reduce power consumption, an MFP includes first to third HDDs of different storage capacities to store data, a writing portion to write received data to one of the first to third HDDs, a mode switching portion to change operating modes including the normal, stand-by, and sleep operating modes, each mode being driven by a different load, and a controller to control driving of the first to third HDDs. The controller includes a selecting portion to select one HDD from the first to third HDDs, which is predetermined in correspondence to the switched operating mode, and a drive controlling portion to drive the selected HDD, while suspending any HDD in operation other than the driven HDD.

Abstract: Proposed is a storage controller and its control method for speeding up the processing time in response to a command in a simple manner while reducing the load of a controller that received a command targeting a non-associated logical volume. This storage controller includes a plurality of controllers for controlling the input and output of data to and from a corresponding logical unit based on a command retained in a local memory, and the local memory stores association information representing the correspondence of the logical units and the controllers and address information of the local memory in each of the controllers of a self-system and another-system.

Abstract: A storage system, such as a storage server, receives a list of volume block numbers (VBNs) in a multi-block read request. In response to the request, the storage system coalesces the list into one or more chains of sequential VBNs. The storage system issues each chain to the storage subsystem.

Abstract: A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.

Abstract: A storage system is arranged to speed up the operation and easily duplicate data without the capacity of the cache memory being so large even if lots of host computers are connected with the storage system. This storage system includes channel adapters, disk drives, disk adapters, and network switches. Further, the front side cache memories connected with the channel adapters and the back side cache memories connected with the disk adapters are provided as two layered cache system. When a request for writing data is given to the storage system by the host computer, the data is written in both the front side cache memory and the back side cache memory. The write data is duplicated by placing the write data in one of the front side cache memories and one of the back side cache memories or two of the back side cache memories.

Abstract: A recording medium, such as a high-density and/or optical recording medium including segment information recorded thereon, and apparatus and methods for recording to and reproducing from the recording medium, in order to improve data protection, data management and/or reproduction compatibility. The recording medium may contain at least one segment area which is an area on the disc controlled by a plurality of valid PACs and if the designated segment areas overlap with one another, control information of the respective PACs which control the overlapped area may be applied to control the overlapped area.

Abstract: A system controller includes an output unit which transfers an access request from an access source coupled to the system controller to an other system controller; a local snoop control unit that determines whether a destination of the access request from the access source is a local memory unit coupled to the system controller, and locks the destination when the destination is the local memory unit; a receiving unit which receives the access request from the output unit and an access request from an other system controller; a global snoop control unit which sends a response indicating whether the access request is executable or not, and controls locking of the destination of the access request when the destination is the local memory unit; and an access processing unit which unlocks the locking and accesses the memory unit when the access request from the access source becomes executable.

Abstract: In one embodiment, an image forming device includes a storage device for storing data. A storage access manager is configured to coordinate access to the storage device from a plurality of client devices that communicate with the storage device using at least one uncoordinating communication protocol.

Abstract: Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.

Abstract: A processing system includes a local or local storage and a number of remote or remote storage systems that store data mirroring that maintained by the local storage system. Data that is written, changed, deleted or other wise modified by the local storage system is periodically sent to the remote storage systems to update the mirroring data maintained by each.

Abstract: A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.

Abstract: A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).

Abstract: A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.

Abstract: A recording medium, such as a high-density and/or optical recording medium including segment information recorded thereon, and apparatus and methods for recording to and reproducing from the recording medium, in order to improve data protection, data management and/or reproduction compatibility. The recording medium may contain at least one segment area which is an area on the disc controlled by a plurality of valid PACs and if the designated segment areas overlap with one another, control information of the respective PACs which control the overlapped area may be applied to control the overlapped area.

Abstract: Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the pointer from the detected entry. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus for reading from a physical storage-device array including a plurality of storage devices. The physical storage-device array has a plurality of sector levels, each sector level containing one sector on each storage device in the array at corresponding addresses on across the storage devices. The apparatus includes: (1) a memory adapted to store two or more profiles, each profile defining (i) a virtual array associated with a selected set of the storage devices and (ii) one or more parameters used for accessing information from the virtual array; (2) a buffer (i) having a first portion and a second portion and (ii) coupled to receive data from the storage devices; and (3) a state machine (i) coupled to the buffer and the memory and (ii) adapted to generate two or more successive pairs of instructions.

Abstract: A method includes detecting a bus transaction on a system interconnect of a data processing system having at least two masters; determining whether the bus transaction is one of a first type of bus transaction or a second type of bus transaction, where the determining is based upon a burst attribute of the bus transaction; performing a cache coherency operation for the bus transaction in response to the determining that the bus transaction is of the first type, where the performing the cache coherency operation includes searching at least one cache of the data processing system to determine whether the at least one cache contains data associated with a memory address the bus transaction; and not performing cache coherency operations for the bus transaction in response to the determining that the bus transaction is of the second type.

Abstract: A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idling SPE stores data stored in the global memory and used by the processor core of the running SPE, before the data is used by the processor core of the running SPE. The DMA module of the running SPE reads the data from the local memory of the idling SPE, and transfers the data to the processor core of the running SPE.

Abstract: A storage controller for handling data stream having data integrity field (DIF) and method thereof. The storage controller comprises a host-side I/O controller for receiving a data stream from a host entity, a host-side I/O controller for connecting to a physical storage device, and, a central processing circuitry having at least one DIF I/O interface for handling DIF data so as to reduce the number of memory access to the main memory of the storage controller.

Abstract: A generic RAID engine system accepts an access request, accepts a metadata input comprising a layout description and, optionally, a plurality of resource optimization objectives, accepts a dynamic input comprising a dynamic state of an I/O stack comprising the generic RAID engine and a fault configuration of a plurality of storage devices in the I/O stack, and accepts RAID code input comprising information about the RAID code used by the I/O stack. The metadata input, the dynamic input, and the RAID code input are utilized to transform the access request into individual device reads and individual device writes such that RAID code relationships for the storage devices are maintained at all times. An optional optimizer module selects strategies that meet the resource optimization objectives.

Abstract: A computer implemented tool is provided for assisting in the mapping of a computer program to a data processing apparatus 2 wherein multiple physical instances of a logical variable in the computer program are required. A computer program 60 is provided as the input to the tool which analyses the data flow of the program and identifies multiple physical instance requirement for logical variables. The tool adds mapping support commands, such as instantiation commands, DMA move commands and the like as necessary to support the mapping of the computer program to a data processing apparatus 2.

Abstract: A system may include a processor node, and may also include an input/output (I/O) node including a processor and an I/O device. The processor and I/O nodes may each include a respective cache memory configured to cache a system memory and a respective cache coherence controller. The system may further include interconnect through which the nodes may communicate. In response to detecting a request for the I/O device to perform a DMA write operation to a coherence unit of the I/O node's respective cache memory, and in response to determining that the coherence unit is not modified with respect to the system memory and no other cache memory within the system has read or write permission corresponding to a copy of the coherence unit, the I/O node's respective cache coherence controller may grant write permission but not read permission for the coherence unit to the I/O node's respective cache memory.