Abstract: One or more techniques are provided for restricting access to protected modes of operation in a memory device. In one embodiment, detection circuitry is provided and configured to receive and evaluate a protected mode entry sequence for accessing a protected mode of operation. The detection circuitry may be further configured to temporarily enable an output pin on a serial interface between the memory device and a master device to receive inputs, such that a entry sequence may be entered on both the input and output pins. In another embodiment, the detection circuitry may be enabled only if a security code is first provided, thus requiring both the correct security code and entry sequence before protected mode access is allowed. The memory device may also include a parallel NAND memory array, and detection logic may be further configured to enable a serial-to-parallel NAND translator once protected mode access is allowed.

Abstract: A computer-based systems and methods for task processing in a computing device are provided. A method includes the step of entering a slice mode for at least one task, the entering comprising reserving one or more portions of a cache memory to yield a slice cache memory for the task. The method also includes the step of storing a slice in the slice cache memory, wherein the slice comprises at least one program residing in at least one memory space outside of the slice cache memory and associated with the at least one task. The method further includes the step of processing the at least one task utilizing the at least one program by accessing the at least one slice cache memory until the slice mode is terminated.

Abstract: A system and method optimizing data throughput to a processor from a storage device having sequential data access capabilities where the processor enables its data cache for memory operations involving the storage device. The system includes a processor coupled to the data storage device, e.g., a NAND flash memory. The processor establishes an address window used as a cache (CW) for reading data from the flash memory and also establishes a non-cacheable address window (NCW) for commands, address delivery and writes to the flash memory. The CW is sized to be larger than the processor data cache to ensure that reads from the flash memory always encounter a cache-miss so that read data is obtained directly from the flash memory. By reading through the CW from the flash memory, the processor takes advantage of bursting, pipelining and data prefetch efficiencies which significantly increase data throughput.

Abstract: A technique for optimizing grace period detection in a uniprocessor environment. An update operation is performed on a data element that is shared with non-preemptible readers of the data element. A call is issued to a synchronous grace period detection method. The synchronous grace period detection method performs synchronous grace period detection and returns from the call if the data processing system implements a multi-processor environment at the time of the call. The synchronous grace period detection determines the end of a grace period in which the readers have passed through a quiescent state and cannot be maintaining references to the pre-update view of the shared data. The synchronous grace period detection method returns from the call without performing grace period detection if the data processing system implements a uniprocessor environment at the time of the call.

Abstract: A PCI Express (PCIe) computer system utilizes address translation services to translate virtual addresses from I/O device adaptors to physical addresses of system memory. A combined memory controller and host bridge uses a translation agent to convert the I/O addresses via translation control entries (TCEs) in a TCE table (also known as an address translation and protection table). Some of the I/O device adaptors have address translation caches for local storage of TCEs. The TCE definition includes a new non-cacheable control bit which is set active in the TCE table when the TCE is in the process of being invalidated. The memory controller prevents further caching of the TCE while the non-cacheable control bit is active. A further implementation utilizes a change-in-progress control bit of the TCE to indicate that the TCE is in the process of being changed to allow simultaneous invalidation of the previously TCE information.

Abstract: A computing system supports a virtualization platform with dedicated cache access. The computing system is configured for usage with a memory and a cache and comprises an instruction decoder configured to decode a cache-line allocation instruction and control logic. The control logic is coupled to the instruction decoder and controls the computing system to execute a cache-line allocation instruction that loads portions of data and code regions of the memory into dedicated cache-lines of the cache which are exempted from eviction according to a cache controller replacement policy.

Abstract: A system or method for reestablishing data consistency between data volume P and its real time or near real time copy volume S. When volumes P and S enter a state of data inconsistency, data consistency can be restored through use of roll-back and/or roll-forward logs. The roll-forward log stores new data to be written to volume P. The roll-back log stores existing data of volume S before the existing data of volume S is overwritten with new data. As will be more fully described below, the roll-back log can be used to incrementally restore volume S to a prior data state in reverse chronological order, while a roll-forward log can be used to incrementally restore volume S in forward chronological to equal the data state of volume P.

Abstract: Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

Abstract: An information processing apparatus is configured to be backed up by a battery so that information in a main memory of the apparatus can be retained when a power supply for the apparatus is stopped. The apparatus stores kernel information in a kernel information table at a time of an initial program loading so that the kernel information stored in the kernel information table can be delivered to a kernel for restarting a program. The program can be started by receiving the kernel information from the kernel information table without retrieving the program from a memory medium or re-generating the kernel information. The apparatus with an operating system that has a relocation function for use in a vehicle can thus have a reduced system startup time.