Abstract: Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.

Abstract: Methods and apparatuses are provided for data resource provision. A method may include receiving a request for a first data resource. The request may include an indication of an additional data resource that may be requested in a future request. The method may further include determining the indicated additional data resource. The method may additionally include causing caching of the additional data resource in preparation for a future request for the additional data resource. Corresponding apparatuses are also provided.

Abstract: Various embodiments of the present invention provide a system for caching information in a multi-process environment. The system includes a processor. A shared memory is communicatively coupled to the processor. The shared memory includes a set of data. A writer process is communicatively coupled to the shared memory. The write process reads and updates the set of data. A plurality of reader processes is communicatively coupled to the shared memory. Each reader process reads at least part of the set of data directly from the shared memory and sends a set of update information to the writer process. The writer process then updates the set of data stored in the shared memory based on the set of update information.

Abstract: A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register.

Abstract: A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number target data entries in the data segment.

Abstract: Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request.

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Abstract: Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.

Abstract: Updated queries are maintained in a cache. A search engine receives a query from a user through a query entry field. The search engine determines search results corresponding to the user query. A new entry mapping the user query to the search results is generated in a cache of results. A web crawler retrieves a new batch of documents for a particular document collection. A search index associated with a search engine is updated to reflect new documents in the document collection. A search engine of queries receives documents from the new batch of documents as inputs. Based on the received documents, the search engine of queries determines which of the queries would have returned the documents as relevant in a search. These queries are determined to be stale and invalidated.

Abstract: Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who stores the first data in an alternative modified state. Other embodiments are also described.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: A cache device comprises: data memory that includes a plurality of ways for storing a part of data of a main memory; tag memory that includes a plurality of ways, each of which is for storing tag contained in address of data recorded in each way of the data memory; comparison circuit that decides whether tag contained in address to be accessed agrees with the tag recorded in the tag memory or not; next address generation circuit that calculates address to be accessed next time as second address by referring to first address to be accessed at present time; and tag reading control circuit that pre-reads tag corresponding to index of the second address from the tag memory and ceases to read tags hereafter from the tag memory in a case where the tag contained in the second address agrees with the pre-read tag.

Abstract: A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.

Abstract: One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program.

Abstract: Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations.

Abstract: An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract: A system supporting producer-consumer pre-fetch communications includes a first processor, wherein the first processor is a producer node, and a second processor, wherein the second processor is a consumer node. The system further includes a data subscribe mechanism for performing a data subscribe operation at the consumer node, wherein the data subscribe operation records that a memory address is subscribed at the consumer node, a data publish mechanism for performing a data publish operation at the producer nod; wherein the data publish operation sends data of the memory address from the producer node to the consumer node if the memory address is subscribed at the consumer node, and a communication network coupled to the producer node and the consumer node for enabling communicating between the producer node and the consumer node.

Abstract: Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.

Abstract: An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

Abstract: Systems and methods disclosed permit flexible optimization of printer cache memories by specify criteria for determining cache membership for objects derived from a print data streams, wherein the objects may be associated with distinct reference counts. In some embodiments, the method may comprise the steps of: assigning an initial value to the reference count associated with an object, if the object is not present in the cache; incrementing the reference count by a first weight, if the object is already present in the cache; decrementing the reference count by a second weight, in response to an end-of-page event; and removing the object from the cache if the reference count is below a threshold.

Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

Abstract: Included are embodiments for facilitating operation of an input/output (I/O) link. At least one embodiment of a method includes receiving a first cache line from a memory controller and determining whether the first cache line corresponds to a first portion of data. Some embodiments include, when the first cache line corresponds to the first portion of data, determining whether a second cache line is received and when the second cache line is not received, processing the first cache line. Similarly, some embodiments include when the first cache line does not correspond to the first portion of data, waiting for a cache line that does correspond to the first portion of data.

Abstract: One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

Abstract: A multiprocessor system includes cache systems arranged in correspondence with processor cores, and each including a cache memory which stores a cache line, a shared memory shared by the processor cores, and an arbiter configured to arbitrate access requests sent from the cache systems to the shared memory, and configured to send the arbitrated access request to the shared memory and the cache systems. The cache system includes a determination circuit configured to determine an access state using line information and the access request sent from the arbiter, a flag circuit configured to set a flag for each cache line based on a determination result of the determination circuit, and a control circuit configured to confirm the flag when a read access or a write access is made to a cache line held in the cache memory, and configured to detect a violation access based on the flag.

Abstract: Techniques for caching images are presented. A matrix of pixel values represents an image. A diagonal of the matrix is used as an array of numbers representing an index value. The index value is compared to existing index values housed in a cache. When no match is present, the index value is inserted into the cache and the corresponding image associated with the inserted index value acquired. When a match is present no action is taken on the index values of the cache.

Abstract: Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.

Abstract: An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counters). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Abstract: Systems and methods that supply poll based notification system in a distributed cache, for tracking changes to cache items. Local caches on the client can employ the notification system to keep the local objects in sync with the backend cache service; and can further dynamically adjust the “scope” of notifications required based on the number and distribution of keys in the local cache. The server can maintain the changes in an efficient fashion (in blocks) and returns the changes to clients that perform the appropriate filtering. Notifications can be associated with a session and/or an application.

Abstract: Nodes include controllers, management servers, and storages. Each of the controllers includes a first mapping table indicating management servers corresponding to logical extents that compose a logical volume that is provided for a host. The management servers include second mapping tables indicating which nodes include storages that store logical extents corresponding to the management servers. The storages include third mapping tables indicating which physical extents of physical volumes included in the storages store the logical extents.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.

Abstract: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: A method and system to determine whether a web page has been cached is provided. An example system comprises a cookie generator, a cookie distributor, and a cookie evaluator. The cookie distributor may be configured to provide the code to a client system, in response to a request for web content from the client system. A value of the code to be updated at the client system in response to the client system initiating a request for the web content. The cookie evaluator may be configured to compare a value of the code to the default value. The cached status detector may be configured to use a result of the comparing to determine a cached status of the web content, the cached status to indicate whether the web content has been cached by the client system.

Abstract: Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Abstract: In a recording controller, an invalidation-request issuing unit, when a second data is recorded on a recording location for a first data that is to be recorded in a memory and a third data corresponding to the second data is recorded in the cache, issues an invalidation request for invalidating the third data, and a notifying unit, when the third data is invalidated, outputs data for identifying a recording request for the first data to an output source of the recording request, and notifies to the output source that recording of the first data is completed.

Abstract: An apparatus and method provide persistent data during a user session on a networked computer system. A global data cache is divided into three sections: trusted, protected, and unprotected. An authorization mechanism stores and retrieves authorization data from the trusted section of the global data store. A common session manager stores and retrieves data from the protected and unprotected sections of the global data cache. Using the authorization mechanism, software applications may verify that a user is authorized without prompting the user for authorization information. Using the common session manager, software applications may store and retrieve data to and from the global data store, allowing the sharing of data during a user session. After the user session terminates, the data in the global data cache corresponding to the user session is invalidated.