For Multiprocessing Or Multitasking (epo) Patents (Class 711/E12.039)
  • Patent number: 8966183
    Abstract: A cache management system employs a replacement policy in a manner that manages concurrent accesses to cache. The cache management system comprises a cache, a replacement policy storage for storing replacement statuses of cache lines of the cache, and an update module. The update module, comprising access filtering and a concurrent update handling, determines how updates to the replacement policy storage are handled. In a multi-threaded compute environment, a concurrent access to shared cache causes a selective update to the replacement policy storage.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian C. Grayson, Jyotsna S. Kartha, Kathryn C. Stacer
  • Patent number: 8904113
    Abstract: Techniques, systems and an article of manufacture for caching in a virtualized computing environment. A method includes enforcing a host page cache on a host physical machine to store only base image data, and enforcing each of at least one guest page cache on a corresponding guest virtual machine to store only data generated by the guest virtual machine after the guest virtual machine is launched, wherein each guest virtual machine is implemented on the host physical machine.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Han Chen, Hui Lei, Zhe Zhang
  • Patent number: 8892820
    Abstract: Disclosed is a storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from the solid-state disk rather than initiating a network transaction.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: November 18, 2014
    Assignee: NetApp, Inc.
    Inventors: Robert E. Ober, Bret S. Weber, Robert W. Warren, Jr.
  • Patent number: 8874856
    Abstract: A false sharing detecting apparatus for analyzing a multi-thread application, the false sharing detecting apparatus includes an operation set detecting unit configured to detect an operation set having a chance of causing performance degradation due to false sharing, and a probability calculation unit configured to calculate a first probability defined as a probability that the detected operation set is to be executed according to an execution pattern causing performance degradation due to false sharing, and calculate a second probability based on the calculated first probability. The second probability is defined as a probability that performance degradation due to false sharing occurs with respect to an operation included in the detected operation set.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hyun Cho, Sung-Do Moon
  • Patent number: 8806101
    Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis
  • Patent number: 8639884
    Abstract: Systems and methods are disclosed for multi-threading computer systems. In a computer system executing multiple program threads in a processing unit, a first load/store execution unit is configured to handle instructions from a first program thread and a second load/store execution unit is configured to handle instructions from a second program thread. When the computer system executing a single program thread, the first and second load/store execution units are reconfigured to handle instructions from the single program thread, and a Level 1 (L1) data cache is reconfigured with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: January 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thang M. Tran
  • Publication number: 20130132674
    Abstract: A data storage system having at least one cache and at least two processors balances the load of data access operations by directing certain processes in each data access operation to one of the processors. Each processor may be optimized for its specific processes. One processor may be dedicated to receiving and servicing data access requests; another processor may be dedicated to background tasks and cache management.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Applicant: LSI CORPORATION
    Inventor: Kapil Sundrani
  • Patent number: 8443148
    Abstract: Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 26, 2010
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: James R. Vash, Bongjin Jung, Rishan Tan
  • Publication number: 20120272006
    Abstract: To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 25, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: William C. Moyer
  • Patent number: 8266379
    Abstract: A multithreaded processor includes multiple level-1 program caches and multiple level-1 data caches to decrease the likelihood of cache misses after thread switches. By using multiple level-1 caches, execution of a first thread does not cause instructions or data cached for a second thread to be replaced. Thus, when the second thread is being executed the occurrence of cache misses is reduced.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies AG
    Inventor: Hee Choul Lee
  • Patent number: 8230180
    Abstract: A method and apparatus are provided for sharing multipath-accessible memory between a plurality of processors, the method including connecting the plurality of processors in read/write communication to a same shared memory region; connecting the plurality of processors in read communication to a same semaphore area; selectably connecting one of the plurality of processors in write communication to the same semaphore area; exchanging shared memory access command messages between two processors for negotiating access to the same shared memory region; and storing protected variables indicative of the currently negotiated access to the same shared memory region in the same semaphore area, wherein the shared memory region has a channel relative to each processor, each channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Lak Kim, Im Bum Oh, Kyoung Heon Jeong, Young Eun Park, Chul Min Jo, Sang Hyun Lee
  • Publication number: 20120179875
    Abstract: A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 12, 2012
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Gad Sheaffer, Quinn Jacobson
  • Publication number: 20120173819
    Abstract: Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.
    Type: Application
    Filed: December 29, 2010
    Publication date: July 5, 2012
    Inventor: Yan Solihin
  • Patent number: 8180967
    Abstract: Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 15, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Haitham H. Akkary, Konrad Lai
  • Patent number: 8099557
    Abstract: In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: January 17, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John D. McCalpin, Patrick N. Conway
  • Publication number: 20110314225
    Abstract: In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor.
    Type: Application
    Filed: February 12, 2010
    Publication date: December 22, 2011
    Inventors: Kosuke Nishihara, Kazuhisa Ishizaka
  • Publication number: 20110191542
    Abstract: Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed.
    Type: Application
    Filed: December 26, 2010
    Publication date: August 4, 2011
    Inventors: James R. Vash, Bongjin Jung, Rishan Tan
  • Publication number: 20110131377
    Abstract: A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Scott Gray, Nicholas Wilt
  • Patent number: 7925842
    Abstract: A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a system call to request allocation of backing storage in physical memory for global shared memory accessible to all of the multiple tasks within the parallel job, where the global shared memory is in a global address space defined by a range of effective addresses. Each task among the multiple tasks receives an indication that the allocation requested by the system call was successful only if the global address space for that task was previously reserved and backing storage for the global shared memory has not already been allocated.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Robert S. Blackmore, Ramakrishnan Rajamony, William J. Starke
  • Patent number: 7921261
    Abstract: A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a respective system call to request reservation, without allocation of backing storage in physical memory, of a global address space defined by a range of effective addresses as global shared memory accessible to all of the multiple tasks within the parallel job. At least two of the tasks within the parallel job allocate global address spaces including a same effective address.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert S. Blackmore, Ramakrishnan Rajamony
  • Patent number: 7895400
    Abstract: Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 22, 2011
    Assignee: Oracle America, Inc.
    Inventors: Brian W. O'Krafka, Pranay Koka, Robert J. Kroeger
  • Patent number: 7877565
    Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: January 25, 2011
    Assignee: NVIDIA Corporation
    Inventors: Roger L. Allen, Cass W. Everitt, Henry Packard Moreton, Thomas H. Kong, Simon S. Moy
  • Patent number: 7840759
    Abstract: Methods and systems for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores are provided. Embodiments include receiving from a processor core a request to load a cache line in the shared cache; determining whether the shared cache is full; determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Marcus L. Kornegay, Ngan Pham
  • Patent number: 7831778
    Abstract: A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: November 9, 2010
    Assignee: Silicon Image, Inc.
    Inventors: Myung Rai Cho, Dongyun Lee, Alan Ruberg
  • Patent number: 7818504
    Abstract: A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derrin M. Berger, Michael A. Blake, Garrett M Drapala, Pak-kin Mak
  • Patent number: 7774564
    Abstract: Disclosed is a multiprocessor system using a plurality of multi-chip packages mounted with at least one processor and at least one memory, wherein: the number of memory access to the memory by the processor is recorded, and if the number of memory access across different multi-chip packages exceeds the number of memory access within the same multi-chip package, the memory contents are swapped. A memory access load distributing method in a multiprocessor system is also disclosed.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: August 10, 2010
    Assignee: NEC Corporation
    Inventor: Eiichiro Kawaguchi
  • Patent number: 7747996
    Abstract: A method to enabling interoperability of a locking synchronization method with a lock-free synchronization method in a multi-threaded environment is presented. The method examines a class file for mutable fields contained in critical code sections. The mutable fields are transferred to a shadow record and a pointer is substituted in the class field for each transferred mutable field. Code is altered so that the lock-free synchronization method is used if a lock is not held on the object. Atomic compare and swap operations are employed after mutable fields are updated during execution of the lock-free synchronization method.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: June 29, 2010
    Assignee: Oracle America, Inc.
    Inventor: David Dice
  • Publication number: 20100083120
    Abstract: There is provided a storage system including one or more LDEVs, one or more processors, a local memory or memories corresponding to the processor or processors, and a shared memory, which is shared by the processors, wherein control information on I/O processing or application processing is stored in the shared memory, and the processor caches a part of the control information in different storage areas on a type-by-type basis in the local memory or memories corresponding to the processor or processors in referring to the control information stored in the shared memory.
    Type: Application
    Filed: December 18, 2008
    Publication date: April 1, 2010
    Inventors: Shintaro Ito, Norio Shimozono
  • Publication number: 20090210069
    Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 20, 2009
    Inventors: Ronald E. Schultz, Scot A. Tutkovics, Richard J. Grgic, James J. Kay, James W. Kenst, Daniel W. Clark
  • Publication number: 20090172298
    Abstract: Embodiments of an invention using cached dirty bits for context switch consistency checks are disclosed. In one embodiment, a processor includes control logic and a cache. The control logic is to cause a consistency check to be performed on a subset of a plurality of state components during a first context switch. The cache is to store a dirty entry for each state component to indicate whether the corresponding state component is included in the subset.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Ki W. Yoon, Ricardo Allen
  • Publication number: 20090157969
    Abstract: A method, computer program product, and data processing system for managing a input/output buffer cache for prevention of deadlocks are disclosed. In a preferred embodiment, automatic buffer cache resizing is performed whenever the number of free buffers in the buffer cache diminishes to below a pre-defined threshold. This resizing adds a pre-defined number of additional buffers to the buffer cache, up to a pre-defined absolute maximum buffer cache size. To prevent deadlocks, an absolute minimum number of free buffers are reserved to ensure that sufficient free buffers for performing a buffer cache resize are always available. In the event that the buffer cache becomes congested and cannot be resized further, threads whose buffer demands cannot be immediately satisfied are blocked until sufficient free buffers become available.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Inventors: Matthew J. Harding, Mitchell P. Harding, Joshua D. Miers
  • Publication number: 20090089511
    Abstract: Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: SUN MICROSYSTEMS INC.
    Inventors: Brian W. O'Krafka, Pranay Koka, Robert J. Kroeger
  • Publication number: 20090083491
    Abstract: A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derrin M. Berger, Michael A. Blake, Garrett M. Drapala, Pak-kin Mak
  • Publication number: 20090070532
    Abstract: A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Inventors: Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana