Abstract: Techniques are described herein that are capable of reducing latency of changing an operating state of a processor from a low-power state to a normal-power state. For example, providing a notification from a hardware system to the processor or receiving the notification at the processor, indicating that a transaction layer packet will be provided to the processor at a future time, may trigger the processor to change the operating state from the low-power state to the normal-power state. In another example, receipt of a transaction layer packet at the processor from a hardware system may trigger the processor to change the operating state from the low-power state to the normal-power state.

Abstract: In an approach, responsibility for reissuing a fetch micro-operation is allocated to a reissue queue subsequent to a cache miss corresponding to a cache and the fetch micro-operation. Responsive to higher level cache returning data to the cache, an issue selection algorithm of the issue queue is overridden to prioritize reissuing the fetch micro-operation.

Abstract: There is provided a data processing apparatus in which receive circuitry receives a result signal from a lower level cache and a higher level cache in respect of a first instruction block. The lower level cache and the higher level cache are arranged hierarchically and transmit circuitry transmits, to the higher level cache, a query for the result signal. In response to the result signal originating from the higher level cache containing requested data, the transmit circuitry transmits a further query to the higher level cache for a subsequent instruction block at an earlier time than the further query is transmitted to the higher level cache when the result signal containing the requested data originates from the lower level cache.

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

Abstract: A cache memory includes a first cache area corresponding to even addresses, and a second cache area corresponding to odd addresses, wherein each of the first and second cache areas includes a plurality of cache sets, and each cache set includes a data set field suitable for storing data corresponding to an address among the even and odd addresses, and a pair field suitable for storing information on a location where data corresponding to an adjacent address which is adjacent to an address corresponding to the stored data is stored.

Abstract: A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

Abstract: Data tiering based on snapshots, including: receiving information describing, for data stored in a storage system, any snapshots associated with the data and any volumes storing the data; determining, from a plurality of storage tiers, a storage tier for the data based on the information; and storing the data in a storage device of the storage system associated with the storage tier.

Abstract: Embodiments of a system and method for low-latency content streaming are described. In various embodiments, multiple data fragments may be sequentially generated. Each data fragment may represent a distinct portion of media content generated from a live content source. Each data fragment may include multiple sub-portions. Furthermore, for each data fragment, generating that fragment may include sequentially generating each sub-portion of that fragment. Embodiments may include, responsive to receiving a request for a particular data fragment from a client during the generation of a particular sub-portion of that particular data fragment, providing the particular sub-portion to the client subsequent to that particular sub-portion being generated and prior to the generation of that particular data fragment being completed in order to reduce playback latency at the client relative to the live content source.

Abstract: An IC includes an array of processor units, arranged in two or more subarrays. A subarray has a test generator, a multiplexer to apply a test vector to a datapath, and a test result output. It includes one or more processor units. A test result compressor is coupled with an output of the datapath, and compresses output data to obtain a test signature, which it stores in a signature register. The signature register is legible from outside the subarray. The datapath includes one or more memories and one or more ALUs. Test data travels through the full datapath, including the memories and the ALUs. ALU control registers are overridden during test to ensure a testable datapath.

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

Abstract: In an approach to cleanup of unpredictable test results, one or more computer processors generate a data area associated with a first test instruction in a test stream. The one or more computer processors determine whether the generated data area overlaps with an unpredictable data area. In response to determining the generated data area overlaps with an unpredictable data area, the one or more computer processors determine a second test instruction associated with the overlapped unpredictable data area, where the second test instruction precedes the first test instruction in the test stream. The one or more computer processors select a location in the test stream between the first test instruction and the second test instruction. The one or more computer processors insert one or more pre-requisite instructions in the selected location, where the one or more pre-requisite instructions load the overlapped unpredictable data area with pre-defined data.

Abstract: In an approach to cleanup of unpredictable test results, one or more computer processors generate a data area associated with a first test instruction in a test stream. The one or more computer processors determine whether the generated data area overlaps with an unpredictable data area. In response to determining the generated data area overlaps with an unpredictable data area, the one or more computer processors determine a second test instruction associated with the overlapped unpredictable data area, where the second test instruction precedes the first test instruction in the test stream. The one or more computer processors select a location in the test stream between the first test instruction and the second test instruction. The one or more computer processors insert one or more pre-requisite instructions in the selected location, where the one or more pre-requisite instructions load the overlapped unpredictable data area with pre-defined data.

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit is coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor is configured to execute instruction words received on the system bus and has a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract: A system and a method for protecting the security of data stored externally to a data processing engine of a data processor using at least one secure pad memory that is mapped to internal memory of the data processing engine and to the external memory. The memory data protection system and method performs an arithmetic operation, such as a bitwise exclusive OR (“XOR”) operation, on data being read from the data processing engine or written to the external memory using data stored in secure pads of the secure pad memory, which data may be random numbers generated by a random number generator.

Abstract: A re-fetching cache memory improves efficiency of a system, for example by advantageously sharing the cache memory and/or by increasing performance. When some or all of the cache memory is temporarily used for another purpose, some or all of a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, some or all of the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the temporary use completes, optionally and/or selectively, at least some of the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or by advantageously sharing the cache memory. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and some or all of a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from some or all of the archive, and the data portion is re-fetched according to the repopulated tag portion. The re-fetching is optionally performed in a cache coherent fashion. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: A backup is performed by a client at a time when a backup server is unable to process the backup. The client maintains a cache including a root tag vector and hash entries. The client begins a backup by writing the root tag vector to a journal file and breaking files into pieces. For each piece, the client performs a hash and compares the resulting hash to entries in the cache. If the hash does not match any entries, the client records a request in the journal file to add the corresponding piece of data to an archive. After completing the backup, the journal file can be sent to the server. Before processing the journal file, the server validates the root tag vector. If the root tag vector is valid, the server processes each of the requests to add data. Otherwise, the server discards the journal file.

Abstract: A location-based caching system provides the ability for a mobile communication device to dynamically provide content related to a user's location. Content may comprise a series of map segments that anticipate the route traveled by a user of the mobile device. Other related content may also be provided, for example, point of interest information related to the route traveled. The system tracks a present location of the mobile device and predicts a future location of the mobile device. Based upon the prediction of future location, the caching module determines whether content related to the future location is presently stored on the mobile device. If appropriate content is not on the mobile device, the caching module retrieves the content from a content server via a network connection. The content information nay be contextually selected based upon, for example, user preferences, movement information, and device state information.

Abstract: A method and a computing system are provided. The computing system may include a system memory configured to store data in a first data format. The computing system may also include a computational core comprising a plurality of execution units (EU). The computational core may be configured to request data from the system memory and to process data in a second data format. Each of the plurality of EU may include an execution control and datapath and a specialized L1 cache pool. The computing system may include a multipurpose L2 cache in communication with the each of the plurality of EU and the system memory. The multipurpose L2 cache may be configured to store data in the first data format and the second data format. The computing system may also include an orthogonal data converter in communication with at least one of the plurality of EU and the system memory.